arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_common_data.h"
  19
  20 #include "control.h"
  21 #include "cm33xx.h"
  22 #include "prm33xx.h"
  23 #include "prm-regbits-33xx.h"
  24 #include "omap_hwmod_33xx_43xx_common_data.h"
  25
  26 /*
  27  * IP blocks
  28  */
  29
  30 /* emif */
  31 static struct omap_hwmod am33xx_emif_hwmod = {
  32         .name           = "emif",
  33         .class          = &am33xx_emif_hwmod_class,
  34         .clkdm_name     = "l3_clkdm",
  35         .flags          = HWMOD_INIT_NO_IDLE,
  36         .main_clk       = "dpll_ddr_m2_div2_ck",
  37         .prcm           = {
  38                 .omap4  = {
  39                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  40                         .modulemode     = MODULEMODE_SWCTRL,
  41                 },
  42         },
  43 };
  44
  45 /* l4_hs */
  46 static struct omap_hwmod am33xx_l4_hs_hwmod = {
  47         .name           = "l4_hs",
  48         .class          = &am33xx_l4_hwmod_class,
  49         .clkdm_name     = "l4hs_clkdm",
  50         .flags          = HWMOD_INIT_NO_IDLE,
  51         .main_clk       = "l4hs_gclk",
  52         .prcm           = {
  53                 .omap4  = {
  54                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  55                         .modulemode     = MODULEMODE_SWCTRL,
  56                 },
  57         },
  58 };
  59
  60 /*
  61  * Modules omap_hwmod structures
  62  *
  63  * The following IPs are excluded for the moment because:
  64  * - They do not need an explicit SW control using omap_hwmod API.
  65  * - They still need to be validated with the driver
  66  *   properly adapted to omap_hwmod / omap_device
  67  *
  68  *    - cEFUSE (doesn't fall under any ocp_if)
  69  *    - clkdiv32k
  70  *    - ocp watch point
  71  */
  72 #if 0
  73 /*
  74  * 'cefuse' class
  75  */
  76 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
  77         .name           = "cefuse",
  78 };
  79
  80 static struct omap_hwmod am33xx_cefuse_hwmod = {
  81         .name           = "cefuse",
  82         .class          = &am33xx_cefuse_hwmod_class,
  83         .clkdm_name     = "l4_cefuse_clkdm",
  84         .main_clk       = "cefuse_fck",
  85         .prcm           = {
  86                 .omap4  = {
  87                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
  88                         .modulemode     = MODULEMODE_SWCTRL,
  89                 },
  90         },
  91 };
  92
  93 /*
  94  * 'clkdiv32k' class
  95  */
  96 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
  97         .name           = "clkdiv32k",
  98 };
  99
 100 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 101         .name           = "clkdiv32k",
 102         .class          = &am33xx_clkdiv32k_hwmod_class,
 103         .clkdm_name     = "clk_24mhz_clkdm",
 104         .main_clk       = "clkdiv32k_ick",
 105         .prcm           = {
 106                 .omap4  = {
 107                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 108                         .modulemode     = MODULEMODE_SWCTRL,
 109                 },
 110         },
 111 };
 112
 113 /* ocpwp */
 114 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 115         .name           = "ocpwp",
 116 };
 117
 118 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 119         .name           = "ocpwp",
 120         .class          = &am33xx_ocpwp_hwmod_class,
 121         .clkdm_name     = "l4ls_clkdm",
 122         .main_clk       = "l4ls_gclk",
 123         .prcm           = {
 124                 .omap4  = {
 125                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 126                         .modulemode     = MODULEMODE_SWCTRL,
 127                 },
 128         },
 129 };
 130 #endif
 131
 132 /*
 133  * 'debugss' class
 134  * debug sub system
 135  */
 136 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
 137         { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
 138         { .role = "dbg_clka", .clk = "dbg_clka_ck" },
 139 };
 140
 141 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 142         .name           = "debugss",
 143 };
 144
 145 static struct omap_hwmod am33xx_debugss_hwmod = {
 146         .name           = "debugss",
 147         .class          = &am33xx_debugss_hwmod_class,
 148         .clkdm_name     = "l3_aon_clkdm",
 149         .main_clk       = "trace_clk_div_ck",
 150         .prcm           = {
 151                 .omap4  = {
 152                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 153                         .modulemode     = MODULEMODE_SWCTRL,
 154                 },
 155         },
 156         .opt_clks       = debugss_opt_clks,
 157         .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
 158 };
 159
 160 /*
 161  * Interfaces
 162  */
 163
 164 /* l3 main -> emif */
 165 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
 166         .master         = &am33xx_l3_main_hwmod,
 167         .slave          = &am33xx_emif_hwmod,
 168         .clk            = "dpll_core_m4_ck",
 169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 170 };
 171
 172 /* l3 main -> l4 hs */
 173 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
 174         .master         = &am33xx_l3_main_hwmod,
 175         .slave          = &am33xx_l4_hs_hwmod,
 176         .clk            = "l3s_gclk",
 177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 178 };
 179
 180 /* l3_main -> debugss */
 181 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
 182         .master         = &am33xx_l3_main_hwmod,
 183         .slave          = &am33xx_debugss_hwmod,
 184         .clk            = "dpll_core_m4_ck",
 185         .user           = OCP_USER_MPU,
 186 };
 187
 188 /* l4 wkup -> smartreflex0 */
 189 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
 190         .master         = &am33xx_l4_wkup_hwmod,
 191         .slave          = &am33xx_smartreflex0_hwmod,
 192         .clk            = "dpll_core_m4_div2_ck",
 193         .user           = OCP_USER_MPU,
 194 };
 195
 196 /* l4 wkup -> smartreflex1 */
 197 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
 198         .master         = &am33xx_l4_wkup_hwmod,
 199         .slave          = &am33xx_smartreflex1_hwmod,
 200         .clk            = "dpll_core_m4_div2_ck",
 201         .user           = OCP_USER_MPU,
 202 };
 203
 204 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 205         &am33xx_l3_main__emif,
 206         &am33xx_mpu__l3_main,
 207         &am33xx_mpu__prcm,
 208         &am33xx_l3_s__l4_ls,
 209         &am33xx_l3_s__l4_wkup,
 210         &am33xx_l3_main__l4_hs,
 211         &am33xx_l3_main__l3_s,
 212         &am33xx_l3_main__l3_instr,
 213         &am33xx_l3_s__l3_main,
 214         &am33xx_l3_main__debugss,
 215         &am33xx_l4_wkup__smartreflex0,
 216         &am33xx_l4_wkup__smartreflex1,
 217         &am33xx_l3_main__ocmc,
 218         NULL,
 219 };
 220
 221 int __init am33xx_hwmod_init(void)
 222 {
 223         omap_hwmod_am33xx_reg();
 224         omap_hwmod_init();
 225         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
 226 }