arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/omap-dma.h>
  14
  15 #include "omap_hwmod.h"
  16 #include "omap_hwmod_common_data.h"
  17 #include "cm-regbits-24xx.h"
  18 #include "prm-regbits-24xx.h"
  19 #include "wd_timer.h"
  20
  21 /*
  22  * 'dispc' class
  23  * display controller
  24  */
  25
  26 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  27         .rev_offs       = 0x0000,
  28         .sysc_offs      = 0x0010,
  29         .syss_offs      = 0x0014,
  30         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  31                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  32         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  33                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  34         .sysc_fields    = &omap_hwmod_sysc_type1,
  35 };
  36
  37 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  38         .name   = "dispc",
  39         .sysc   = &omap2_dispc_sysc,
  40 };
  41
  42 /* OMAP2xxx Timer Common */
  43 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  44         .rev_offs       = 0x0000,
  45         .sysc_offs      = 0x0010,
  46         .syss_offs      = 0x0014,
  47         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  48                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  49                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  50         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  51         .sysc_fields    = &omap_hwmod_sysc_type1,
  52 };
  53
  54 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  55         .name   = "timer",
  56         .sysc   = &omap2xxx_timer_sysc,
  57 };
  58
  59 /*
  60  * 'wd_timer' class
  61  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  62  * overflow condition
  63  */
  64
  65 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  66         .rev_offs       = 0x0000,
  67         .sysc_offs      = 0x0010,
  68         .syss_offs      = 0x0014,
  69         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  70                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  71         .sysc_fields    = &omap_hwmod_sysc_type1,
  72 };
  73
  74 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  75         .name           = "wd_timer",
  76         .sysc           = &omap2xxx_wd_timer_sysc,
  77         .pre_shutdown   = &omap2_wd_timer_disable,
  78         .reset          = &omap2_wd_timer_reset,
  79 };
  80
  81 /*
  82  * 'gpio' class
  83  * general purpose io module
  84  */
  85 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  86         .rev_offs       = 0x0000,
  87         .sysc_offs      = 0x0010,
  88         .syss_offs      = 0x0014,
  89         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  90                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  91                            SYSS_HAS_RESET_STATUS),
  92         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  93         .sysc_fields    = &omap_hwmod_sysc_type1,
  94 };
  95
  96 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
  97         .name = "gpio",
  98         .sysc = &omap2xxx_gpio_sysc,
  99 };
 100
 101 /* system dma */
 102 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 103         .rev_offs       = 0x0000,
 104         .sysc_offs      = 0x002c,
 105         .syss_offs      = 0x0028,
 106         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 107                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 108                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 109         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 110         .sysc_fields    = &omap_hwmod_sysc_type1,
 111 };
 112
 113 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 114         .name   = "dma",
 115         .sysc   = &omap2xxx_dma_sysc,
 116 };
 117
 118 /*
 119  * 'mailbox' class
 120  * mailbox module allowing communication between the on-chip processors
 121  * using a queued mailbox-interrupt mechanism.
 122  */
 123
 124 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 125         .rev_offs       = 0x000,
 126         .sysc_offs      = 0x010,
 127         .syss_offs      = 0x014,
 128         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 129                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 130         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 131         .sysc_fields    = &omap_hwmod_sysc_type1,
 132 };
 133
 134 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 135         .name   = "mailbox",
 136         .sysc   = &omap2xxx_mailbox_sysc,
 137 };
 138
 139 /*
 140  * 'mcspi' class
 141  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 142  * bus
 143  */
 144
 145 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 146         .rev_offs       = 0x0000,
 147         .sysc_offs      = 0x0010,
 148         .syss_offs      = 0x0014,
 149         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 150                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 151                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 153         .sysc_fields    = &omap_hwmod_sysc_type1,
 154 };
 155
 156 struct omap_hwmod_class omap2xxx_mcspi_class = {
 157         .name   = "mcspi",
 158         .sysc   = &omap2xxx_mcspi_sysc,
 159 };
 160
 161 /*
 162  * 'gpmc' class
 163  * general purpose memory controller
 164  */
 165
 166 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 167         .rev_offs       = 0x0000,
 168         .sysc_offs      = 0x0010,
 169         .syss_offs      = 0x0014,
 170         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 171                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 172         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 173         .sysc_fields    = &omap_hwmod_sysc_type1,
 174 };
 175
 176 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 177         .name   = "gpmc",
 178         .sysc   = &omap2xxx_gpmc_sysc,
 179 };
 180
 181 /*
 182  * IP blocks
 183  */
 184
 185 /* L3 */
 186 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 187         .name           = "l3_main",
 188         .class          = &l3_hwmod_class,
 189         .flags          = HWMOD_NO_IDLEST,
 190 };
 191
 192 /* L4 CORE */
 193 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 194         .name           = "l4_core",
 195         .class          = &l4_hwmod_class,
 196         .flags          = HWMOD_NO_IDLEST,
 197 };
 198
 199 /* L4 WKUP */
 200 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 201         .name           = "l4_wkup",
 202         .class          = &l4_hwmod_class,
 203         .flags          = HWMOD_NO_IDLEST,
 204 };
 205
 206 /* MPU */
 207 struct omap_hwmod omap2xxx_mpu_hwmod = {
 208         .name           = "mpu",
 209         .class          = &mpu_hwmod_class,
 210         .main_clk       = "mpu_ck",
 211 };
 212
 213 /* IVA2 */
 214 struct omap_hwmod omap2xxx_iva_hwmod = {
 215         .name           = "iva",
 216         .class          = &iva_hwmod_class,
 217 };
 218
 219 /* timer1 */
 220 struct omap_hwmod omap2xxx_timer1_hwmod = {
 221         .name           = "timer1",
 222         .main_clk       = "gpt1_fck",
 223         .prcm           = {
 224                 .omap2 = {
 225                         .module_offs = WKUP_MOD,
 226                         .idlest_reg_id = 1,
 227                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 228                 },
 229         },
 230         .class          = &omap2xxx_timer_hwmod_class,
 231         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 232 };
 233
 234 /* timer2 */
 235 struct omap_hwmod omap2xxx_timer2_hwmod = {
 236         .name           = "timer2",
 237         .main_clk       = "gpt2_fck",
 238         .prcm           = {
 239                 .omap2 = {
 240                         .module_offs = CORE_MOD,
 241                         .idlest_reg_id = 1,
 242                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 243                 },
 244         },
 245         .class          = &omap2xxx_timer_hwmod_class,
 246         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 247 };
 248
 249 /* timer3 */
 250 struct omap_hwmod omap2xxx_timer3_hwmod = {
 251         .name           = "timer3",
 252         .main_clk       = "gpt3_fck",
 253         .prcm           = {
 254                 .omap2 = {
 255                         .module_offs = CORE_MOD,
 256                         .idlest_reg_id = 1,
 257                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 258                 },
 259         },
 260         .class          = &omap2xxx_timer_hwmod_class,
 261         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 262 };
 263
 264 /* timer4 */
 265 struct omap_hwmod omap2xxx_timer4_hwmod = {
 266         .name           = "timer4",
 267         .main_clk       = "gpt4_fck",
 268         .prcm           = {
 269                 .omap2 = {
 270                         .module_offs = CORE_MOD,
 271                         .idlest_reg_id = 1,
 272                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 273                 },
 274         },
 275         .class          = &omap2xxx_timer_hwmod_class,
 276         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 277 };
 278
 279 /* timer5 */
 280 struct omap_hwmod omap2xxx_timer5_hwmod = {
 281         .name           = "timer5",
 282         .main_clk       = "gpt5_fck",
 283         .prcm           = {
 284                 .omap2 = {
 285                         .module_offs = CORE_MOD,
 286                         .idlest_reg_id = 1,
 287                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 288                 },
 289         },
 290         .class          = &omap2xxx_timer_hwmod_class,
 291         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 292 };
 293
 294 /* timer6 */
 295 struct omap_hwmod omap2xxx_timer6_hwmod = {
 296         .name           = "timer6",
 297         .main_clk       = "gpt6_fck",
 298         .prcm           = {
 299                 .omap2 = {
 300                         .module_offs = CORE_MOD,
 301                         .idlest_reg_id = 1,
 302                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 303                 },
 304         },
 305         .class          = &omap2xxx_timer_hwmod_class,
 306         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 307 };
 308
 309 /* timer7 */
 310 struct omap_hwmod omap2xxx_timer7_hwmod = {
 311         .name           = "timer7",
 312         .main_clk       = "gpt7_fck",
 313         .prcm           = {
 314                 .omap2 = {
 315                         .module_offs = CORE_MOD,
 316                         .idlest_reg_id = 1,
 317                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 318                 },
 319         },
 320         .class          = &omap2xxx_timer_hwmod_class,
 321         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 322 };
 323
 324 /* timer8 */
 325 struct omap_hwmod omap2xxx_timer8_hwmod = {
 326         .name           = "timer8",
 327         .main_clk       = "gpt8_fck",
 328         .prcm           = {
 329                 .omap2 = {
 330                         .module_offs = CORE_MOD,
 331                         .idlest_reg_id = 1,
 332                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 333                 },
 334         },
 335         .class          = &omap2xxx_timer_hwmod_class,
 336         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 337 };
 338
 339 /* timer9 */
 340 struct omap_hwmod omap2xxx_timer9_hwmod = {
 341         .name           = "timer9",
 342         .main_clk       = "gpt9_fck",
 343         .prcm           = {
 344                 .omap2 = {
 345                         .module_offs = CORE_MOD,
 346                         .idlest_reg_id = 1,
 347                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 348                 },
 349         },
 350         .class          = &omap2xxx_timer_hwmod_class,
 351         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 352 };
 353
 354 /* timer10 */
 355 struct omap_hwmod omap2xxx_timer10_hwmod = {
 356         .name           = "timer10",
 357         .main_clk       = "gpt10_fck",
 358         .prcm           = {
 359                 .omap2 = {
 360                         .module_offs = CORE_MOD,
 361                         .idlest_reg_id = 1,
 362                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 363                 },
 364         },
 365         .class          = &omap2xxx_timer_hwmod_class,
 366         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 367 };
 368
 369 /* timer11 */
 370 struct omap_hwmod omap2xxx_timer11_hwmod = {
 371         .name           = "timer11",
 372         .main_clk       = "gpt11_fck",
 373         .prcm           = {
 374                 .omap2 = {
 375                         .module_offs = CORE_MOD,
 376                         .idlest_reg_id = 1,
 377                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 378                 },
 379         },
 380         .class          = &omap2xxx_timer_hwmod_class,
 381         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 382 };
 383
 384 /* timer12 */
 385 struct omap_hwmod omap2xxx_timer12_hwmod = {
 386         .name           = "timer12",
 387         .main_clk       = "gpt12_fck",
 388         .prcm           = {
 389                 .omap2 = {
 390                         .module_offs = CORE_MOD,
 391                         .idlest_reg_id = 1,
 392                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 393                 },
 394         },
 395         .class          = &omap2xxx_timer_hwmod_class,
 396         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 397 };
 398
 399 /* wd_timer2 */
 400 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 401         .name           = "wd_timer2",
 402         .class          = &omap2xxx_wd_timer_hwmod_class,
 403         .main_clk       = "mpu_wdt_fck",
 404         .prcm           = {
 405                 .omap2 = {
 406                         .module_offs = WKUP_MOD,
 407                         .idlest_reg_id = 1,
 408                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 409                 },
 410         },
 411 };
 412
 413 /* UART1 */
 414
 415 struct omap_hwmod omap2xxx_uart1_hwmod = {
 416         .name           = "uart1",
 417         .main_clk       = "uart1_fck",
 418         .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 419         .prcm           = {
 420                 .omap2 = {
 421                         .module_offs = CORE_MOD,
 422                         .idlest_reg_id = 1,
 423                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 424                 },
 425         },
 426         .class          = &omap2_uart_class,
 427 };
 428
 429 /* UART2 */
 430
 431 struct omap_hwmod omap2xxx_uart2_hwmod = {
 432         .name           = "uart2",
 433         .main_clk       = "uart2_fck",
 434         .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 435         .prcm           = {
 436                 .omap2 = {
 437                         .module_offs = CORE_MOD,
 438                         .idlest_reg_id = 1,
 439                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 440                 },
 441         },
 442         .class          = &omap2_uart_class,
 443 };
 444
 445 /* UART3 */
 446
 447 struct omap_hwmod omap2xxx_uart3_hwmod = {
 448         .name           = "uart3",
 449         .main_clk       = "uart3_fck",
 450         .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 451         .prcm           = {
 452                 .omap2 = {
 453                         .module_offs = CORE_MOD,
 454                         .idlest_reg_id = 2,
 455                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 456                 },
 457         },
 458         .class          = &omap2_uart_class,
 459 };
 460
 461 /* dss */
 462
 463 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 464         /*
 465          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 466          * driver does not use these clocks.
 467          */
 468         { .role = "tv_clk", .clk = "dss_54m_fck" },
 469         { .role = "sys_clk", .clk = "dss2_fck" },
 470 };
 471
 472 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 473         .name           = "dss_core",
 474         .class          = &omap2_dss_hwmod_class,
 475         .main_clk       = "dss1_fck", /* instead of dss_fck */
 476         .prcm           = {
 477                 .omap2 = {
 478                         .module_offs = CORE_MOD,
 479                         .idlest_reg_id = 1,
 480                 },
 481         },
 482         .opt_clks       = dss_opt_clks,
 483         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 484         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 485 };
 486
 487 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 488         .name           = "dss_dispc",
 489         .class          = &omap2_dispc_hwmod_class,
 490         .main_clk       = "dss1_fck",
 491         .prcm           = {
 492                 .omap2 = {
 493                         .module_offs = CORE_MOD,
 494                         .idlest_reg_id = 1,
 495                 },
 496         },
 497         .flags          = HWMOD_NO_IDLEST,
 498         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 499 };
 500
 501 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 502         { .role = "ick", .clk = "dss_ick" },
 503 };
 504
 505 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 506         .name           = "dss_rfbi",
 507         .class          = &omap2_rfbi_hwmod_class,
 508         .main_clk       = "dss1_fck",
 509         .prcm           = {
 510                 .omap2 = {
 511                         .module_offs = CORE_MOD,
 512                 },
 513         },
 514         .opt_clks       = dss_rfbi_opt_clks,
 515         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 516         .flags          = HWMOD_NO_IDLEST,
 517 };
 518
 519 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 520         .name           = "dss_venc",
 521         .class          = &omap2_venc_hwmod_class,
 522         .main_clk       = "dss_54m_fck",
 523         .prcm           = {
 524                 .omap2 = {
 525                         .module_offs = CORE_MOD,
 526                 },
 527         },
 528         .flags          = HWMOD_NO_IDLEST,
 529 };
 530
 531 /* gpio1 */
 532 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 533         .name           = "gpio1",
 534         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 535         .main_clk       = "gpios_fck",
 536         .prcm           = {
 537                 .omap2 = {
 538                         .module_offs = WKUP_MOD,
 539                         .idlest_reg_id = 1,
 540                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 541                 },
 542         },
 543         .class          = &omap2xxx_gpio_hwmod_class,
 544 };
 545
 546 /* gpio2 */
 547 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 548         .name           = "gpio2",
 549         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 550         .main_clk       = "gpios_fck",
 551         .prcm           = {
 552                 .omap2 = {
 553                         .module_offs = WKUP_MOD,
 554                         .idlest_reg_id = 1,
 555                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 556                 },
 557         },
 558         .class          = &omap2xxx_gpio_hwmod_class,
 559 };
 560
 561 /* gpio3 */
 562 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 563         .name           = "gpio3",
 564         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 565         .main_clk       = "gpios_fck",
 566         .prcm           = {
 567                 .omap2 = {
 568                         .module_offs = WKUP_MOD,
 569                         .idlest_reg_id = 1,
 570                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 571                 },
 572         },
 573         .class          = &omap2xxx_gpio_hwmod_class,
 574 };
 575
 576 /* gpio4 */
 577 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 578         .name           = "gpio4",
 579         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 580         .main_clk       = "gpios_fck",
 581         .prcm           = {
 582                 .omap2 = {
 583                         .module_offs = WKUP_MOD,
 584                         .idlest_reg_id = 1,
 585                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 586                 },
 587         },
 588         .class          = &omap2xxx_gpio_hwmod_class,
 589 };
 590
 591 /* mcspi1 */
 592 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 593         .name           = "mcspi1",
 594         .main_clk       = "mcspi1_fck",
 595         .prcm           = {
 596                 .omap2 = {
 597                         .module_offs = CORE_MOD,
 598                         .idlest_reg_id = 1,
 599                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 600                 },
 601         },
 602         .class          = &omap2xxx_mcspi_class,
 603 };
 604
 605 /* mcspi2 */
 606 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 607         .name           = "mcspi2",
 608         .main_clk       = "mcspi2_fck",
 609         .prcm           = {
 610                 .omap2 = {
 611                         .module_offs = CORE_MOD,
 612                         .idlest_reg_id = 1,
 613                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 614                 },
 615         },
 616         .class          = &omap2xxx_mcspi_class,
 617 };
 618
 619 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 620         .name   = "counter",
 621 };
 622
 623 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 624         .name           = "counter_32k",
 625         .main_clk       = "func_32k_ck",
 626         .prcm           = {
 627                 .omap2  = {
 628                         .module_offs = WKUP_MOD,
 629                         .idlest_reg_id = 1,
 630                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 631                 },
 632         },
 633         .class          = &omap2xxx_counter_hwmod_class,
 634 };
 635
 636 /* gpmc */
 637 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 638         .name           = "gpmc",
 639         .class          = &omap2xxx_gpmc_hwmod_class,
 640         .main_clk       = "gpmc_fck",
 641         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 642         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 643         .prcm           = {
 644                 .omap2  = {
 645                         .module_offs = CORE_MOD,
 646                 },
 647         },
 648 };
 649
 650 /* RNG */
 651
 652 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 653         .rev_offs       = 0x3c,
 654         .sysc_offs      = 0x40,
 655         .syss_offs      = 0x44,
 656         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 657                            SYSS_HAS_RESET_STATUS),
 658         .sysc_fields    = &omap_hwmod_sysc_type1,
 659 };
 660
 661 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 662         .name           = "rng",
 663         .sysc           = &omap2_rng_sysc,
 664 };
 665
 666 struct omap_hwmod omap2xxx_rng_hwmod = {
 667         .name           = "rng",
 668         .main_clk       = "l4_ck",
 669         .prcm           = {
 670                 .omap2 = {
 671                         .module_offs = CORE_MOD,
 672                         .idlest_reg_id = 4,
 673                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 674                 },
 675         },
 676         /*
 677          * XXX The first read from the SYSSTATUS register of the RNG
 678          * after the SYSCONFIG SOFTRESET bit is set triggers an
 679          * imprecise external abort.  It's unclear why this happens.
 680          * Until this is analyzed, skip the IP block reset.
 681          */
 682         .flags          = HWMOD_INIT_NO_RESET,
 683         .class          = &omap2_rng_hwmod_class,
 684 };
 685
 686 /* SHAM */
 687
 688 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
 689         .rev_offs       = 0x5c,
 690         .sysc_offs      = 0x60,
 691         .syss_offs      = 0x64,
 692         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 693                            SYSS_HAS_RESET_STATUS),
 694         .sysc_fields    = &omap_hwmod_sysc_type1,
 695 };
 696
 697 static struct omap_hwmod_class omap2xxx_sham_class = {
 698         .name   = "sham",
 699         .sysc   = &omap2_sham_sysc,
 700 };
 701
 702 struct omap_hwmod omap2xxx_sham_hwmod = {
 703         .name           = "sham",
 704         .main_clk       = "l4_ck",
 705         .prcm           = {
 706                 .omap2 = {
 707                         .module_offs = CORE_MOD,
 708                         .idlest_reg_id = 4,
 709                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
 710                 },
 711         },
 712         .class          = &omap2xxx_sham_class,
 713 };
 714
 715 /* AES */
 716
 717 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
 718         .rev_offs       = 0x44,
 719         .sysc_offs      = 0x48,
 720         .syss_offs      = 0x4c,
 721         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 722                            SYSS_HAS_RESET_STATUS),
 723         .sysc_fields    = &omap_hwmod_sysc_type1,
 724 };
 725
 726 static struct omap_hwmod_class omap2xxx_aes_class = {
 727         .name   = "aes",
 728         .sysc   = &omap2_aes_sysc,
 729 };
 730
 731 struct omap_hwmod omap2xxx_aes_hwmod = {
 732         .name           = "aes",
 733         .main_clk       = "l4_ck",
 734         .prcm           = {
 735                 .omap2 = {
 736                         .module_offs = CORE_MOD,
 737                         .idlest_reg_id = 4,
 738                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
 739                 },
 740         },
 741         .class          = &omap2xxx_aes_class,
 742 };