1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Secondary CPU startup routine source file.
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * Interface functions needed for the SMP. This file is based on arm
11 * realview smp platform.
12 * Copyright (c) 2003 ARM Limited.
15 #include <linux/linkage.h>
16 #include <linux/init.h>
17 #include <asm/assembler.h>
21 /* Physical address needed since MMU not enabled yet on secondary core */
22 #define AUX_CORE_BOOT0_PA 0x48281800
23 #define API_HYP_ENTRY 0x102
25 ENTRY(omap_secondary_startup)
29 /* Should never get here */
33 #ENDPROC(omap_secondary_startup)
36 * OMAP5 specific entry point for secondary CPU to jump from ROM
37 * code. This routine also provides a holding flag into which
38 * secondary core is held until we're ready for it to initialise.
39 * The primary core will update this flag using a hardware
40 * register AuxCoreBoot0.
42 ENTRY(omap5_secondary_startup)
43 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
46 mrc p15, 0, r4, c0, c0, 5
50 b omap_secondary_startup
51 ENDPROC(omap5_secondary_startup)
53 * Same as omap5_secondary_startup except we call into the ROM to
54 * enable HYP mode first. This is called instead of
55 * omap5_secondary_startup if the primary CPU was put into HYP mode by
58 ENTRY(omap5_secondary_hyp_startup)
59 wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
62 mrc p15, 0, r4, c0, c0, 5
66 ldr r12, =API_HYP_ENTRY
70 b omap_secondary_startup
71 ENDPROC(omap5_secondary_hyp_startup)
73 * OMAP4 specific entry point for secondary CPU to jump from ROM
74 * code. This routine also provides a holding flag into which
75 * secondary core is held until we're ready for it to initialise.
76 * The primary core will update this flag using a hardware
77 * register AuxCoreBoot0.
79 ENTRY(omap4_secondary_startup)
82 smc #0 @ read from AuxCoreBoot0
84 mrc p15, 0, r4, c0, c0, 5
90 * we've been released from the wait loop,secondary_stack
91 * should now contain the SVC stack for this core
93 b omap_secondary_startup
94 ENDPROC(omap4_secondary_startup)
96 ENTRY(omap4460_secondary_startup)
97 hold_2: ldr r12,=0x103
99 smc #0 @ read from AuxCoreBoot0
101 mrc p15, 0, r4, c0, c0, 5
107 * GIC distributor control register has changed between
108 * CortexA9 r1pX and r2pX. The Control Register secure
109 * banked version is now composed of 2 bits:
110 * bit 0 == Secure Enable
111 * bit 1 == Non-Secure Enable
112 * The Non-Secure banked register has not changed
113 * Because the ROM Code is based on the r1pX GIC, the CPU1
114 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
115 * The workaround must be:
116 * 1) Before doing the CPU1 wakeup, CPU0 must disable
117 * the GIC distributor
118 * 2) CPU1 must re-enable the GIC distributor on
121 ldr r1, =OMAP44XX_GIC_DIST_BASE
127 * we've been released from the wait loop,secondary_stack
128 * should now contain the SVC stack for this core
130 b omap_secondary_startup
131 ENDPROC(omap4460_secondary_startup)