2 * linux/arch/arm/mach-omap2/mcbsp.c
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Multichannel mode not supported.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
21 #include <mach/irqs.h>
25 #include <plat/mcbsp.h>
27 static void omap2_mcbsp2_mux_setup(void)
29 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
30 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
31 omap_cfg_reg(W15_24XX_MCBSP2_DR);
32 omap_cfg_reg(V15_24XX_MCBSP2_DX);
33 omap_cfg_reg(V14_24XX_GPIO117);
35 * TODO: Need to add MUX settings for OMAP 2430 SDP
39 static void omap2_mcbsp_request(unsigned int id)
41 if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
42 omap2_mcbsp2_mux_setup();
45 static struct omap_mcbsp_ops omap2_mcbsp_ops = {
46 .request = omap2_mcbsp_request,
49 #ifdef CONFIG_ARCH_OMAP2420
50 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
52 .phys_base = OMAP24XX_MCBSP1_BASE,
53 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
54 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
55 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
56 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
57 .ops = &omap2_mcbsp_ops,
60 .phys_base = OMAP24XX_MCBSP2_BASE,
61 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
62 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
63 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
64 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
65 .ops = &omap2_mcbsp_ops,
68 #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
69 #define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
71 #define omap2420_mcbsp_pdata NULL
72 #define OMAP2420_MCBSP_PDATA_SZ 0
73 #define OMAP2420_MCBSP_REG_NUM 0
76 #ifdef CONFIG_ARCH_OMAP2430
77 static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
79 .phys_base = OMAP24XX_MCBSP1_BASE,
80 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
81 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
82 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
83 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
84 .ops = &omap2_mcbsp_ops,
87 .phys_base = OMAP24XX_MCBSP2_BASE,
88 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
89 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
90 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
91 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
92 .ops = &omap2_mcbsp_ops,
95 .phys_base = OMAP2430_MCBSP3_BASE,
96 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
97 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
98 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
99 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
100 .ops = &omap2_mcbsp_ops,
103 .phys_base = OMAP2430_MCBSP4_BASE,
104 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
105 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
106 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
107 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
108 .ops = &omap2_mcbsp_ops,
111 .phys_base = OMAP2430_MCBSP5_BASE,
112 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
113 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
114 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
115 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
116 .ops = &omap2_mcbsp_ops,
119 #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
120 #define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
122 #define omap2430_mcbsp_pdata NULL
123 #define OMAP2430_MCBSP_PDATA_SZ 0
124 #define OMAP2430_MCBSP_REG_NUM 0
127 #ifdef CONFIG_ARCH_OMAP3
128 static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
130 .phys_base = OMAP34XX_MCBSP1_BASE,
131 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
132 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
133 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
134 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
135 .ops = &omap2_mcbsp_ops,
139 .phys_base = OMAP34XX_MCBSP2_BASE,
140 .phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
141 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
142 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
143 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
144 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
145 .ops = &omap2_mcbsp_ops,
146 .buffer_size = 0x3FF,
149 .phys_base = OMAP34XX_MCBSP3_BASE,
150 .phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
151 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
152 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
153 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
154 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
155 .ops = &omap2_mcbsp_ops,
159 .phys_base = OMAP34XX_MCBSP4_BASE,
160 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
161 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
162 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
163 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
164 .ops = &omap2_mcbsp_ops,
168 .phys_base = OMAP34XX_MCBSP5_BASE,
169 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
170 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
171 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
172 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
173 .ops = &omap2_mcbsp_ops,
177 #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
178 #define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
180 #define omap34xx_mcbsp_pdata NULL
181 #define OMAP34XX_MCBSP_PDATA_SZ 0
182 #define OMAP34XX_MCBSP_REG_NUM 0
185 static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
187 .phys_base = OMAP44XX_MCBSP1_BASE,
188 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
189 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
190 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
191 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
192 .ops = &omap2_mcbsp_ops,
195 .phys_base = OMAP44XX_MCBSP2_BASE,
196 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
197 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
198 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
199 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
200 .ops = &omap2_mcbsp_ops,
203 .phys_base = OMAP44XX_MCBSP3_BASE,
204 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
205 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
206 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
207 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
208 .ops = &omap2_mcbsp_ops,
211 .phys_base = OMAP44XX_MCBSP4_BASE,
212 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
213 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
214 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
215 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
216 .ops = &omap2_mcbsp_ops,
219 #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
220 #define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
222 static int __init omap2_mcbsp_init(void)
224 if (cpu_is_omap2420()) {
225 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
226 omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
227 } else if (cpu_is_omap2430()) {
228 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
229 omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
230 } else if (cpu_is_omap34xx()) {
231 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
232 omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
233 } else if (cpu_is_omap44xx()) {
234 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
235 omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
238 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
243 if (cpu_is_omap2420())
244 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
245 OMAP2420_MCBSP_PDATA_SZ);
246 if (cpu_is_omap2430())
247 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
248 OMAP2430_MCBSP_PDATA_SZ);
249 if (cpu_is_omap34xx())
250 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
251 OMAP34XX_MCBSP_PDATA_SZ);
252 if (cpu_is_omap44xx())
253 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
254 OMAP44XX_MCBSP_PDATA_SZ);
256 return omap_mcbsp_init();
258 arch_initcall(omap2_mcbsp_init);