2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/clk.h>
25 #include <linux/omapfb.h>
29 #include <asm/mach/map.h>
31 #include <plat/sram.h>
32 #include <plat/sdrc.h>
33 #include <plat/gpmc.h>
34 #include <plat/serial.h>
36 #include "clock2xxx.h"
37 #include "clock3xxx.h"
38 #include "clock44xx.h"
41 #include <plat/omap-pm.h>
42 #include <plat/powerdomain.h>
44 #include <plat/clockdomain.h>
45 #include <plat/omap_hwmod.h>
46 #include <plat/multi.h>
49 * The machine specific code may provide the extra mapping besides the
50 * default mapping provided here.
53 #ifdef CONFIG_ARCH_OMAP2
54 static struct map_desc omap24xx_io_desc[] __initdata = {
56 .virtual = L3_24XX_VIRT,
57 .pfn = __phys_to_pfn(L3_24XX_PHYS),
58 .length = L3_24XX_SIZE,
62 .virtual = L4_24XX_VIRT,
63 .pfn = __phys_to_pfn(L4_24XX_PHYS),
64 .length = L4_24XX_SIZE,
69 #ifdef CONFIG_ARCH_OMAP2420
70 static struct map_desc omap242x_io_desc[] __initdata = {
72 .virtual = DSP_MEM_2420_VIRT,
73 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
74 .length = DSP_MEM_2420_SIZE,
78 .virtual = DSP_IPI_2420_VIRT,
79 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
80 .length = DSP_IPI_2420_SIZE,
84 .virtual = DSP_MMU_2420_VIRT,
85 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
86 .length = DSP_MMU_2420_SIZE,
93 #ifdef CONFIG_ARCH_OMAP2430
94 static struct map_desc omap243x_io_desc[] __initdata = {
96 .virtual = L4_WK_243X_VIRT,
97 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
98 .length = L4_WK_243X_SIZE,
102 .virtual = OMAP243X_GPMC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
104 .length = OMAP243X_GPMC_SIZE,
108 .virtual = OMAP243X_SDRC_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
110 .length = OMAP243X_SDRC_SIZE,
114 .virtual = OMAP243X_SMS_VIRT,
115 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
116 .length = OMAP243X_SMS_SIZE,
123 #ifdef CONFIG_ARCH_OMAP3
124 static struct map_desc omap34xx_io_desc[] __initdata = {
126 .virtual = L3_34XX_VIRT,
127 .pfn = __phys_to_pfn(L3_34XX_PHYS),
128 .length = L3_34XX_SIZE,
132 .virtual = L4_34XX_VIRT,
133 .pfn = __phys_to_pfn(L4_34XX_PHYS),
134 .length = L4_34XX_SIZE,
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
167 #if defined(CONFIG_DEBUG_LL) && \
168 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
170 .virtual = ZOOM_UART_VIRT,
171 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
178 #ifdef CONFIG_ARCH_OMAP4
179 static struct map_desc omap44xx_io_desc[] __initdata = {
181 .virtual = L3_44XX_VIRT,
182 .pfn = __phys_to_pfn(L3_44XX_PHYS),
183 .length = L3_44XX_SIZE,
187 .virtual = L4_44XX_VIRT,
188 .pfn = __phys_to_pfn(L4_44XX_PHYS),
189 .length = L4_44XX_SIZE,
193 .virtual = OMAP44XX_GPMC_VIRT,
194 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
195 .length = OMAP44XX_GPMC_SIZE,
199 .virtual = OMAP44XX_EMIF1_VIRT,
200 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
201 .length = OMAP44XX_EMIF1_SIZE,
205 .virtual = OMAP44XX_EMIF2_VIRT,
206 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
207 .length = OMAP44XX_EMIF2_SIZE,
211 .virtual = OMAP44XX_DMM_VIRT,
212 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
213 .length = OMAP44XX_DMM_SIZE,
217 .virtual = L4_PER_44XX_VIRT,
218 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
219 .length = L4_PER_44XX_SIZE,
223 .virtual = L4_EMU_44XX_VIRT,
224 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
225 .length = L4_EMU_44XX_SIZE,
231 static void __init _omap2_map_common_io(void)
233 /* Normally devicemaps_init() would flush caches and tlb after
234 * mdesc->map_io(), but we must also do it here because of the CPU
235 * revision check below.
237 local_flush_tlb_all();
240 omap2_check_revision();
244 #ifdef CONFIG_ARCH_OMAP2420
245 void __init omap242x_map_common_io(void)
247 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
248 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
249 _omap2_map_common_io();
253 #ifdef CONFIG_ARCH_OMAP2430
254 void __init omap243x_map_common_io(void)
256 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
257 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
258 _omap2_map_common_io();
262 #ifdef CONFIG_ARCH_OMAP3
263 void __init omap34xx_map_common_io(void)
265 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
266 _omap2_map_common_io();
270 #ifdef CONFIG_ARCH_OMAP4
271 void __init omap44xx_map_common_io(void)
273 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
274 _omap2_map_common_io();
279 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
281 * Sets the CORE DPLL3 M2 divider to the same value that it's at
282 * currently. This has the effect of setting the SDRC SDRAM AC timing
283 * registers to the values currently defined by the kernel. Currently
284 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
285 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
286 * or passes along the return value of clk_set_rate().
288 static int __init _omap2_init_reprogram_sdrc(void)
290 struct clk *dpll3_m2_ck;
294 if (!cpu_is_omap34xx())
297 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
298 if (IS_ERR(dpll3_m2_ck))
301 rate = clk_get_rate(dpll3_m2_ck);
302 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
303 v = clk_set_rate(dpll3_m2_ck, rate);
305 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
307 clk_put(dpll3_m2_ck);
312 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
314 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
318 * Initialize asm_irq_base for entry-macro.S
320 static inline void omap_irq_base_init(void)
322 extern void __iomem *omap_irq_base;
325 if (cpu_is_omap24xx())
326 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
327 else if (cpu_is_omap34xx())
328 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
329 else if (cpu_is_omap44xx())
330 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
332 pr_err("Could not initialize omap_irq_base\n");
336 void __init omap2_init_common_infrastructure(void)
340 if (cpu_is_omap242x()) {
341 omap2xxx_powerdomains_init();
342 omap2_clockdomains_init();
343 omap2420_hwmod_init();
344 } else if (cpu_is_omap243x()) {
345 omap2xxx_powerdomains_init();
346 omap2_clockdomains_init();
347 omap2430_hwmod_init();
348 } else if (cpu_is_omap34xx()) {
349 omap3xxx_powerdomains_init();
350 omap2_clockdomains_init();
351 omap3xxx_hwmod_init();
352 } else if (cpu_is_omap44xx()) {
353 omap44xx_powerdomains_init();
354 omap44xx_clockdomains_init();
355 omap44xx_hwmod_init();
357 pr_err("Could not init hwmod data - unknown SoC\n");
360 /* Set the default postsetup state for all hwmods */
361 #ifdef CONFIG_PM_RUNTIME
362 postsetup_state = _HWMOD_STATE_IDLE;
364 postsetup_state = _HWMOD_STATE_ENABLED;
366 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
369 * Set the default postsetup state for unusual modules (like
372 * The postsetup_state is not actually used until
373 * omap_hwmod_late_init(), so boards that desire full watchdog
374 * coverage of kernel initialization can reprogram the
375 * postsetup_state between the calls to
376 * omap2_init_common_infra() and omap2_init_common_devices().
378 * XXX ideally we could detect whether the MPU WDT was currently
379 * enabled here and make this conditional
381 postsetup_state = _HWMOD_STATE_DISABLED;
382 omap_hwmod_for_each_by_class("wd_timer",
383 _set_hwmod_postsetup_state,
386 omap_pm_if_early_init();
388 if (cpu_is_omap2420())
390 else if (cpu_is_omap2430())
392 else if (cpu_is_omap34xx())
394 else if (cpu_is_omap44xx())
397 pr_err("Could not init clock framework - unknown SoC\n");
400 void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
401 struct omap_sdrc_params *sdrc_cs1)
403 omap_serial_early_init();
405 omap_hwmod_late_init();
407 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
408 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
409 _omap2_init_reprogram_sdrc();
413 omap_irq_base_init();
417 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
420 u8 omap_readb(u32 pa)
422 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
424 EXPORT_SYMBOL(omap_readb);
426 u16 omap_readw(u32 pa)
428 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
430 EXPORT_SYMBOL(omap_readw);
432 u32 omap_readl(u32 pa)
434 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
436 EXPORT_SYMBOL(omap_readl);
438 void omap_writeb(u8 v, u32 pa)
440 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
442 EXPORT_SYMBOL(omap_writeb);
444 void omap_writew(u16 v, u32 pa)
446 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
448 EXPORT_SYMBOL(omap_writew);
450 void omap_writel(u32 v, u32 pa)
452 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
454 EXPORT_SYMBOL(omap_writel);