2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/clk.h>
25 #include <linux/omapfb.h>
29 #include <asm/mach/map.h>
32 #include <plat/sram.h>
33 #include <plat/sdrc.h>
34 #include <plat/gpmc.h>
35 #include <plat/serial.h>
36 #include <plat/vram.h>
38 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
41 #include <plat/omap-pm.h>
42 #include <plat/powerdomain.h>
43 #include "powerdomains.h"
45 #include <plat/clockdomain.h>
46 #include "clockdomains.h"
48 #include <plat/omap_hwmod.h>
49 #include "omap_hwmod_2420.h"
50 #include "omap_hwmod_2430.h"
51 #include "omap_hwmod_34xx.h"
54 * The machine specific code may provide the extra mapping besides the
55 * default mapping provided here.
58 #ifdef CONFIG_ARCH_OMAP24XX
59 static struct map_desc omap24xx_io_desc[] __initdata = {
61 .virtual = L3_24XX_VIRT,
62 .pfn = __phys_to_pfn(L3_24XX_PHYS),
63 .length = L3_24XX_SIZE,
67 .virtual = L4_24XX_VIRT,
68 .pfn = __phys_to_pfn(L4_24XX_PHYS),
69 .length = L4_24XX_SIZE,
74 #ifdef CONFIG_ARCH_OMAP2420
75 static struct map_desc omap242x_io_desc[] __initdata = {
77 .virtual = DSP_MEM_24XX_VIRT,
78 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
79 .length = DSP_MEM_24XX_SIZE,
83 .virtual = DSP_IPI_24XX_VIRT,
84 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
85 .length = DSP_IPI_24XX_SIZE,
89 .virtual = DSP_MMU_24XX_VIRT,
90 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
91 .length = DSP_MMU_24XX_SIZE,
98 #ifdef CONFIG_ARCH_OMAP2430
99 static struct map_desc omap243x_io_desc[] __initdata = {
101 .virtual = L4_WK_243X_VIRT,
102 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
103 .length = L4_WK_243X_SIZE,
107 .virtual = OMAP243X_GPMC_VIRT,
108 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
109 .length = OMAP243X_GPMC_SIZE,
113 .virtual = OMAP243X_SDRC_VIRT,
114 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
115 .length = OMAP243X_SDRC_SIZE,
119 .virtual = OMAP243X_SMS_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
121 .length = OMAP243X_SMS_SIZE,
128 #ifdef CONFIG_ARCH_OMAP34XX
129 static struct map_desc omap34xx_io_desc[] __initdata = {
131 .virtual = L3_34XX_VIRT,
132 .pfn = __phys_to_pfn(L3_34XX_PHYS),
133 .length = L3_34XX_SIZE,
137 .virtual = L4_34XX_VIRT,
138 .pfn = __phys_to_pfn(L4_34XX_PHYS),
139 .length = L4_34XX_SIZE,
143 .virtual = L4_WK_34XX_VIRT,
144 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
145 .length = L4_WK_34XX_SIZE,
149 .virtual = OMAP34XX_GPMC_VIRT,
150 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
151 .length = OMAP34XX_GPMC_SIZE,
155 .virtual = OMAP343X_SMS_VIRT,
156 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
157 .length = OMAP343X_SMS_SIZE,
161 .virtual = OMAP343X_SDRC_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
163 .length = OMAP343X_SDRC_SIZE,
167 .virtual = L4_PER_34XX_VIRT,
168 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
169 .length = L4_PER_34XX_SIZE,
173 .virtual = L4_EMU_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
175 .length = L4_EMU_34XX_SIZE,
180 #ifdef CONFIG_ARCH_OMAP4
181 static struct map_desc omap44xx_io_desc[] __initdata = {
183 .virtual = L3_44XX_VIRT,
184 .pfn = __phys_to_pfn(L3_44XX_PHYS),
185 .length = L3_44XX_SIZE,
189 .virtual = L4_44XX_VIRT,
190 .pfn = __phys_to_pfn(L4_44XX_PHYS),
191 .length = L4_44XX_SIZE,
195 .virtual = L4_WK_44XX_VIRT,
196 .pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
197 .length = L4_WK_44XX_SIZE,
201 .virtual = OMAP44XX_GPMC_VIRT,
202 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
203 .length = OMAP44XX_GPMC_SIZE,
207 .virtual = OMAP44XX_EMIF1_VIRT,
208 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
209 .length = OMAP44XX_EMIF1_SIZE,
213 .virtual = OMAP44XX_EMIF2_VIRT,
214 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
215 .length = OMAP44XX_EMIF2_SIZE,
219 .virtual = OMAP44XX_DMM_VIRT,
220 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
221 .length = OMAP44XX_DMM_SIZE,
225 .virtual = L4_PER_44XX_VIRT,
226 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
227 .length = L4_PER_44XX_SIZE,
231 .virtual = L4_EMU_44XX_VIRT,
232 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
233 .length = L4_EMU_44XX_SIZE,
239 void __init omap2_map_common_io(void)
241 #if defined(CONFIG_ARCH_OMAP2420)
242 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
243 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
246 #if defined(CONFIG_ARCH_OMAP2430)
247 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
248 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
251 #if defined(CONFIG_ARCH_OMAP34XX)
252 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
255 #if defined(CONFIG_ARCH_OMAP4)
256 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
258 /* Normally devicemaps_init() would flush caches and tlb after
259 * mdesc->map_io(), but we must also do it here because of the CPU
260 * revision check below.
262 local_flush_tlb_all();
265 omap2_check_revision();
267 omapfb_reserve_sdram();
268 omap_vram_reserve_sdram();
272 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
274 * Sets the CORE DPLL3 M2 divider to the same value that it's at
275 * currently. This has the effect of setting the SDRC SDRAM AC timing
276 * registers to the values currently defined by the kernel. Currently
277 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
278 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
279 * or passes along the return value of clk_set_rate().
281 static int __init _omap2_init_reprogram_sdrc(void)
283 struct clk *dpll3_m2_ck;
287 if (!cpu_is_omap34xx())
290 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
294 rate = clk_get_rate(dpll3_m2_ck);
295 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
296 v = clk_set_rate(dpll3_m2_ck, rate);
298 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
300 clk_put(dpll3_m2_ck);
305 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
306 struct omap_sdrc_params *sdrc_cs1)
308 struct omap_hwmod **hwmods = NULL;
310 if (cpu_is_omap2420())
311 hwmods = omap2420_hwmods;
312 else if (cpu_is_omap2430())
313 hwmods = omap2430_hwmods;
314 else if (cpu_is_omap34xx())
315 hwmods = omap34xx_hwmods;
317 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
318 /* The OPP tables have to be registered before a clk init */
319 omap_hwmod_init(hwmods);
321 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
322 pwrdm_init(powerdomains_omap);
323 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
326 omap_serial_early_init();
327 #ifndef CONFIG_ARCH_OMAP4
328 omap_hwmod_late_init();
330 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
331 _omap2_init_reprogram_sdrc();