2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <video/omapdss.h>
28 #include "omap_hwmod.h"
29 #include "omap_device.h"
40 #define DISPC_CONTROL 0x0040
41 #define DISPC_CONTROL2 0x0238
42 #define DISPC_CONTROL3 0x0848
43 #define DISPC_IRQSTATUS 0x0018
45 #define DSS_SYSCONFIG 0x10
46 #define DSS_SYSSTATUS 0x14
47 #define DSS_CONTROL 0x40
48 #define DSS_SDI_CONTROL 0x44
49 #define DSS_PLL_CONTROL 0x48
51 #define LCD_EN_MASK (0x1 << 0)
52 #define DIGIT_EN_MASK (0x1 << 1)
54 #define FRAMEDONE_IRQ_SHIFT 0
55 #define EVSYNC_EVEN_IRQ_SHIFT 2
56 #define EVSYNC_ODD_IRQ_SHIFT 3
57 #define FRAMEDONE2_IRQ_SHIFT 22
58 #define FRAMEDONE3_IRQ_SHIFT 30
59 #define FRAMEDONETV_IRQ_SHIFT 24
62 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
63 * reset before deciding that something has gone wrong
65 #define FRAMEDONE_IRQ_TIMEOUT 100
67 static struct platform_device omap_display_device = {
71 .platform_data = NULL,
75 struct omap_dss_hwmod_data {
81 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
82 { "dss_core", "omapdss_dss", -1 },
83 { "dss_dispc", "omapdss_dispc", -1 },
84 { "dss_rfbi", "omapdss_rfbi", -1 },
85 { "dss_venc", "omapdss_venc", -1 },
88 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
89 { "dss_core", "omapdss_dss", -1 },
90 { "dss_dispc", "omapdss_dispc", -1 },
91 { "dss_rfbi", "omapdss_rfbi", -1 },
92 { "dss_venc", "omapdss_venc", -1 },
93 { "dss_dsi1", "omapdss_dsi", 0 },
96 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
97 { "dss_core", "omapdss_dss", -1 },
98 { "dss_dispc", "omapdss_dispc", -1 },
99 { "dss_rfbi", "omapdss_rfbi", -1 },
100 { "dss_dsi1", "omapdss_dsi", 0 },
101 { "dss_dsi2", "omapdss_dsi", 1 },
102 { "dss_hdmi", "omapdss_hdmi", -1 },
105 static void __init omap4_tpd12s015_mux_pads(void)
107 omap_mux_init_signal("hdmi_cec",
108 OMAP_PIN_INPUT_PULLUP);
109 omap_mux_init_signal("hdmi_ddc_scl",
110 OMAP_PIN_INPUT_PULLUP);
111 omap_mux_init_signal("hdmi_ddc_sda",
112 OMAP_PIN_INPUT_PULLUP);
115 static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
121 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
122 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
123 * internal pull up resistor.
125 if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
126 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
127 reg = omap4_ctrl_pad_readl(control_i2c_1);
128 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
129 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
130 omap4_ctrl_pad_writel(reg, control_i2c_1);
134 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
136 u32 enable_mask, enable_shift;
137 u32 pipd_mask, pipd_shift;
141 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
142 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
143 pipd_mask = OMAP4_DSI1_PIPD_MASK;
144 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
145 } else if (dsi_id == 1) {
146 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
147 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
148 pipd_mask = OMAP4_DSI2_PIPD_MASK;
149 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
154 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
159 reg |= (lanes << enable_shift) & enable_mask;
160 reg |= (lanes << pipd_shift) & pipd_mask;
162 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
167 int __init omap_hdmi_init(enum omap_hdmi_flags flags)
169 if (cpu_is_omap44xx()) {
170 omap4_hdmi_mux_pads(flags);
171 omap4_tpd12s015_mux_pads();
177 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
179 if (cpu_is_omap44xx())
180 return omap4_dsi_mux_pads(dsi_id, lane_mask);
185 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
187 if (cpu_is_omap44xx())
188 omap4_dsi_mux_pads(dsi_id, 0);
191 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
193 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
196 static struct platform_device *create_dss_pdev(const char *pdev_name,
197 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
198 struct platform_device *parent)
200 struct platform_device *pdev;
201 struct omap_device *od;
202 struct omap_hwmod *ohs[1];
203 struct omap_hwmod *oh;
206 oh = omap_hwmod_lookup(oh_name);
208 pr_err("Could not look up %s\n", oh_name);
213 pdev = platform_device_alloc(pdev_name, pdev_id);
215 pr_err("Could not create pdev for %s\n", pdev_name);
221 pdev->dev.parent = &parent->dev;
224 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
226 dev_set_name(&pdev->dev, "%s", pdev->name);
229 od = omap_device_alloc(pdev, ohs, 1);
231 pr_err("Could not alloc omap_device for %s\n", pdev_name);
236 r = platform_device_add_data(pdev, pdata, pdata_len);
238 pr_err("Could not set pdata for %s\n", pdev_name);
242 r = omap_device_register(pdev);
244 pr_err("Could not register omap_device for %s\n", pdev_name);
254 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
255 int pdev_id, void *pdata, int pdata_len,
256 struct platform_device *parent)
258 struct platform_device *pdev;
261 pdev = platform_device_alloc(pdev_name, pdev_id);
263 pr_err("Could not create pdev for %s\n", pdev_name);
269 pdev->dev.parent = &parent->dev;
272 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
274 dev_set_name(&pdev->dev, "%s", pdev->name);
276 r = platform_device_add_data(pdev, pdata, pdata_len);
278 pr_err("Could not set pdata for %s\n", pdev_name);
282 r = platform_device_add(pdev);
284 pr_err("Could not register platform_device for %s\n", pdev_name);
294 static enum omapdss_version __init omap_display_get_version(void)
296 if (cpu_is_omap24xx())
297 return OMAPDSS_VER_OMAP24xx;
298 else if (cpu_is_omap3630())
299 return OMAPDSS_VER_OMAP3630;
300 else if (cpu_is_omap34xx()) {
301 if (soc_is_am35xx()) {
302 return OMAPDSS_VER_AM35xx;
304 if (omap_rev() < OMAP3430_REV_ES3_0)
305 return OMAPDSS_VER_OMAP34xx_ES1;
307 return OMAPDSS_VER_OMAP34xx_ES3;
309 } else if (omap_rev() == OMAP4430_REV_ES1_0)
310 return OMAPDSS_VER_OMAP4430_ES1;
311 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
312 omap_rev() == OMAP4430_REV_ES2_1 ||
313 omap_rev() == OMAP4430_REV_ES2_2)
314 return OMAPDSS_VER_OMAP4430_ES2;
315 else if (cpu_is_omap44xx())
316 return OMAPDSS_VER_OMAP4;
317 else if (soc_is_omap54xx())
318 return OMAPDSS_VER_OMAP5;
320 return OMAPDSS_VER_UNKNOWN;
323 int __init omap_display_init(struct omap_dss_board_info *board_data)
326 struct platform_device *pdev;
328 const struct omap_dss_hwmod_data *curr_dss_hwmod;
329 struct platform_device *dss_pdev;
330 enum omapdss_version ver;
332 /* create omapdss device */
334 ver = omap_display_get_version();
336 if (ver == OMAPDSS_VER_UNKNOWN) {
337 pr_err("DSS not supported on this SoC\n");
341 board_data->version = ver;
342 board_data->dsi_enable_pads = omap_dsi_enable_pads;
343 board_data->dsi_disable_pads = omap_dsi_disable_pads;
344 board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
345 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
347 omap_display_device.dev.platform_data = board_data;
349 r = platform_device_register(&omap_display_device);
351 pr_err("Unable to register omapdss device\n");
355 /* create devices for dss hwmods */
357 if (cpu_is_omap24xx()) {
358 curr_dss_hwmod = omap2_dss_hwmod_data;
359 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
360 } else if (cpu_is_omap34xx()) {
361 curr_dss_hwmod = omap3_dss_hwmod_data;
362 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
364 curr_dss_hwmod = omap4_dss_hwmod_data;
365 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
369 * First create the pdev for dss_core, which is used as a parent device
370 * by the other dss pdevs. Note: dss_core has to be the first item in
373 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
374 curr_dss_hwmod[0].id,
375 curr_dss_hwmod[0].oh_name,
376 board_data, sizeof(*board_data),
379 if (IS_ERR(dss_pdev)) {
380 pr_err("Could not build omap_device for %s\n",
381 curr_dss_hwmod[0].oh_name);
383 return PTR_ERR(dss_pdev);
386 for (i = 1; i < oh_count; i++) {
387 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
388 curr_dss_hwmod[i].id,
389 curr_dss_hwmod[i].oh_name,
390 board_data, sizeof(*board_data),
394 pr_err("Could not build omap_device for %s\n",
395 curr_dss_hwmod[i].oh_name);
397 return PTR_ERR(pdev);
401 /* Create devices for DPI and SDI */
403 pdev = create_simple_dss_pdev("omapdss_dpi", 0,
404 board_data, sizeof(*board_data), dss_pdev);
406 pr_err("Could not build platform_device for omapdss_dpi\n");
407 return PTR_ERR(pdev);
410 if (cpu_is_omap34xx()) {
411 pdev = create_simple_dss_pdev("omapdss_sdi", 0,
412 board_data, sizeof(*board_data), dss_pdev);
414 pr_err("Could not build platform_device for omapdss_sdi\n");
415 return PTR_ERR(pdev);
419 /* create DRM device */
422 pr_err("Unable to register omapdrm device\n");
426 /* create vrfb device */
427 r = omap_init_vrfb();
429 pr_err("Unable to register omapvrfb device\n");
433 /* create FB device */
436 pr_err("Unable to register omapfb device\n");
440 /* create V4L2 display device */
441 r = omap_init_vout();
443 pr_err("Unable to register omap_vout device\n");
450 static void dispc_disable_outputs(void)
453 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
455 struct omap_dss_dispc_dev_attr *da;
456 struct omap_hwmod *oh;
458 oh = omap_hwmod_lookup("dss_dispc");
460 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
465 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
469 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
471 /* store value of LCDENABLE and DIGITENABLE bits */
472 v = omap_hwmod_read(oh, DISPC_CONTROL);
473 lcd_en = v & LCD_EN_MASK;
474 digit_en = v & DIGIT_EN_MASK;
476 /* store value of LCDENABLE for LCD2 */
477 if (da->manager_count > 2) {
478 v = omap_hwmod_read(oh, DISPC_CONTROL2);
479 lcd2_en = v & LCD_EN_MASK;
482 /* store value of LCDENABLE for LCD3 */
483 if (da->manager_count > 3) {
484 v = omap_hwmod_read(oh, DISPC_CONTROL3);
485 lcd3_en = v & LCD_EN_MASK;
488 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
489 return; /* no managers currently enabled */
492 * If any manager was enabled, we need to disable it before
493 * DSS clocks are disabled or DISPC module is reset
496 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
499 if (da->has_framedonetv_irq) {
500 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
502 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
503 1 << EVSYNC_ODD_IRQ_SHIFT;
508 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
510 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
513 * clear any previous FRAMEDONE, FRAMEDONETV,
514 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
516 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
518 /* disable LCD and TV managers */
519 v = omap_hwmod_read(oh, DISPC_CONTROL);
520 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
521 omap_hwmod_write(v, oh, DISPC_CONTROL);
523 /* disable LCD2 manager */
524 if (da->manager_count > 2) {
525 v = omap_hwmod_read(oh, DISPC_CONTROL2);
527 omap_hwmod_write(v, oh, DISPC_CONTROL2);
530 /* disable LCD3 manager */
531 if (da->manager_count > 3) {
532 v = omap_hwmod_read(oh, DISPC_CONTROL3);
534 omap_hwmod_write(v, oh, DISPC_CONTROL3);
538 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
541 if (i > FRAMEDONE_IRQ_TIMEOUT) {
542 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
549 int omap_dss_reset(struct omap_hwmod *oh)
551 struct omap_hwmod_opt_clk *oc;
555 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
556 pr_err("dss_core: hwmod data doesn't contain reset data\n");
560 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
562 clk_prepare_enable(oc->_clk);
564 dispc_disable_outputs();
566 /* clear SDI registers */
567 if (cpu_is_omap3430()) {
568 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
569 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
573 * clear DSS_CONTROL register to switch DSS clock sources to
576 omap_hwmod_write(0x0, oh, DSS_CONTROL);
578 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
579 & SYSS_RESETDONE_MASK),
580 MAX_MODULE_SOFTRESET_WAIT, c);
582 if (c == MAX_MODULE_SOFTRESET_WAIT)
583 pr_warning("dss_core: waiting for reset to finish failed\n");
585 pr_debug("dss_core: softreset done\n");
587 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
589 clk_disable_unprepare(oc->_clk);
591 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;