2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
31 #include <plat/clock.h>
32 #include <plat/sram.h>
33 #include <plat/sdrc.h>
34 #include <asm/div64.h>
35 #include <asm/clkdev.h>
37 #include <plat/sdrc.h>
39 #include "clock34xx.h"
42 #include "prm-regbits-34xx.h"
44 #include "cm-regbits-34xx.h"
46 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
47 #define DPLL_AUTOIDLE_DISABLE 0x0
48 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
50 #define MAX_DPLL_WAIT_TRIES 1000000
52 #define CYCLES_PER_MHZ 1000000
55 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
56 * that are sourced by DPLL5, and both of these require this clock
57 * to be at 120 MHz for proper operation.
59 #define DPLL5_FREQ_FOR_USBHOST 120000000
61 /* needed by omap3_core_dpll_m2_set_rate() */
62 struct clk *sdrc_ick_p, *arm_fck_p;
65 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
66 * @clk: struct clk * being enabled
67 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
68 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
70 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
71 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
72 * @idlest_reg and @idlest_bit. No return value.
74 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
75 void __iomem **idlest_reg,
80 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
81 *idlest_reg = (__force void __iomem *)r;
82 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
85 const struct clkops clkops_omap3430es2_ssi_wait = {
86 .enable = omap2_dflt_clk_enable,
87 .disable = omap2_dflt_clk_disable,
88 .find_idlest = omap3430es2_clk_ssi_find_idlest,
89 .find_companion = omap2_clk_dflt_find_companion,
93 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
94 * @clk: struct clk * being enabled
95 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
96 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
98 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
99 * target IDLEST bits. For our purposes, we are concerned with the
100 * target IDLEST bits, which exist at a different bit position than
101 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
102 * default find_idlest code assumes that they are at the same
103 * position.) No return value.
105 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
106 void __iomem **idlest_reg,
111 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
112 *idlest_reg = (__force void __iomem *)r;
113 /* USBHOST_IDLE has same shift */
114 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
117 const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
118 .enable = omap2_dflt_clk_enable,
119 .disable = omap2_dflt_clk_disable,
120 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
121 .find_companion = omap2_clk_dflt_find_companion,
125 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
126 * @clk: struct clk * being enabled
127 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
128 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
130 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
131 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
132 * @idlest_reg and @idlest_bit. No return value.
134 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
135 void __iomem **idlest_reg,
140 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
141 *idlest_reg = (__force void __iomem *)r;
142 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
145 const struct clkops clkops_omap3430es2_hsotgusb_wait = {
146 .enable = omap2_dflt_clk_enable,
147 .disable = omap2_dflt_clk_disable,
148 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
149 .find_companion = omap2_clk_dflt_find_companion,
153 * omap3_dpll_recalc - recalculate DPLL rate
154 * @clk: DPLL struct clk
156 * Recalculate and propagate the DPLL rate.
158 unsigned long omap3_dpll_recalc(struct clk *clk)
160 return omap2_get_dpll_rate(clk);
163 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
164 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
166 const struct dpll_data *dd;
171 v = __raw_readl(dd->control_reg);
172 v &= ~dd->enable_mask;
173 v |= clken_bits << __ffs(dd->enable_mask);
174 __raw_writel(v, dd->control_reg);
177 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
178 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
180 const struct dpll_data *dd;
186 state <<= __ffs(dd->idlest_mask);
188 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
189 i < MAX_DPLL_WAIT_TRIES) {
194 if (i == MAX_DPLL_WAIT_TRIES) {
195 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
196 clk->name, (state) ? "locked" : "bypassed");
198 pr_debug("clock: %s transition to '%s' in %d loops\n",
199 clk->name, (state) ? "locked" : "bypassed", i);
207 /* From 3430 TRM ES2 4.7.6.2 */
208 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
213 fint = clk->dpll_data->clk_ref->rate / n;
215 pr_debug("clock: fint is %lu\n", fint);
217 if (fint >= 750000 && fint <= 1000000)
219 else if (fint > 1000000 && fint <= 1250000)
221 else if (fint > 1250000 && fint <= 1500000)
223 else if (fint > 1500000 && fint <= 1750000)
225 else if (fint > 1750000 && fint <= 2100000)
227 else if (fint > 7500000 && fint <= 10000000)
229 else if (fint > 10000000 && fint <= 12500000)
231 else if (fint > 12500000 && fint <= 15000000)
233 else if (fint > 15000000 && fint <= 17500000)
235 else if (fint > 17500000 && fint <= 21000000)
238 pr_debug("clock: unknown freqsel setting for %d\n", n);
243 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
246 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
247 * @clk: pointer to a DPLL struct clk
249 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
250 * readiness before returning. Will save and restore the DPLL's
251 * autoidle state across the enable, per the CDP code. If the DPLL
252 * locked successfully, return 0; if the DPLL did not lock in the time
253 * allotted, or DPLL3 was passed in, return -EINVAL.
255 static int _omap3_noncore_dpll_lock(struct clk *clk)
260 pr_debug("clock: locking DPLL %s\n", clk->name);
262 ai = omap3_dpll_autoidle_read(clk);
264 omap3_dpll_deny_idle(clk);
266 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
268 r = _omap3_wait_dpll_status(clk, 1);
271 omap3_dpll_allow_idle(clk);
277 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
278 * @clk: pointer to a DPLL struct clk
280 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
281 * bypass mode, the DPLL's rate is set equal to its parent clock's
282 * rate. Waits for the DPLL to report readiness before returning.
283 * Will save and restore the DPLL's autoidle state across the enable,
284 * per the CDP code. If the DPLL entered bypass mode successfully,
285 * return 0; if the DPLL did not enter bypass in the time allotted, or
286 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
289 static int _omap3_noncore_dpll_bypass(struct clk *clk)
294 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
297 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
300 ai = omap3_dpll_autoidle_read(clk);
302 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
304 r = _omap3_wait_dpll_status(clk, 0);
307 omap3_dpll_allow_idle(clk);
309 omap3_dpll_deny_idle(clk);
315 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
316 * @clk: pointer to a DPLL struct clk
318 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
319 * restore the DPLL's autoidle state across the stop, per the CDP
320 * code. If DPLL3 was passed in, or the DPLL does not support
321 * low-power stop, return -EINVAL; otherwise, return 0.
323 static int _omap3_noncore_dpll_stop(struct clk *clk)
327 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
330 pr_debug("clock: stopping DPLL %s\n", clk->name);
332 ai = omap3_dpll_autoidle_read(clk);
334 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
337 omap3_dpll_allow_idle(clk);
339 omap3_dpll_deny_idle(clk);
345 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
346 * @clk: pointer to a DPLL struct clk
348 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
349 * The choice of modes depends on the DPLL's programmed rate: if it is
350 * the same as the DPLL's parent clock, it will enter bypass;
351 * otherwise, it will enter lock. This code will wait for the DPLL to
352 * indicate readiness before returning, unless the DPLL takes too long
353 * to enter the target state. Intended to be used as the struct clk's
354 * enable function. If DPLL3 was passed in, or the DPLL does not
355 * support low-power stop, or if the DPLL took too long to enter
356 * bypass or lock, return -EINVAL; otherwise, return 0.
358 static int omap3_noncore_dpll_enable(struct clk *clk)
361 struct dpll_data *dd;
367 if (clk->rate == dd->clk_bypass->rate) {
368 WARN_ON(clk->parent != dd->clk_bypass);
369 r = _omap3_noncore_dpll_bypass(clk);
371 WARN_ON(clk->parent != dd->clk_ref);
372 r = _omap3_noncore_dpll_lock(clk);
374 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
376 clk->rate = omap2_get_dpll_rate(clk);
382 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
383 * @clk: pointer to a DPLL struct clk
385 * Instructs a non-CORE DPLL to enter low-power stop. This function is
386 * intended for use in struct clkops. No return value.
388 static void omap3_noncore_dpll_disable(struct clk *clk)
390 _omap3_noncore_dpll_stop(clk);
393 const struct clkops clkops_noncore_dpll_ops = {
394 .enable = omap3_noncore_dpll_enable,
395 .disable = omap3_noncore_dpll_disable,
398 /* Non-CORE DPLL rate set code */
401 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
402 * @clk: struct clk * of DPLL to set
403 * @m: DPLL multiplier to set
404 * @n: DPLL divider to set
405 * @freqsel: FREQSEL value to set
407 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
408 * lock.. Returns -EINVAL upon error, or 0 upon success.
410 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
412 struct dpll_data *dd = clk->dpll_data;
415 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
416 _omap3_noncore_dpll_bypass(clk);
418 /* Set jitter correction */
419 v = __raw_readl(dd->control_reg);
420 v &= ~dd->freqsel_mask;
421 v |= freqsel << __ffs(dd->freqsel_mask);
422 __raw_writel(v, dd->control_reg);
424 /* Set DPLL multiplier, divider */
425 v = __raw_readl(dd->mult_div1_reg);
426 v &= ~(dd->mult_mask | dd->div1_mask);
427 v |= m << __ffs(dd->mult_mask);
428 v |= (n - 1) << __ffs(dd->div1_mask);
429 __raw_writel(v, dd->mult_div1_reg);
431 /* We let the clock framework set the other output dividers later */
433 /* REVISIT: Set ramp-up delay? */
435 _omap3_noncore_dpll_lock(clk);
441 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
442 * @clk: struct clk * of DPLL to set
443 * @rate: rounded target rate
445 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
446 * low-power bypass, and the target rate is the bypass source clock
447 * rate, then configure the DPLL for bypass. Otherwise, round the
448 * target rate if it hasn't been done already, then program and lock
449 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
451 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
453 struct clk *new_parent = NULL;
455 struct dpll_data *dd;
465 if (rate == omap2_get_dpll_rate(clk))
469 * Ensure both the bypass and ref clocks are enabled prior to
470 * doing anything; we need the bypass clock running to reprogram
473 omap2_clk_enable(dd->clk_bypass);
474 omap2_clk_enable(dd->clk_ref);
476 if (dd->clk_bypass->rate == rate &&
477 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
478 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
480 ret = _omap3_noncore_dpll_bypass(clk);
482 new_parent = dd->clk_bypass;
484 if (dd->last_rounded_rate != rate)
485 omap2_dpll_round_rate(clk, rate);
487 if (dd->last_rounded_rate == 0)
490 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
494 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
497 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
498 dd->last_rounded_n, freqsel);
500 new_parent = dd->clk_ref;
504 * Switch the parent clock in the heirarchy, and make sure
505 * that the new parent's usecount is correct. Note: we
506 * enable the new parent before disabling the old to avoid
507 * any unnecessary hardware disable->enable transitions.
510 omap2_clk_enable(new_parent);
511 omap2_clk_disable(clk->parent);
513 clk_reparent(clk, new_parent);
516 omap2_clk_disable(dd->clk_ref);
517 omap2_clk_disable(dd->clk_bypass);
522 int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
525 * According to the 12-5 CDP code from TI, "Limitation 2.5"
526 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
529 if (omap_rev() == OMAP3430_REV_ES1_0) {
530 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
531 "silicon 'Limitation 2.5' on 3430ES1.\n");
534 return omap3_noncore_dpll_set_rate(clk, rate);
539 * CORE DPLL (DPLL3) rate programming functions
541 * These call into SRAM code to do the actual CM writes, since the SDRAM
542 * is clocked from DPLL3.
546 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
547 * @clk: struct clk * of DPLL to set
548 * @rate: rounded target rate
550 * Program the DPLL M2 divider with the rounded target rate. Returns
551 * -EINVAL upon error, or 0 upon success.
553 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
558 unsigned long validrate, sdrcrate, _mpurate;
559 struct omap_sdrc_params *sdrc_cs0;
560 struct omap_sdrc_params *sdrc_cs1;
566 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
567 if (validrate != rate)
570 sdrcrate = sdrc_ick_p->rate;
571 if (rate > clk->rate)
572 sdrcrate <<= ((rate / clk->rate) >> 1);
574 sdrcrate >>= ((clk->rate / rate) >> 1);
576 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
580 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
581 pr_debug("clock: will unlock SDRC DLL\n");
586 * XXX This only needs to be done when the CPU frequency changes
588 _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
589 c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
590 c += 1; /* for safety */
591 c *= SDRC_MPURATE_LOOPS;
592 c >>= SDRC_MPURATE_SCALE;
596 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
598 pr_debug("clock: SDRC CS0 timing params used:"
599 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
600 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
601 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
603 pr_debug("clock: SDRC CS1 timing params used: "
604 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
605 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
606 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
609 omap3_configure_core_dpll(
610 new_div, unlock_dll, c, rate > clk->rate,
611 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
612 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
613 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
614 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
616 omap3_configure_core_dpll(
617 new_div, unlock_dll, c, rate > clk->rate,
618 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
619 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
626 /* DPLL autoidle read/set code */
630 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
631 * @clk: struct clk * of the DPLL to read
633 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
634 * -EINVAL if passed a null pointer or if the struct clk does not
635 * appear to refer to a DPLL.
637 u32 omap3_dpll_autoidle_read(struct clk *clk)
639 const struct dpll_data *dd;
642 if (!clk || !clk->dpll_data)
647 v = __raw_readl(dd->autoidle_reg);
648 v &= dd->autoidle_mask;
649 v >>= __ffs(dd->autoidle_mask);
655 * omap3_dpll_allow_idle - enable DPLL autoidle bits
656 * @clk: struct clk * of the DPLL to operate on
658 * Enable DPLL automatic idle control. This automatic idle mode
659 * switching takes effect only when the DPLL is locked, at least on
660 * OMAP3430. The DPLL will enter low-power stop when its downstream
661 * clocks are gated. No return value.
663 void omap3_dpll_allow_idle(struct clk *clk)
665 const struct dpll_data *dd;
668 if (!clk || !clk->dpll_data)
674 * REVISIT: CORE DPLL can optionally enter low-power bypass
675 * by writing 0x5 instead of 0x1. Add some mechanism to
676 * optionally enter this mode.
678 v = __raw_readl(dd->autoidle_reg);
679 v &= ~dd->autoidle_mask;
680 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
681 __raw_writel(v, dd->autoidle_reg);
685 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
686 * @clk: struct clk * of the DPLL to operate on
688 * Disable DPLL automatic idle control. No return value.
690 void omap3_dpll_deny_idle(struct clk *clk)
692 const struct dpll_data *dd;
695 if (!clk || !clk->dpll_data)
700 v = __raw_readl(dd->autoidle_reg);
701 v &= ~dd->autoidle_mask;
702 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
703 __raw_writel(v, dd->autoidle_reg);
706 /* Clock control for DPLL outputs */
709 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
710 * @clk: DPLL output struct clk
712 * Using parent clock DPLL data, look up DPLL state. If locked, set our
713 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
715 unsigned long omap3_clkoutx2_recalc(struct clk *clk)
717 const struct dpll_data *dd;
722 /* Walk up the parents of clk, looking for a DPLL */
724 while (pclk && !pclk->dpll_data)
727 /* clk does not have a DPLL as a parent? */
730 dd = pclk->dpll_data;
732 WARN_ON(!dd->enable_mask);
734 v = __raw_readl(dd->control_reg) & dd->enable_mask;
735 v >>= __ffs(dd->enable_mask);
736 if (v != OMAP3XXX_EN_DPLL_LOCKED)
737 rate = clk->parent->rate;
739 rate = clk->parent->rate * 2;
743 /* Common clock code */
746 * As it is structured now, this will prevent an OMAP2/3 multiboot
747 * kernel from compiling. This will need further attention.
749 #if defined(CONFIG_ARCH_OMAP3)
751 struct clk_functions omap2_clk_functions = {
752 .clk_enable = omap2_clk_enable,
753 .clk_disable = omap2_clk_disable,
754 .clk_round_rate = omap2_clk_round_rate,
755 .clk_set_rate = omap2_clk_set_rate,
756 .clk_set_parent = omap2_clk_set_parent,
757 .clk_disable_unused = omap2_clk_disable_unused,
761 * Set clocks for bypass mode for reboot to work.
763 void omap2_clk_prepare_for_reboot(void)
765 /* REVISIT: Not ready for 343x */
769 if (vclk == NULL || sclk == NULL)
772 rate = clk_get_rate(sclk);
773 clk_set_rate(vclk, rate);
777 void omap3_clk_lock_dpll5(void)
779 struct clk *dpll5_clk;
780 struct clk *dpll5_m2_clk;
782 dpll5_clk = clk_get(NULL, "dpll5_ck");
783 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
784 clk_enable(dpll5_clk);
786 /* Enable autoidle to allow it to enter low power bypass */
787 omap3_dpll_allow_idle(dpll5_clk);
789 /* Program dpll5_m2_clk divider for no division */
790 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
791 clk_enable(dpll5_m2_clk);
792 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
794 clk_disable(dpll5_m2_clk);
795 clk_disable(dpll5_clk);
799 /* REVISIT: Move this init stuff out into clock.c */
802 * Switch the MPU rate if specified on cmdline.
803 * We cannot do this early until cmdline is parsed.
805 static int __init omap2_clk_arch_init(void)
807 struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
808 unsigned long osc_sys_rate;
813 /* XXX test these for success */
814 dpll1_ck = clk_get(NULL, "dpll1_ck");
815 arm_fck = clk_get(NULL, "arm_fck");
816 core_ck = clk_get(NULL, "core_ck");
817 osc_sys_ck = clk_get(NULL, "osc_sys_ck");
819 /* REVISIT: not yet ready for 343x */
820 if (clk_set_rate(dpll1_ck, mpurate))
821 printk(KERN_ERR "*** Unable to set MPU rate\n");
823 recalculate_root_clocks();
825 osc_sys_rate = clk_get_rate(osc_sys_ck);
827 pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
828 "%ld.%01ld/%ld/%ld MHz\n",
829 (osc_sys_rate / 1000000),
830 ((osc_sys_rate / 100000) % 10),
831 (clk_get_rate(core_ck) / 1000000),
832 (clk_get_rate(arm_fck) / 1000000));
838 arch_initcall(omap2_clk_arch_init);