2 * linux/arch/arm/mach-omap2/clock24xx.h
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
23 #include "prm-regbits-24xx.h"
24 #include "cm-regbits-24xx.h"
27 static void omap2_table_mpu_recalc(struct clk *clk);
28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30 static void omap2_sys_clk_recalc(struct clk *clk);
31 static void omap2_osc_clk_recalc(struct clk *clk);
32 static void omap2_sys_clk_recalc(struct clk *clk);
33 static void omap2_dpllcore_recalc(struct clk *clk);
34 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
41 unsigned long xtal_speed; /* crystal rate */
42 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
43 unsigned long mpu_speed; /* speed of MPU */
44 unsigned long cm_clksel_mpu; /* mpu divider */
45 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
46 unsigned long cm_clksel_gfx; /* gfx dividers */
47 unsigned long cm_clksel1_core; /* major subsystem dividers */
48 unsigned long cm_clksel1_pll; /* m,n */
49 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
50 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
51 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
56 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
57 * These configurations are characterized by voltage and speed for clocks.
58 * The device is only validated for certain combinations. One way to express
59 * these combinations is via the 'ratio's' which the clocks operate with
60 * respect to each other. These ratio sets are for a given voltage/DPLL
61 * setting. All configurations can be described by a DPLL setting and a ratio
62 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
64 * 2430 differs from 2420 in that there are no more phase synchronizers used.
65 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
66 * 2430 (iva2.1, NOdsp, mdm)
69 /* Core fields for cm_clksel, not ratio governed */
70 #define RX_CLKSEL_DSS1 (0x10 << 8)
71 #define RX_CLKSEL_DSS2 (0x0 << 13)
72 #define RX_CLKSEL_SSI (0x5 << 20)
74 /*-------------------------------------------------------------------------
76 *-------------------------------------------------------------------------*/
78 /* 2430 Ratio's, 2430-Ratio Config 1 */
79 #define R1_CLKSEL_L3 (4 << 0)
80 #define R1_CLKSEL_L4 (2 << 5)
81 #define R1_CLKSEL_USB (4 << 25)
82 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
83 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
84 R1_CLKSEL_L4 | R1_CLKSEL_L3
85 #define R1_CLKSEL_MPU (2 << 0)
86 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
87 #define R1_CLKSEL_DSP (2 << 0)
88 #define R1_CLKSEL_DSP_IF (2 << 5)
89 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
90 #define R1_CLKSEL_GFX (2 << 0)
91 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
92 #define R1_CLKSEL_MDM (4 << 0)
93 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
95 /* 2430-Ratio Config 2 */
96 #define R2_CLKSEL_L3 (6 << 0)
97 #define R2_CLKSEL_L4 (2 << 5)
98 #define R2_CLKSEL_USB (2 << 25)
99 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
100 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
101 R2_CLKSEL_L4 | R2_CLKSEL_L3
102 #define R2_CLKSEL_MPU (2 << 0)
103 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
104 #define R2_CLKSEL_DSP (2 << 0)
105 #define R2_CLKSEL_DSP_IF (3 << 5)
106 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
107 #define R2_CLKSEL_GFX (2 << 0)
108 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
109 #define R2_CLKSEL_MDM (6 << 0)
110 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
112 /* 2430-Ratio Bootm (BYPASS) */
113 #define RB_CLKSEL_L3 (1 << 0)
114 #define RB_CLKSEL_L4 (1 << 5)
115 #define RB_CLKSEL_USB (1 << 25)
116 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
117 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
118 RB_CLKSEL_L4 | RB_CLKSEL_L3
119 #define RB_CLKSEL_MPU (1 << 0)
120 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
121 #define RB_CLKSEL_DSP (1 << 0)
122 #define RB_CLKSEL_DSP_IF (1 << 5)
123 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
124 #define RB_CLKSEL_GFX (1 << 0)
125 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
126 #define RB_CLKSEL_MDM (1 << 0)
127 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
129 /* 2420 Ratio Equivalents */
130 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
131 #define RXX_CLKSEL_SSI (0x8 << 20)
133 /* 2420-PRCM III 532MHz core */
134 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
135 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
136 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
137 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
138 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
139 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
141 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
142 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
143 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
144 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
145 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
146 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
147 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
148 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
149 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
151 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
152 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
154 /* 2420-PRCM II 600MHz core */
155 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
156 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
157 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
158 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
159 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
160 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
161 RII_CLKSEL_L4 | RII_CLKSEL_L3
162 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
163 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
164 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
165 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
166 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
167 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
168 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
169 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
170 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
172 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
173 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
175 /* 2420-PRCM I 660MHz core */
176 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
177 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
178 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
179 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
180 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
181 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
182 RI_CLKSEL_L4 | RI_CLKSEL_L3
183 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
184 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
185 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
186 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
187 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
188 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
189 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
190 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
191 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
193 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
194 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
196 /* 2420-PRCM VII (boot) */
197 #define RVII_CLKSEL_L3 (1 << 0)
198 #define RVII_CLKSEL_L4 (1 << 5)
199 #define RVII_CLKSEL_DSS1 (1 << 8)
200 #define RVII_CLKSEL_DSS2 (0 << 13)
201 #define RVII_CLKSEL_VLYNQ (1 << 15)
202 #define RVII_CLKSEL_SSI (1 << 20)
203 #define RVII_CLKSEL_USB (1 << 25)
205 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
206 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
207 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
209 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
210 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
212 #define RVII_CLKSEL_DSP (1 << 0)
213 #define RVII_CLKSEL_DSP_IF (1 << 5)
214 #define RVII_SYNC_DSP (0 << 7)
215 #define RVII_CLKSEL_IVA (1 << 8)
216 #define RVII_SYNC_IVA (0 << 13)
217 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
218 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
220 #define RVII_CLKSEL_GFX (1 << 0)
221 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
223 /*-------------------------------------------------------------------------
224 * 2430 Target modes: Along with each configuration the CPU has several
225 * modes which goes along with them. Modes mainly are the addition of
226 * describe DPLL combinations to go along with a ratio.
227 *-------------------------------------------------------------------------*/
229 /* Hardware governed */
230 #define MX_48M_SRC (0 << 3)
231 #define MX_54M_SRC (0 << 5)
232 #define MX_APLLS_CLIKIN_12 (3 << 23)
233 #define MX_APLLS_CLIKIN_13 (2 << 23)
234 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
237 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
238 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
240 #define M5A_DPLL_MULT_12 (133 << 12)
241 #define M5A_DPLL_DIV_12 (5 << 8)
242 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
243 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
245 #define M5A_DPLL_MULT_13 (61 << 12)
246 #define M5A_DPLL_DIV_13 (2 << 8)
247 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
248 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
250 #define M5A_DPLL_MULT_19 (55 << 12)
251 #define M5A_DPLL_DIV_19 (3 << 8)
252 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
253 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
255 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
256 #define M5B_DPLL_MULT_12 (50 << 12)
257 #define M5B_DPLL_DIV_12 (2 << 8)
258 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
259 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
261 #define M5B_DPLL_MULT_13 (200 << 12)
262 #define M5B_DPLL_DIV_13 (12 << 8)
264 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
265 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
267 #define M5B_DPLL_MULT_19 (125 << 12)
268 #define M5B_DPLL_DIV_19 (31 << 8)
269 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
270 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
273 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
275 #define M4_DPLL_MULT_12 (133 << 12)
276 #define M4_DPLL_DIV_12 (3 << 8)
277 #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
278 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
281 #define M4_DPLL_MULT_13 (399 << 12)
282 #define M4_DPLL_DIV_13 (12 << 8)
283 #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
284 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
287 #define M4_DPLL_MULT_19 (145 << 12)
288 #define M4_DPLL_DIV_19 (6 << 8)
289 #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
290 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
294 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
296 #define M3_DPLL_MULT_12 (55 << 12)
297 #define M3_DPLL_DIV_12 (1 << 8)
298 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
299 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
301 #define M3_DPLL_MULT_13 (76 << 12)
302 #define M3_DPLL_DIV_13 (2 << 8)
303 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
304 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
306 #define M3_DPLL_MULT_19 (17 << 12)
307 #define M3_DPLL_DIV_19 (0 << 8)
308 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
309 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
313 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
315 #define M2_DPLL_MULT_12 (55 << 12)
316 #define M2_DPLL_DIV_12 (1 << 8)
317 #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
318 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
321 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
322 * relock time issue */
323 /* Core frequency changed from 330/165 to 329/164 MHz*/
324 #define M2_DPLL_MULT_13 (76 << 12)
325 #define M2_DPLL_DIV_13 (2 << 8)
326 #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
327 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
330 #define M2_DPLL_MULT_19 (17 << 12)
331 #define M2_DPLL_DIV_19 (0 << 8)
332 #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
333 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
337 #define MB_DPLL_MULT (1 << 12)
338 #define MB_DPLL_DIV (0 << 8)
339 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
340 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
342 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
343 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
345 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
346 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
349 * 2430 - chassis (sedna)
350 * 165 (ratio1) same as above #2
352 * 133 (ratio2) same as above #4
353 * 110 (ratio2) same as above #3
358 /* PRCM I target DPLL = 2*330MHz = 660MHz */
359 #define MI_DPLL_MULT_12 (55 << 12)
360 #define MI_DPLL_DIV_12 (1 << 8)
361 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
362 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
366 * 2420 Equivalent - mode registers
367 * PRCM II , target DPLL = 2*300MHz = 600MHz
369 #define MII_DPLL_MULT_12 (50 << 12)
370 #define MII_DPLL_DIV_12 (1 << 8)
371 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
372 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
374 #define MII_DPLL_MULT_13 (300 << 12)
375 #define MII_DPLL_DIV_13 (12 << 8)
376 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
377 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
380 /* PRCM III target DPLL = 2*266 = 532MHz*/
381 #define MIII_DPLL_MULT_12 (133 << 12)
382 #define MIII_DPLL_DIV_12 (5 << 8)
383 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
384 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
386 #define MIII_DPLL_MULT_13 (266 << 12)
387 #define MIII_DPLL_DIV_13 (12 << 8)
388 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
389 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
392 /* PRCM VII (boot bypass) */
393 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
394 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
396 /* High and low operation value */
397 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
398 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
400 /* MPU speed defines */
401 #define S12M 12000000
402 #define S13M 13000000
403 #define S19M 19200000
404 #define S26M 26000000
405 #define S100M 100000000
406 #define S133M 133000000
407 #define S150M 150000000
408 #define S164M 164000000
409 #define S165M 165000000
410 #define S199M 199000000
411 #define S200M 200000000
412 #define S266M 266000000
413 #define S300M 300000000
414 #define S329M 329000000
415 #define S330M 330000000
416 #define S399M 399000000
417 #define S400M 400000000
418 #define S532M 532000000
419 #define S600M 600000000
420 #define S658M 658000000
421 #define S660M 660000000
422 #define S798M 798000000
424 /*-------------------------------------------------------------------------
425 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
426 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
427 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
428 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
430 * Filling in table based on H4 boards and 2430-SDPs variants available.
431 * There are quite a few more rates combinations which could be defined.
433 * When multiple values are defined the start up will try and choose the
434 * fastest one. If a 'fast' value is defined, then automatically, the /2
435 * one should be included as it can be used. Generally having more that
436 * one fast set does not make sense, as static timings need to be changed
437 * to change the set. The exception is the bypass setting which is
438 * availble for low power bypass.
440 * Note: This table needs to be sorted, fastest to slowest.
441 *-------------------------------------------------------------------------*/
442 static struct prcm_config rate_table[] = {
444 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
445 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
446 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
447 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
451 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
452 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
453 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
454 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
457 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
458 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
459 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
460 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
463 /* PRCM III - FAST */
464 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
465 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
466 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
470 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
471 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
472 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
473 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
477 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
478 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
479 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
480 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
483 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
484 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
485 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
486 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
489 /* PRCM III - SLOW */
490 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
491 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
492 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
493 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
496 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
497 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
498 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
499 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
502 /* PRCM-VII (boot-bypass) */
503 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
504 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
505 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
506 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
509 /* PRCM-VII (boot-bypass) */
510 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
511 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
512 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
513 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
516 /* PRCM #4 - ratio2 (ES2.1) - FAST */
517 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
518 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
519 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
520 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
521 SDRC_RFR_CTRL_133MHz,
524 /* PRCM #2 - ratio1 (ES2) - FAST */
525 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
526 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
527 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
528 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
529 SDRC_RFR_CTRL_165MHz,
532 /* PRCM #5a - ratio1 - FAST */
533 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
534 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
535 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
536 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
537 SDRC_RFR_CTRL_133MHz,
540 /* PRCM #5b - ratio1 - FAST */
541 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
542 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
543 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
544 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
545 SDRC_RFR_CTRL_100MHz,
548 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
549 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
550 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
551 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
552 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
553 SDRC_RFR_CTRL_133MHz,
556 /* PRCM #2 - ratio1 (ES2) - SLOW */
557 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
558 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
559 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
560 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
561 SDRC_RFR_CTRL_165MHz,
564 /* PRCM #5a - ratio1 - SLOW */
565 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
566 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
567 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
568 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
569 SDRC_RFR_CTRL_133MHz,
572 /* PRCM #5b - ratio1 - SLOW*/
573 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
574 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
575 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
576 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
577 SDRC_RFR_CTRL_100MHz,
580 /* PRCM-boot/bypass */
581 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
582 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
583 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
584 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
585 SDRC_RFR_CTRL_BYPASS,
588 /* PRCM-boot/bypass */
589 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
590 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
591 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
592 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
593 SDRC_RFR_CTRL_BYPASS,
596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
599 /*-------------------------------------------------------------------------
602 * NOTE:In many cases here we are assigning a 'default' parent. In many
603 * cases the parent is selectable. The get/set parent calls will also
606 * Many some clocks say always_enabled, but they can be auto idled for
607 * power savings. They will always be available upon clock request.
609 * Several sources are given initial rates which may be wrong, this will
610 * be fixed up in the init func.
612 * Things are broadly separated below by clock domains. It is
613 * noteworthy that most periferals have dependencies on multiple clock
614 * domains. Many get their interface clocks from the L4 domain, but get
615 * functional clocks from fixed sources or other core domain derived
617 *-------------------------------------------------------------------------*/
619 /* Base external input clocks */
620 static struct clk func_32k_ck = {
621 .name = "func_32k_ck",
623 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
624 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
625 .clkdm_name = "wkup_clkdm",
626 .recalc = &propagate_rate,
629 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
630 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
632 .ops = &clkops_oscck,
633 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
635 .clkdm_name = "wkup_clkdm",
636 .recalc = &omap2_osc_clk_recalc,
639 /* Without modem likely 12MHz, with modem likely 13MHz */
640 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
641 .name = "sys_ck", /* ~ ref_clk also */
643 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
644 ALWAYS_ENABLED | RATE_PROPAGATES,
645 .clkdm_name = "wkup_clkdm",
646 .recalc = &omap2_sys_clk_recalc,
649 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
652 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
653 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
654 .clkdm_name = "wkup_clkdm",
655 .recalc = &propagate_rate,
659 * Analog domain root source clocks
662 /* dpll_ck, is broken out in to special cases through clksel */
663 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
667 static struct dpll_data dpll_dd = {
668 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
669 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
670 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
671 .max_multiplier = 1024,
673 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
677 * XXX Cannot add round_rate here yet, as this is still a composite clock,
680 static struct clk dpll_ck = {
682 .parent = &sys_ck, /* Can be func_32k also */
683 .dpll_data = &dpll_dd,
684 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
685 RATE_PROPAGATES | ALWAYS_ENABLED,
686 .clkdm_name = "wkup_clkdm",
687 .recalc = &omap2_dpllcore_recalc,
688 .set_rate = &omap2_reprogram_dpllcore,
691 static struct clk apll96_ck = {
693 .ops = &clkops_fixed,
696 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
697 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
698 .clkdm_name = "wkup_clkdm",
699 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
700 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
701 .recalc = &propagate_rate,
704 static struct clk apll54_ck = {
706 .ops = &clkops_fixed,
709 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
710 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
711 .clkdm_name = "wkup_clkdm",
712 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
713 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
714 .recalc = &propagate_rate,
718 * PRCM digital base sources
723 static const struct clksel_rate func_54m_apll54_rates[] = {
724 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
728 static const struct clksel_rate func_54m_alt_rates[] = {
729 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
733 static const struct clksel func_54m_clksel[] = {
734 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
735 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
739 static struct clk func_54m_ck = {
740 .name = "func_54m_ck",
741 .parent = &apll54_ck, /* can also be alt_clk */
742 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
743 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
744 .clkdm_name = "wkup_clkdm",
745 .init = &omap2_init_clksel_parent,
746 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
747 .clksel_mask = OMAP24XX_54M_SOURCE,
748 .clksel = func_54m_clksel,
749 .recalc = &omap2_clksel_recalc,
752 static struct clk core_ck = {
754 .parent = &dpll_ck, /* can also be 32k */
755 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
756 ALWAYS_ENABLED | RATE_PROPAGATES,
757 .clkdm_name = "wkup_clkdm",
758 .recalc = &followparent_recalc,
762 static const struct clksel_rate func_96m_apll96_rates[] = {
763 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
767 static const struct clksel_rate func_96m_alt_rates[] = {
768 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
772 static const struct clksel func_96m_clksel[] = {
773 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
774 { .parent = &alt_ck, .rates = func_96m_alt_rates },
778 /* The parent of this clock is not selectable on 2420. */
779 static struct clk func_96m_ck = {
780 .name = "func_96m_ck",
781 .parent = &apll96_ck,
782 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
783 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
784 .clkdm_name = "wkup_clkdm",
785 .init = &omap2_init_clksel_parent,
786 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
787 .clksel_mask = OMAP2430_96M_SOURCE,
788 .clksel = func_96m_clksel,
789 .recalc = &omap2_clksel_recalc,
790 .round_rate = &omap2_clksel_round_rate,
791 .set_rate = &omap2_clksel_set_rate
796 static const struct clksel_rate func_48m_apll96_rates[] = {
797 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
801 static const struct clksel_rate func_48m_alt_rates[] = {
802 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
806 static const struct clksel func_48m_clksel[] = {
807 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
808 { .parent = &alt_ck, .rates = func_48m_alt_rates },
812 static struct clk func_48m_ck = {
813 .name = "func_48m_ck",
814 .parent = &apll96_ck, /* 96M or Alt */
815 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
816 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
817 .clkdm_name = "wkup_clkdm",
818 .init = &omap2_init_clksel_parent,
819 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
820 .clksel_mask = OMAP24XX_48M_SOURCE,
821 .clksel = func_48m_clksel,
822 .recalc = &omap2_clksel_recalc,
823 .round_rate = &omap2_clksel_round_rate,
824 .set_rate = &omap2_clksel_set_rate
827 static struct clk func_12m_ck = {
828 .name = "func_12m_ck",
829 .parent = &func_48m_ck,
831 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
832 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
833 .clkdm_name = "wkup_clkdm",
834 .recalc = &omap2_fixed_divisor_recalc,
837 /* Secure timer, only available in secure mode */
838 static struct clk wdt1_osc_ck = {
839 .name = "ck_wdt1_osc",
841 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
842 .recalc = &followparent_recalc,
846 * The common_clkout* clksel_rate structs are common to
847 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
848 * sys_clkout2_* are 2420-only, so the
849 * clksel_rate flags fields are inaccurate for those clocks. This is
850 * harmless since access to those clocks are gated by the struct clk
851 * flags fields, which mark them as 2420-only.
853 static const struct clksel_rate common_clkout_src_core_rates[] = {
854 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
858 static const struct clksel_rate common_clkout_src_sys_rates[] = {
859 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
863 static const struct clksel_rate common_clkout_src_96m_rates[] = {
864 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
868 static const struct clksel_rate common_clkout_src_54m_rates[] = {
869 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
873 static const struct clksel common_clkout_src_clksel[] = {
874 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
875 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
876 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
877 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
881 static struct clk sys_clkout_src = {
882 .name = "sys_clkout_src",
883 .parent = &func_54m_ck,
884 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
886 .clkdm_name = "wkup_clkdm",
887 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
888 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
889 .init = &omap2_init_clksel_parent,
890 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
891 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
892 .clksel = common_clkout_src_clksel,
893 .recalc = &omap2_clksel_recalc,
894 .round_rate = &omap2_clksel_round_rate,
895 .set_rate = &omap2_clksel_set_rate
898 static const struct clksel_rate common_clkout_rates[] = {
899 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
900 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
901 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
902 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
903 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
907 static const struct clksel sys_clkout_clksel[] = {
908 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
912 static struct clk sys_clkout = {
913 .name = "sys_clkout",
914 .parent = &sys_clkout_src,
915 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
916 PARENT_CONTROLS_CLOCK,
917 .clkdm_name = "wkup_clkdm",
918 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
919 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
920 .clksel = sys_clkout_clksel,
921 .recalc = &omap2_clksel_recalc,
922 .round_rate = &omap2_clksel_round_rate,
923 .set_rate = &omap2_clksel_set_rate
926 /* In 2430, new in 2420 ES2 */
927 static struct clk sys_clkout2_src = {
928 .name = "sys_clkout2_src",
929 .parent = &func_54m_ck,
930 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
931 .clkdm_name = "wkup_clkdm",
932 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
933 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
934 .init = &omap2_init_clksel_parent,
935 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
936 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
937 .clksel = common_clkout_src_clksel,
938 .recalc = &omap2_clksel_recalc,
939 .round_rate = &omap2_clksel_round_rate,
940 .set_rate = &omap2_clksel_set_rate
943 static const struct clksel sys_clkout2_clksel[] = {
944 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
948 /* In 2430, new in 2420 ES2 */
949 static struct clk sys_clkout2 = {
950 .name = "sys_clkout2",
951 .parent = &sys_clkout2_src,
952 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
953 .clkdm_name = "wkup_clkdm",
954 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
955 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
956 .clksel = sys_clkout2_clksel,
957 .recalc = &omap2_clksel_recalc,
958 .round_rate = &omap2_clksel_round_rate,
959 .set_rate = &omap2_clksel_set_rate
962 static struct clk emul_ck = {
964 .parent = &func_54m_ck,
965 .flags = CLOCK_IN_OMAP242X,
966 .clkdm_name = "wkup_clkdm",
967 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
968 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
969 .recalc = &followparent_recalc,
977 * INT_M_FCLK, INT_M_I_CLK
979 * - Individual clocks are hardware managed.
980 * - Base divider comes from: CM_CLKSEL_MPU
983 static const struct clksel_rate mpu_core_rates[] = {
984 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
985 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
986 { .div = 4, .val = 4, .flags = RATE_IN_242X },
987 { .div = 6, .val = 6, .flags = RATE_IN_242X },
988 { .div = 8, .val = 8, .flags = RATE_IN_242X },
992 static const struct clksel mpu_clksel[] = {
993 { .parent = &core_ck, .rates = mpu_core_rates },
997 static struct clk mpu_ck = { /* Control cpu */
1000 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1001 ALWAYS_ENABLED | DELAYED_APP |
1002 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1003 .clkdm_name = "mpu_clkdm",
1004 .init = &omap2_init_clksel_parent,
1005 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1006 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
1007 .clksel = mpu_clksel,
1008 .recalc = &omap2_clksel_recalc,
1009 .round_rate = &omap2_clksel_round_rate,
1010 .set_rate = &omap2_clksel_set_rate
1014 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1016 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1017 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1019 * Won't be too specific here. The core clock comes into this block
1020 * it is divided then tee'ed. One branch goes directly to xyz enable
1021 * controls. The other branch gets further divided by 2 then possibly
1022 * routed into a synchronizer and out of clocks abc.
1024 static const struct clksel_rate dsp_fck_core_rates[] = {
1025 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1026 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1027 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1028 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1029 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1030 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1031 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1035 static const struct clksel dsp_fck_clksel[] = {
1036 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1040 static struct clk dsp_fck = {
1043 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1044 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1045 .clkdm_name = "dsp_clkdm",
1046 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1047 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1048 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1049 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1050 .clksel = dsp_fck_clksel,
1051 .recalc = &omap2_clksel_recalc,
1052 .round_rate = &omap2_clksel_round_rate,
1053 .set_rate = &omap2_clksel_set_rate
1056 /* DSP interface clock */
1057 static const struct clksel_rate dsp_irate_ick_rates[] = {
1058 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1059 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1060 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1064 static const struct clksel dsp_irate_ick_clksel[] = {
1065 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1069 /* This clock does not exist as such in the TRM. */
1070 static struct clk dsp_irate_ick = {
1071 .name = "dsp_irate_ick",
1073 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1074 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1075 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1076 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1077 .clksel = dsp_irate_ick_clksel,
1078 .recalc = &omap2_clksel_recalc,
1079 .round_rate = &omap2_clksel_round_rate,
1080 .set_rate = &omap2_clksel_set_rate
1084 static struct clk dsp_ick = {
1085 .name = "dsp_ick", /* apparently ipi and isp */
1086 .parent = &dsp_irate_ick,
1087 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1088 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1089 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1092 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1093 static struct clk iva2_1_ick = {
1094 .name = "iva2_1_ick",
1095 .parent = &dsp_irate_ick,
1096 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1097 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1098 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1102 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1103 * the C54x, but which is contained in the DSP powerdomain. Does not
1104 * exist on later OMAPs.
1106 static struct clk iva1_ifck = {
1107 .name = "iva1_ifck",
1109 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1110 RATE_PROPAGATES | DELAYED_APP,
1111 .clkdm_name = "iva1_clkdm",
1112 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1113 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1114 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1115 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1116 .clksel = dsp_fck_clksel,
1117 .recalc = &omap2_clksel_recalc,
1118 .round_rate = &omap2_clksel_round_rate,
1119 .set_rate = &omap2_clksel_set_rate
1122 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1123 static struct clk iva1_mpu_int_ifck = {
1124 .name = "iva1_mpu_int_ifck",
1125 .parent = &iva1_ifck,
1126 .flags = CLOCK_IN_OMAP242X,
1127 .clkdm_name = "iva1_clkdm",
1128 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1129 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1131 .recalc = &omap2_fixed_divisor_recalc,
1136 * L3 clocks are used for both interface and functional clocks to
1137 * multiple entities. Some of these clocks are completely managed
1138 * by hardware, and some others allow software control. Hardware
1139 * managed ones general are based on directly CLK_REQ signals and
1140 * various auto idle settings. The functional spec sets many of these
1141 * as 'tie-high' for their enables.
1144 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1149 * GPMC memories and SDRC have timing and clock sensitive registers which
1150 * may very well need notification when the clock changes. Currently for low
1151 * operating points, these are taken care of in sleep.S.
1153 static const struct clksel_rate core_l3_core_rates[] = {
1154 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1155 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1156 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1157 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1158 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1159 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1160 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1164 static const struct clksel core_l3_clksel[] = {
1165 { .parent = &core_ck, .rates = core_l3_core_rates },
1169 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1170 .name = "core_l3_ck",
1172 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1173 ALWAYS_ENABLED | DELAYED_APP |
1174 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1175 .clkdm_name = "core_l3_clkdm",
1176 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1177 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1178 .clksel = core_l3_clksel,
1179 .recalc = &omap2_clksel_recalc,
1180 .round_rate = &omap2_clksel_round_rate,
1181 .set_rate = &omap2_clksel_set_rate
1185 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1186 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1187 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1188 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1192 static const struct clksel usb_l4_ick_clksel[] = {
1193 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1197 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1198 static struct clk usb_l4_ick = { /* FS-USB interface clock */
1199 .name = "usb_l4_ick",
1200 .parent = &core_l3_ck,
1201 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1202 DELAYED_APP | CONFIG_PARTICIPANT,
1203 .clkdm_name = "core_l4_clkdm",
1204 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1205 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1206 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1207 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1208 .clksel = usb_l4_ick_clksel,
1209 .recalc = &omap2_clksel_recalc,
1210 .round_rate = &omap2_clksel_round_rate,
1211 .set_rate = &omap2_clksel_set_rate
1215 * L4 clock management domain
1217 * This domain contains lots of interface clocks from the L4 interface, some
1218 * functional clocks. Fixed APLL functional source clocks are managed in
1221 static const struct clksel_rate l4_core_l3_rates[] = {
1222 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1223 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1227 static const struct clksel l4_clksel[] = {
1228 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1232 static struct clk l4_ck = { /* used both as an ick and fck */
1234 .parent = &core_l3_ck,
1235 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1236 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1237 .clkdm_name = "core_l4_clkdm",
1238 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1239 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1240 .clksel = l4_clksel,
1241 .recalc = &omap2_clksel_recalc,
1242 .round_rate = &omap2_clksel_round_rate,
1243 .set_rate = &omap2_clksel_set_rate
1247 * SSI is in L3 management domain, its direct parent is core not l3,
1248 * many core power domain entities are grouped into the L3 clock
1250 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1252 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1254 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1255 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1256 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1257 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1258 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1259 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1260 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1261 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1265 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1266 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1270 static struct clk ssi_ssr_sst_fck = {
1273 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1275 .clkdm_name = "core_l3_clkdm",
1276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1277 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1278 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1279 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1280 .clksel = ssi_ssr_sst_fck_clksel,
1281 .recalc = &omap2_clksel_recalc,
1282 .round_rate = &omap2_clksel_round_rate,
1283 .set_rate = &omap2_clksel_set_rate
1290 * GFX_FCLK, GFX_ICLK
1291 * GFX_CG1(2d), GFX_CG2(3d)
1293 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1294 * The 2d and 3d clocks run at a hardware determined
1295 * divided value of fclk.
1298 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1300 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1301 static const struct clksel gfx_fck_clksel[] = {
1302 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1306 static struct clk gfx_3d_fck = {
1307 .name = "gfx_3d_fck",
1308 .parent = &core_l3_ck,
1309 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1310 .clkdm_name = "gfx_clkdm",
1311 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1312 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1313 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1314 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1315 .clksel = gfx_fck_clksel,
1316 .recalc = &omap2_clksel_recalc,
1317 .round_rate = &omap2_clksel_round_rate,
1318 .set_rate = &omap2_clksel_set_rate
1321 static struct clk gfx_2d_fck = {
1322 .name = "gfx_2d_fck",
1323 .parent = &core_l3_ck,
1324 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1325 .clkdm_name = "gfx_clkdm",
1326 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1327 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1328 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1329 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1330 .clksel = gfx_fck_clksel,
1331 .recalc = &omap2_clksel_recalc,
1332 .round_rate = &omap2_clksel_round_rate,
1333 .set_rate = &omap2_clksel_set_rate
1336 static struct clk gfx_ick = {
1337 .name = "gfx_ick", /* From l3 */
1338 .parent = &core_l3_ck,
1339 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1340 .clkdm_name = "gfx_clkdm",
1341 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1342 .enable_bit = OMAP_EN_GFX_SHIFT,
1343 .recalc = &followparent_recalc,
1347 * Modem clock domain (2430)
1351 * These clocks are usable in chassis mode only.
1353 static const struct clksel_rate mdm_ick_core_rates[] = {
1354 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1355 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1356 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1357 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1361 static const struct clksel mdm_ick_clksel[] = {
1362 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1366 static struct clk mdm_ick = { /* used both as a ick and fck */
1369 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1370 .clkdm_name = "mdm_clkdm",
1371 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1372 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1373 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1374 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1375 .clksel = mdm_ick_clksel,
1376 .recalc = &omap2_clksel_recalc,
1377 .round_rate = &omap2_clksel_round_rate,
1378 .set_rate = &omap2_clksel_set_rate
1381 static struct clk mdm_osc_ck = {
1382 .name = "mdm_osc_ck",
1384 .flags = CLOCK_IN_OMAP243X,
1385 .clkdm_name = "mdm_clkdm",
1386 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1387 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1388 .recalc = &followparent_recalc,
1394 * DSS_L4_ICLK, DSS_L3_ICLK,
1395 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1397 * DSS is both initiator and target.
1399 /* XXX Add RATE_NOT_VALIDATED */
1401 static const struct clksel_rate dss1_fck_sys_rates[] = {
1402 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1406 static const struct clksel_rate dss1_fck_core_rates[] = {
1407 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1408 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1409 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1410 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1411 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1412 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1413 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1414 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1415 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1416 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1420 static const struct clksel dss1_fck_clksel[] = {
1421 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1422 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1426 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1428 .parent = &l4_ck, /* really both l3 and l4 */
1429 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1430 .clkdm_name = "dss_clkdm",
1431 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1432 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1433 .recalc = &followparent_recalc,
1436 static struct clk dss1_fck = {
1438 .parent = &core_ck, /* Core or sys */
1439 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1441 .clkdm_name = "dss_clkdm",
1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1444 .init = &omap2_init_clksel_parent,
1445 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1446 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1447 .clksel = dss1_fck_clksel,
1448 .recalc = &omap2_clksel_recalc,
1449 .round_rate = &omap2_clksel_round_rate,
1450 .set_rate = &omap2_clksel_set_rate
1453 static const struct clksel_rate dss2_fck_sys_rates[] = {
1454 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1458 static const struct clksel_rate dss2_fck_48m_rates[] = {
1459 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1463 static const struct clksel dss2_fck_clksel[] = {
1464 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1465 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1469 static struct clk dss2_fck = { /* Alt clk used in power management */
1471 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1472 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1474 .clkdm_name = "dss_clkdm",
1475 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1476 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1477 .init = &omap2_init_clksel_parent,
1478 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1479 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1480 .clksel = dss2_fck_clksel,
1481 .recalc = &followparent_recalc,
1484 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1485 .name = "dss_54m_fck", /* 54m tv clk */
1486 .parent = &func_54m_ck,
1487 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1488 .clkdm_name = "dss_clkdm",
1489 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1490 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1491 .recalc = &followparent_recalc,
1495 * CORE power domain ICLK & FCLK defines.
1496 * Many of the these can have more than one possible parent. Entries
1497 * here will likely have an L4 interface parent, and may have multiple
1498 * functional clock parents.
1500 static const struct clksel_rate gpt_alt_rates[] = {
1501 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1505 static const struct clksel omap24xx_gpt_clksel[] = {
1506 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1507 { .parent = &sys_ck, .rates = gpt_sys_rates },
1508 { .parent = &alt_ck, .rates = gpt_alt_rates },
1512 static struct clk gpt1_ick = {
1515 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1516 .clkdm_name = "core_l4_clkdm",
1517 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1518 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1519 .recalc = &followparent_recalc,
1522 static struct clk gpt1_fck = {
1524 .parent = &func_32k_ck,
1525 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1526 .clkdm_name = "core_l4_clkdm",
1527 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1528 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1529 .init = &omap2_init_clksel_parent,
1530 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1531 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1532 .clksel = omap24xx_gpt_clksel,
1533 .recalc = &omap2_clksel_recalc,
1534 .round_rate = &omap2_clksel_round_rate,
1535 .set_rate = &omap2_clksel_set_rate
1538 static struct clk gpt2_ick = {
1541 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1542 .clkdm_name = "core_l4_clkdm",
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1544 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1545 .recalc = &followparent_recalc,
1548 static struct clk gpt2_fck = {
1550 .parent = &func_32k_ck,
1551 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1552 .clkdm_name = "core_l4_clkdm",
1553 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1554 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1555 .init = &omap2_init_clksel_parent,
1556 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1557 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1558 .clksel = omap24xx_gpt_clksel,
1559 .recalc = &omap2_clksel_recalc,
1562 static struct clk gpt3_ick = {
1565 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1566 .clkdm_name = "core_l4_clkdm",
1567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1568 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1569 .recalc = &followparent_recalc,
1572 static struct clk gpt3_fck = {
1574 .parent = &func_32k_ck,
1575 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1576 .clkdm_name = "core_l4_clkdm",
1577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1578 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1579 .init = &omap2_init_clksel_parent,
1580 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1581 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1582 .clksel = omap24xx_gpt_clksel,
1583 .recalc = &omap2_clksel_recalc,
1586 static struct clk gpt4_ick = {
1589 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1590 .clkdm_name = "core_l4_clkdm",
1591 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1592 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1593 .recalc = &followparent_recalc,
1596 static struct clk gpt4_fck = {
1598 .parent = &func_32k_ck,
1599 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1600 .clkdm_name = "core_l4_clkdm",
1601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1603 .init = &omap2_init_clksel_parent,
1604 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1605 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1606 .clksel = omap24xx_gpt_clksel,
1607 .recalc = &omap2_clksel_recalc,
1610 static struct clk gpt5_ick = {
1613 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1614 .clkdm_name = "core_l4_clkdm",
1615 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1616 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1617 .recalc = &followparent_recalc,
1620 static struct clk gpt5_fck = {
1622 .parent = &func_32k_ck,
1623 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1624 .clkdm_name = "core_l4_clkdm",
1625 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1626 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1627 .init = &omap2_init_clksel_parent,
1628 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1629 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1630 .clksel = omap24xx_gpt_clksel,
1631 .recalc = &omap2_clksel_recalc,
1634 static struct clk gpt6_ick = {
1637 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1638 .clkdm_name = "core_l4_clkdm",
1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1640 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1641 .recalc = &followparent_recalc,
1644 static struct clk gpt6_fck = {
1646 .parent = &func_32k_ck,
1647 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1648 .clkdm_name = "core_l4_clkdm",
1649 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1650 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1651 .init = &omap2_init_clksel_parent,
1652 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1653 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1654 .clksel = omap24xx_gpt_clksel,
1655 .recalc = &omap2_clksel_recalc,
1658 static struct clk gpt7_ick = {
1661 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1662 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1663 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1664 .recalc = &followparent_recalc,
1667 static struct clk gpt7_fck = {
1669 .parent = &func_32k_ck,
1670 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1671 .clkdm_name = "core_l4_clkdm",
1672 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1673 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1674 .init = &omap2_init_clksel_parent,
1675 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1676 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1677 .clksel = omap24xx_gpt_clksel,
1678 .recalc = &omap2_clksel_recalc,
1681 static struct clk gpt8_ick = {
1684 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1685 .clkdm_name = "core_l4_clkdm",
1686 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1687 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1688 .recalc = &followparent_recalc,
1691 static struct clk gpt8_fck = {
1693 .parent = &func_32k_ck,
1694 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1695 .clkdm_name = "core_l4_clkdm",
1696 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1697 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1698 .init = &omap2_init_clksel_parent,
1699 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1700 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1701 .clksel = omap24xx_gpt_clksel,
1702 .recalc = &omap2_clksel_recalc,
1705 static struct clk gpt9_ick = {
1708 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1709 .clkdm_name = "core_l4_clkdm",
1710 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1711 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1712 .recalc = &followparent_recalc,
1715 static struct clk gpt9_fck = {
1717 .parent = &func_32k_ck,
1718 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1719 .clkdm_name = "core_l4_clkdm",
1720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1721 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1722 .init = &omap2_init_clksel_parent,
1723 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1724 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1725 .clksel = omap24xx_gpt_clksel,
1726 .recalc = &omap2_clksel_recalc,
1729 static struct clk gpt10_ick = {
1730 .name = "gpt10_ick",
1732 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1733 .clkdm_name = "core_l4_clkdm",
1734 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1735 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1736 .recalc = &followparent_recalc,
1739 static struct clk gpt10_fck = {
1740 .name = "gpt10_fck",
1741 .parent = &func_32k_ck,
1742 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1743 .clkdm_name = "core_l4_clkdm",
1744 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1745 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1746 .init = &omap2_init_clksel_parent,
1747 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1748 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1749 .clksel = omap24xx_gpt_clksel,
1750 .recalc = &omap2_clksel_recalc,
1753 static struct clk gpt11_ick = {
1754 .name = "gpt11_ick",
1756 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1757 .clkdm_name = "core_l4_clkdm",
1758 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1759 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1760 .recalc = &followparent_recalc,
1763 static struct clk gpt11_fck = {
1764 .name = "gpt11_fck",
1765 .parent = &func_32k_ck,
1766 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1767 .clkdm_name = "core_l4_clkdm",
1768 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1769 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1770 .init = &omap2_init_clksel_parent,
1771 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1772 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1773 .clksel = omap24xx_gpt_clksel,
1774 .recalc = &omap2_clksel_recalc,
1777 static struct clk gpt12_ick = {
1778 .name = "gpt12_ick",
1780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1781 .clkdm_name = "core_l4_clkdm",
1782 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1783 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1784 .recalc = &followparent_recalc,
1787 static struct clk gpt12_fck = {
1788 .name = "gpt12_fck",
1789 .parent = &func_32k_ck,
1790 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1791 .clkdm_name = "core_l4_clkdm",
1792 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1793 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1794 .init = &omap2_init_clksel_parent,
1795 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1796 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1797 .clksel = omap24xx_gpt_clksel,
1798 .recalc = &omap2_clksel_recalc,
1801 static struct clk mcbsp1_ick = {
1802 .name = "mcbsp_ick",
1805 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1806 .clkdm_name = "core_l4_clkdm",
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1809 .recalc = &followparent_recalc,
1812 static struct clk mcbsp1_fck = {
1813 .name = "mcbsp_fck",
1815 .parent = &func_96m_ck,
1816 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1817 .clkdm_name = "core_l4_clkdm",
1818 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1819 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1820 .recalc = &followparent_recalc,
1823 static struct clk mcbsp2_ick = {
1824 .name = "mcbsp_ick",
1827 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1828 .clkdm_name = "core_l4_clkdm",
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1831 .recalc = &followparent_recalc,
1834 static struct clk mcbsp2_fck = {
1835 .name = "mcbsp_fck",
1837 .parent = &func_96m_ck,
1838 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1839 .clkdm_name = "core_l4_clkdm",
1840 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1841 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1842 .recalc = &followparent_recalc,
1845 static struct clk mcbsp3_ick = {
1846 .name = "mcbsp_ick",
1849 .flags = CLOCK_IN_OMAP243X,
1850 .clkdm_name = "core_l4_clkdm",
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1852 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1853 .recalc = &followparent_recalc,
1856 static struct clk mcbsp3_fck = {
1857 .name = "mcbsp_fck",
1859 .parent = &func_96m_ck,
1860 .flags = CLOCK_IN_OMAP243X,
1861 .clkdm_name = "core_l4_clkdm",
1862 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1863 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1864 .recalc = &followparent_recalc,
1867 static struct clk mcbsp4_ick = {
1868 .name = "mcbsp_ick",
1871 .flags = CLOCK_IN_OMAP243X,
1872 .clkdm_name = "core_l4_clkdm",
1873 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1874 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1875 .recalc = &followparent_recalc,
1878 static struct clk mcbsp4_fck = {
1879 .name = "mcbsp_fck",
1881 .parent = &func_96m_ck,
1882 .flags = CLOCK_IN_OMAP243X,
1883 .clkdm_name = "core_l4_clkdm",
1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1885 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1886 .recalc = &followparent_recalc,
1889 static struct clk mcbsp5_ick = {
1890 .name = "mcbsp_ick",
1893 .flags = CLOCK_IN_OMAP243X,
1894 .clkdm_name = "core_l4_clkdm",
1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1896 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1897 .recalc = &followparent_recalc,
1900 static struct clk mcbsp5_fck = {
1901 .name = "mcbsp_fck",
1903 .parent = &func_96m_ck,
1904 .flags = CLOCK_IN_OMAP243X,
1905 .clkdm_name = "core_l4_clkdm",
1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1907 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1908 .recalc = &followparent_recalc,
1911 static struct clk mcspi1_ick = {
1912 .name = "mcspi_ick",
1915 .clkdm_name = "core_l4_clkdm",
1916 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1918 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1919 .recalc = &followparent_recalc,
1922 static struct clk mcspi1_fck = {
1923 .name = "mcspi_fck",
1925 .parent = &func_48m_ck,
1926 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1927 .clkdm_name = "core_l4_clkdm",
1928 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1929 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1930 .recalc = &followparent_recalc,
1933 static struct clk mcspi2_ick = {
1934 .name = "mcspi_ick",
1937 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1938 .clkdm_name = "core_l4_clkdm",
1939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1940 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1941 .recalc = &followparent_recalc,
1944 static struct clk mcspi2_fck = {
1945 .name = "mcspi_fck",
1947 .parent = &func_48m_ck,
1948 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1949 .clkdm_name = "core_l4_clkdm",
1950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1951 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1952 .recalc = &followparent_recalc,
1955 static struct clk mcspi3_ick = {
1956 .name = "mcspi_ick",
1959 .flags = CLOCK_IN_OMAP243X,
1960 .clkdm_name = "core_l4_clkdm",
1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1962 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1963 .recalc = &followparent_recalc,
1966 static struct clk mcspi3_fck = {
1967 .name = "mcspi_fck",
1969 .parent = &func_48m_ck,
1970 .flags = CLOCK_IN_OMAP243X,
1971 .clkdm_name = "core_l4_clkdm",
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1973 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1974 .recalc = &followparent_recalc,
1977 static struct clk uart1_ick = {
1978 .name = "uart1_ick",
1980 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1981 .clkdm_name = "core_l4_clkdm",
1982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1984 .recalc = &followparent_recalc,
1987 static struct clk uart1_fck = {
1988 .name = "uart1_fck",
1989 .parent = &func_48m_ck,
1990 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1991 .clkdm_name = "core_l4_clkdm",
1992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1993 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1994 .recalc = &followparent_recalc,
1997 static struct clk uart2_ick = {
1998 .name = "uart2_ick",
2000 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2001 .clkdm_name = "core_l4_clkdm",
2002 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2004 .recalc = &followparent_recalc,
2007 static struct clk uart2_fck = {
2008 .name = "uart2_fck",
2009 .parent = &func_48m_ck,
2010 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2011 .clkdm_name = "core_l4_clkdm",
2012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2013 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2014 .recalc = &followparent_recalc,
2017 static struct clk uart3_ick = {
2018 .name = "uart3_ick",
2020 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2021 .clkdm_name = "core_l4_clkdm",
2022 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2023 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2024 .recalc = &followparent_recalc,
2027 static struct clk uart3_fck = {
2028 .name = "uart3_fck",
2029 .parent = &func_48m_ck,
2030 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2031 .clkdm_name = "core_l4_clkdm",
2032 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2033 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2034 .recalc = &followparent_recalc,
2037 static struct clk gpios_ick = {
2038 .name = "gpios_ick",
2040 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2041 .clkdm_name = "core_l4_clkdm",
2042 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2043 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2044 .recalc = &followparent_recalc,
2047 static struct clk gpios_fck = {
2048 .name = "gpios_fck",
2049 .parent = &func_32k_ck,
2050 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2051 .clkdm_name = "wkup_clkdm",
2052 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2053 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2054 .recalc = &followparent_recalc,
2057 static struct clk mpu_wdt_ick = {
2058 .name = "mpu_wdt_ick",
2060 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2061 .clkdm_name = "core_l4_clkdm",
2062 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2063 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2064 .recalc = &followparent_recalc,
2067 static struct clk mpu_wdt_fck = {
2068 .name = "mpu_wdt_fck",
2069 .parent = &func_32k_ck,
2070 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2071 .clkdm_name = "wkup_clkdm",
2072 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2073 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2074 .recalc = &followparent_recalc,
2077 static struct clk sync_32k_ick = {
2078 .name = "sync_32k_ick",
2080 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2082 .clkdm_name = "core_l4_clkdm",
2083 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2084 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2085 .recalc = &followparent_recalc,
2088 static struct clk wdt1_ick = {
2091 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2092 .clkdm_name = "core_l4_clkdm",
2093 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2094 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2095 .recalc = &followparent_recalc,
2098 static struct clk omapctrl_ick = {
2099 .name = "omapctrl_ick",
2101 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2103 .clkdm_name = "core_l4_clkdm",
2104 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2105 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2106 .recalc = &followparent_recalc,
2109 static struct clk icr_ick = {
2112 .flags = CLOCK_IN_OMAP243X,
2113 .clkdm_name = "core_l4_clkdm",
2114 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2115 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2116 .recalc = &followparent_recalc,
2119 static struct clk cam_ick = {
2122 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2123 .clkdm_name = "core_l4_clkdm",
2124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2125 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2126 .recalc = &followparent_recalc,
2130 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2131 * split into two separate clocks, since the parent clocks are different
2132 * and the clockdomains are also different.
2134 static struct clk cam_fck = {
2136 .parent = &func_96m_ck,
2137 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2138 .clkdm_name = "core_l3_clkdm",
2139 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2140 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2141 .recalc = &followparent_recalc,
2144 static struct clk mailboxes_ick = {
2145 .name = "mailboxes_ick",
2147 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2148 .clkdm_name = "core_l4_clkdm",
2149 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2150 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2151 .recalc = &followparent_recalc,
2154 static struct clk wdt4_ick = {
2157 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2158 .clkdm_name = "core_l4_clkdm",
2159 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2160 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2161 .recalc = &followparent_recalc,
2164 static struct clk wdt4_fck = {
2166 .parent = &func_32k_ck,
2167 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2168 .clkdm_name = "core_l4_clkdm",
2169 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2170 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2171 .recalc = &followparent_recalc,
2174 static struct clk wdt3_ick = {
2177 .flags = CLOCK_IN_OMAP242X,
2178 .clkdm_name = "core_l4_clkdm",
2179 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2180 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2181 .recalc = &followparent_recalc,
2184 static struct clk wdt3_fck = {
2186 .parent = &func_32k_ck,
2187 .flags = CLOCK_IN_OMAP242X,
2188 .clkdm_name = "core_l4_clkdm",
2189 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2190 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2191 .recalc = &followparent_recalc,
2194 static struct clk mspro_ick = {
2195 .name = "mspro_ick",
2197 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2198 .clkdm_name = "core_l4_clkdm",
2199 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2200 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2201 .recalc = &followparent_recalc,
2204 static struct clk mspro_fck = {
2205 .name = "mspro_fck",
2206 .parent = &func_96m_ck,
2207 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2208 .clkdm_name = "core_l4_clkdm",
2209 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2210 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2211 .recalc = &followparent_recalc,
2214 static struct clk mmc_ick = {
2217 .flags = CLOCK_IN_OMAP242X,
2218 .clkdm_name = "core_l4_clkdm",
2219 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2220 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2221 .recalc = &followparent_recalc,
2224 static struct clk mmc_fck = {
2226 .parent = &func_96m_ck,
2227 .flags = CLOCK_IN_OMAP242X,
2228 .clkdm_name = "core_l4_clkdm",
2229 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2230 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2231 .recalc = &followparent_recalc,
2234 static struct clk fac_ick = {
2237 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2238 .clkdm_name = "core_l4_clkdm",
2239 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2240 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2241 .recalc = &followparent_recalc,
2244 static struct clk fac_fck = {
2246 .parent = &func_12m_ck,
2247 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2248 .clkdm_name = "core_l4_clkdm",
2249 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2250 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2251 .recalc = &followparent_recalc,
2254 static struct clk eac_ick = {
2257 .flags = CLOCK_IN_OMAP242X,
2258 .clkdm_name = "core_l4_clkdm",
2259 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2260 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2261 .recalc = &followparent_recalc,
2264 static struct clk eac_fck = {
2266 .parent = &func_96m_ck,
2267 .flags = CLOCK_IN_OMAP242X,
2268 .clkdm_name = "core_l4_clkdm",
2269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2270 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2271 .recalc = &followparent_recalc,
2274 static struct clk hdq_ick = {
2277 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2278 .clkdm_name = "core_l4_clkdm",
2279 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2280 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2281 .recalc = &followparent_recalc,
2284 static struct clk hdq_fck = {
2286 .parent = &func_12m_ck,
2287 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2288 .clkdm_name = "core_l4_clkdm",
2289 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2290 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2291 .recalc = &followparent_recalc,
2294 static struct clk i2c2_ick = {
2298 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2299 .clkdm_name = "core_l4_clkdm",
2300 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2301 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2302 .recalc = &followparent_recalc,
2305 static struct clk i2c2_fck = {
2308 .parent = &func_12m_ck,
2309 .flags = CLOCK_IN_OMAP242X,
2310 .clkdm_name = "core_l4_clkdm",
2311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2312 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2313 .recalc = &followparent_recalc,
2316 static struct clk i2chs2_fck = {
2319 .parent = &func_96m_ck,
2320 .flags = CLOCK_IN_OMAP243X,
2321 .clkdm_name = "core_l4_clkdm",
2322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2323 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2324 .recalc = &followparent_recalc,
2327 static struct clk i2c1_ick = {
2331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2332 .clkdm_name = "core_l4_clkdm",
2333 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2334 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2335 .recalc = &followparent_recalc,
2338 static struct clk i2c1_fck = {
2341 .parent = &func_12m_ck,
2342 .flags = CLOCK_IN_OMAP242X,
2343 .clkdm_name = "core_l4_clkdm",
2344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2345 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2346 .recalc = &followparent_recalc,
2349 static struct clk i2chs1_fck = {
2352 .parent = &func_96m_ck,
2353 .flags = CLOCK_IN_OMAP243X,
2354 .clkdm_name = "core_l4_clkdm",
2355 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2356 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2357 .recalc = &followparent_recalc,
2360 static struct clk gpmc_fck = {
2362 .parent = &core_l3_ck,
2363 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2365 .clkdm_name = "core_l3_clkdm",
2366 .recalc = &followparent_recalc,
2369 static struct clk sdma_fck = {
2371 .parent = &core_l3_ck,
2372 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2373 .clkdm_name = "core_l3_clkdm",
2374 .recalc = &followparent_recalc,
2377 static struct clk sdma_ick = {
2380 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2381 .clkdm_name = "core_l3_clkdm",
2382 .recalc = &followparent_recalc,
2385 static struct clk vlynq_ick = {
2386 .name = "vlynq_ick",
2387 .parent = &core_l3_ck,
2388 .flags = CLOCK_IN_OMAP242X,
2389 .clkdm_name = "core_l3_clkdm",
2390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2391 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2392 .recalc = &followparent_recalc,
2395 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2396 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2400 static const struct clksel_rate vlynq_fck_core_rates[] = {
2401 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2402 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2403 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2404 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2405 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2406 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2407 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2408 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2409 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2410 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2414 static const struct clksel vlynq_fck_clksel[] = {
2415 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2416 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2420 static struct clk vlynq_fck = {
2421 .name = "vlynq_fck",
2422 .parent = &func_96m_ck,
2423 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
2424 .clkdm_name = "core_l3_clkdm",
2425 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2426 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2427 .init = &omap2_init_clksel_parent,
2428 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2429 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2430 .clksel = vlynq_fck_clksel,
2431 .recalc = &omap2_clksel_recalc,
2432 .round_rate = &omap2_clksel_round_rate,
2433 .set_rate = &omap2_clksel_set_rate
2436 static struct clk sdrc_ick = {
2439 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2440 .clkdm_name = "core_l4_clkdm",
2441 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2442 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2443 .recalc = &followparent_recalc,
2446 static struct clk des_ick = {
2449 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2450 .clkdm_name = "core_l4_clkdm",
2451 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2452 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2453 .recalc = &followparent_recalc,
2456 static struct clk sha_ick = {
2459 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2460 .clkdm_name = "core_l4_clkdm",
2461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2462 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2463 .recalc = &followparent_recalc,
2466 static struct clk rng_ick = {
2469 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2470 .clkdm_name = "core_l4_clkdm",
2471 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2472 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2473 .recalc = &followparent_recalc,
2476 static struct clk aes_ick = {
2479 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2480 .clkdm_name = "core_l4_clkdm",
2481 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2482 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2483 .recalc = &followparent_recalc,
2486 static struct clk pka_ick = {
2489 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2490 .clkdm_name = "core_l4_clkdm",
2491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2492 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2493 .recalc = &followparent_recalc,
2496 static struct clk usb_fck = {
2498 .parent = &func_48m_ck,
2499 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2500 .clkdm_name = "core_l3_clkdm",
2501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2502 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2503 .recalc = &followparent_recalc,
2506 static struct clk usbhs_ick = {
2507 .name = "usbhs_ick",
2508 .parent = &core_l3_ck,
2509 .flags = CLOCK_IN_OMAP243X,
2510 .clkdm_name = "core_l3_clkdm",
2511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2512 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2513 .recalc = &followparent_recalc,
2516 static struct clk mmchs1_ick = {
2517 .name = "mmchs_ick",
2519 .flags = CLOCK_IN_OMAP243X,
2520 .clkdm_name = "core_l4_clkdm",
2521 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2522 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2523 .recalc = &followparent_recalc,
2526 static struct clk mmchs1_fck = {
2527 .name = "mmchs_fck",
2528 .parent = &func_96m_ck,
2529 .flags = CLOCK_IN_OMAP243X,
2530 .clkdm_name = "core_l3_clkdm",
2531 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2532 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2533 .recalc = &followparent_recalc,
2536 static struct clk mmchs2_ick = {
2537 .name = "mmchs_ick",
2540 .flags = CLOCK_IN_OMAP243X,
2541 .clkdm_name = "core_l4_clkdm",
2542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2543 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2544 .recalc = &followparent_recalc,
2547 static struct clk mmchs2_fck = {
2548 .name = "mmchs_fck",
2550 .parent = &func_96m_ck,
2551 .flags = CLOCK_IN_OMAP243X,
2552 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2553 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2554 .recalc = &followparent_recalc,
2557 static struct clk gpio5_ick = {
2558 .name = "gpio5_ick",
2560 .flags = CLOCK_IN_OMAP243X,
2561 .clkdm_name = "core_l4_clkdm",
2562 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2563 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2564 .recalc = &followparent_recalc,
2567 static struct clk gpio5_fck = {
2568 .name = "gpio5_fck",
2569 .parent = &func_32k_ck,
2570 .flags = CLOCK_IN_OMAP243X,
2571 .clkdm_name = "core_l4_clkdm",
2572 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2573 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2574 .recalc = &followparent_recalc,
2577 static struct clk mdm_intc_ick = {
2578 .name = "mdm_intc_ick",
2580 .flags = CLOCK_IN_OMAP243X,
2581 .clkdm_name = "core_l4_clkdm",
2582 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2583 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2584 .recalc = &followparent_recalc,
2587 static struct clk mmchsdb1_fck = {
2588 .name = "mmchsdb_fck",
2589 .parent = &func_32k_ck,
2590 .flags = CLOCK_IN_OMAP243X,
2591 .clkdm_name = "core_l4_clkdm",
2592 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2593 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2594 .recalc = &followparent_recalc,
2597 static struct clk mmchsdb2_fck = {
2598 .name = "mmchsdb_fck",
2600 .parent = &func_32k_ck,
2601 .flags = CLOCK_IN_OMAP243X,
2602 .clkdm_name = "core_l4_clkdm",
2603 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2604 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2605 .recalc = &followparent_recalc,
2609 * This clock is a composite clock which does entire set changes then
2610 * forces a rebalance. It keys on the MPU speed, but it really could
2611 * be any key speed part of a set in the rate table.
2613 * to really change a set, you need memory table sets which get changed
2614 * in sram, pre-notifiers & post notifiers, changing the top set, without
2615 * having low level display recalc's won't work... this is why dpm notifiers
2616 * work, isr's off, walk a list of clocks already _off_ and not messing with
2619 * This clock should have no parent. It embodies the entire upper level
2620 * active set. A parent will mess up some of the init also.
2622 static struct clk virt_prcm_set = {
2623 .name = "virt_prcm_set",
2624 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2625 ALWAYS_ENABLED | DELAYED_APP,
2626 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2627 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2628 .set_rate = &omap2_select_table_rate,
2629 .round_rate = &omap2_round_to_table_rate,
2632 static struct clk *onchip_24xx_clks[] __initdata = {
2633 /* external root sources */
2638 /* internal analog sources */
2642 /* internal prcm root sources */
2654 /* mpu domain clocks */
2656 /* dsp domain clocks */
2659 &dsp_ick, /* 242x */
2660 &iva2_1_ick, /* 243x */
2661 &iva1_ifck, /* 242x */
2662 &iva1_mpu_int_ifck, /* 242x */
2663 /* GFX domain clocks */
2667 /* Modem domain clocks */
2670 /* DSS domain clocks */
2675 /* L3 domain clocks */
2679 /* L4 domain clocks */
2680 &l4_ck, /* used as both core_l4 and wu_l4 */
2681 /* virtual meta-group clock */
2683 /* general l4 interface ck, multi-parent functional clk */