arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <plat/cpu.h>
  26 #include <plat/usb.h>
  27 #include <plat/clock.h>
  28 #include <plat/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 static int clk_omap1_dummy_enable(struct clk *clk)
  37 {
  38         return 0;
  39 }
  40
  41 static void clk_omap1_dummy_disable(struct clk *clk)
  42 {
  43 }
  44
  45 static const struct clkops clkops_dummy = {
  46         .enable = clk_omap1_dummy_enable,
  47         .disable = clk_omap1_dummy_disable,
  48 };
  49
  50 static struct clk dummy_ck = {
  51         .name   = "dummy",
  52         .ops    = &clkops_dummy,
  53         .flags  = RATE_FIXED,
  54 };
  55
  56 struct omap_clk {
  57         u32             cpu;
  58         struct clk_lookup lk;
  59 };
  60
  61 #define CLK(dev, con, ck, cp)           \
  62         {                               \
  63                  .cpu = cp,             \
  64                 .lk = {                 \
  65                         .dev_id = dev,  \
  66                         .con_id = con,  \
  67                         .clk = ck,      \
  68                 },                      \
  69         }
  70
  71 #define CK_310  (1 << 0)
  72 #define CK_7XX  (1 << 1)
  73 #define CK_1510 (1 << 2)
  74 #define CK_16XX (1 << 3)
  75
  76 static struct omap_clk omap_clks[] = {
  77         /* non-ULPD clocks */
  78         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
  79         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  80         /* CK_GEN1 clocks */
  81         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  82         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  83         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  85         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  86         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
  87         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  88         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  89         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
  90         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
  91         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  92         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  93         /* CK_GEN2 clocks */
  94         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  96         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  97         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  98         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  99         /* CK_GEN3 clocks */
 100         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 101         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 102         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
 103         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 104         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 105         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 106         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 107         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
 108         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 109         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 110         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 111         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 112         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 113         /* ULPD clocks */
 114         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 115         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 116         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 117         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 118         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 119         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 120         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 121         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 122         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 123         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
 124         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 125         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 126         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 127         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 128         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 129         CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
 130         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 131         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 132         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 133         /* Virtual clocks */
 134         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 135         CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 136         CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
 137         CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310),
 138         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 139         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 140         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 141         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 142         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 143         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 144         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 145         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 146         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 147         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 148 };
 149
 150 static int omap1_clk_enable_generic(struct clk * clk);
 151 static int omap1_clk_enable(struct clk *clk);
 152 static void omap1_clk_disable_generic(struct clk * clk);
 153 static void omap1_clk_disable(struct clk *clk);
 154
 155 __u32 arm_idlect1_mask;
 156
 157 /*-------------------------------------------------------------------------
 158  * Omap1 specific clock functions
 159  *-------------------------------------------------------------------------*/
 160
 161 static unsigned long omap1_watchdog_recalc(struct clk *clk)
 162 {
 163         return clk->parent->rate / 14;
 164 }
 165
 166 static unsigned long omap1_uart_recalc(struct clk *clk)
 167 {
 168         unsigned int val = __raw_readl(clk->enable_reg);
 169         return val & clk->enable_bit ? 48000000 : 12000000;
 170 }
 171
 172 static unsigned long omap1_sossi_recalc(struct clk *clk)
 173 {
 174         u32 div = omap_readl(MOD_CONF_CTRL_1);
 175
 176         div = (div >> 17) & 0x7;
 177         div++;
 178
 179         return clk->parent->rate / div;
 180 }
 181
 182 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 183 {
 184         int retval;
 185
 186         retval = omap1_clk_enable(&api_ck.clk);
 187         if (!retval) {
 188                 retval = omap1_clk_enable_generic(clk);
 189                 omap1_clk_disable(&api_ck.clk);
 190         }
 191
 192         return retval;
 193 }
 194
 195 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 196 {
 197         if (omap1_clk_enable(&api_ck.clk) == 0) {
 198                 omap1_clk_disable_generic(clk);
 199                 omap1_clk_disable(&api_ck.clk);
 200         }
 201 }
 202
 203 static const struct clkops clkops_dspck = {
 204         .enable         = &omap1_clk_enable_dsp_domain,
 205         .disable        = &omap1_clk_disable_dsp_domain,
 206 };
 207
 208 static int omap1_clk_enable_uart_functional(struct clk *clk)
 209 {
 210         int ret;
 211         struct uart_clk *uclk;
 212
 213         ret = omap1_clk_enable_generic(clk);
 214         if (ret == 0) {
 215                 /* Set smart idle acknowledgement mode */
 216                 uclk = (struct uart_clk *)clk;
 217                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 218                             uclk->sysc_addr);
 219         }
 220
 221         return ret;
 222 }
 223
 224 static void omap1_clk_disable_uart_functional(struct clk *clk)
 225 {
 226         struct uart_clk *uclk;
 227
 228         /* Set force idle acknowledgement mode */
 229         uclk = (struct uart_clk *)clk;
 230         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 231
 232         omap1_clk_disable_generic(clk);
 233 }
 234
 235 static const struct clkops clkops_uart = {
 236         .enable         = &omap1_clk_enable_uart_functional,
 237         .disable        = &omap1_clk_disable_uart_functional,
 238 };
 239
 240 static void omap1_clk_allow_idle(struct clk *clk)
 241 {
 242         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 243
 244         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 245                 return;
 246
 247         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 248                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 249 }
 250
 251 static void omap1_clk_deny_idle(struct clk *clk)
 252 {
 253         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 254
 255         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 256                 return;
 257
 258         if (iclk->no_idle_count++ == 0)
 259                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 260 }
 261
 262 static __u16 verify_ckctl_value(__u16 newval)
 263 {
 264         /* This function checks for following limitations set
 265          * by the hardware (all conditions must be true):
 266          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 267          * ARM_CK >= TC_CK
 268          * DSP_CK >= TC_CK
 269          * DSPMMU_CK >= TC_CK
 270          *
 271          * In addition following rules are enforced:
 272          * LCD_CK <= TC_CK
 273          * ARMPER_CK <= TC_CK
 274          *
 275          * However, maximum frequencies are not checked for!
 276          */
 277         __u8 per_exp;
 278         __u8 lcd_exp;
 279         __u8 arm_exp;
 280         __u8 dsp_exp;
 281         __u8 tc_exp;
 282         __u8 dspmmu_exp;
 283
 284         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 285         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 286         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 287         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 288         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 289         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 290
 291         if (dspmmu_exp < dsp_exp)
 292                 dspmmu_exp = dsp_exp;
 293         if (dspmmu_exp > dsp_exp+1)
 294                 dspmmu_exp = dsp_exp+1;
 295         if (tc_exp < arm_exp)
 296                 tc_exp = arm_exp;
 297         if (tc_exp < dspmmu_exp)
 298                 tc_exp = dspmmu_exp;
 299         if (tc_exp > lcd_exp)
 300                 lcd_exp = tc_exp;
 301         if (tc_exp > per_exp)
 302                 per_exp = tc_exp;
 303
 304         newval &= 0xf000;
 305         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 306         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 307         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 308         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 309         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 310         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 311
 312         return newval;
 313 }
 314
 315 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 316 {
 317         /* Note: If target frequency is too low, this function will return 4,
 318          * which is invalid value. Caller must check for this value and act
 319          * accordingly.
 320          *
 321          * Note: This function does not check for following limitations set
 322          * by the hardware (all conditions must be true):
 323          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 324          * ARM_CK >= TC_CK
 325          * DSP_CK >= TC_CK
 326          * DSPMMU_CK >= TC_CK
 327          */
 328         unsigned long realrate;
 329         struct clk * parent;
 330         unsigned  dsor_exp;
 331
 332         parent = clk->parent;
 333         if (unlikely(parent == NULL))
 334                 return -EIO;
 335
 336         realrate = parent->rate;
 337         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 338                 if (realrate <= rate)
 339                         break;
 340
 341                 realrate /= 2;
 342         }
 343
 344         return dsor_exp;
 345 }
 346
 347 static unsigned long omap1_ckctl_recalc(struct clk *clk)
 348 {
 349         /* Calculate divisor encoded as 2-bit exponent */
 350         int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 351
 352         return clk->parent->rate / dsor;
 353 }
 354
 355 static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
 356 {
 357         int dsor;
 358
 359         /* Calculate divisor encoded as 2-bit exponent
 360          *
 361          * The clock control bits are in DSP domain,
 362          * so api_ck is needed for access.
 363          * Note that DSP_CKCTL virt addr = phys addr, so
 364          * we must use __raw_readw() instead of omap_readw().
 365          */
 366         omap1_clk_enable(&api_ck.clk);
 367         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 368         omap1_clk_disable(&api_ck.clk);
 369
 370         return clk->parent->rate / dsor;
 371 }
 372
 373 /* MPU virtual clock functions */
 374 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 375 {
 376         /* Find the highest supported frequency <= rate and switch to it */
 377         struct mpu_rate * ptr;
 378
 379         for (ptr = rate_table; ptr->rate; ptr++) {
 380                 if (ptr->xtal != ck_ref.rate)
 381                         continue;
 382
 383                 /* DPLL1 cannot be reprogrammed without risking system crash */
 384                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 385                         continue;
 386
 387                 /* Can check only after xtal frequency check */
 388                 if (ptr->rate <= rate)
 389                         break;
 390         }
 391
 392         if (!ptr->rate)
 393                 return -EINVAL;
 394
 395         /*
 396          * In most cases we should not need to reprogram DPLL.
 397          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 398          * (on 730, bit 13 must always be 1)
 399          */
 400         if (cpu_is_omap7xx())
 401                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 402         else
 403                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 404
 405         ck_dpll1.rate = ptr->pll_rate;
 406         return 0;
 407 }
 408
 409 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 410 {
 411         int dsor_exp;
 412         u16 regval;
 413
 414         dsor_exp = calc_dsor_exp(clk, rate);
 415         if (dsor_exp > 3)
 416                 dsor_exp = -EINVAL;
 417         if (dsor_exp < 0)
 418                 return dsor_exp;
 419
 420         regval = __raw_readw(DSP_CKCTL);
 421         regval &= ~(3 << clk->rate_offset);
 422         regval |= dsor_exp << clk->rate_offset;
 423         __raw_writew(regval, DSP_CKCTL);
 424         clk->rate = clk->parent->rate / (1 << dsor_exp);
 425
 426         return 0;
 427 }
 428
 429 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 430 {
 431         int dsor_exp = calc_dsor_exp(clk, rate);
 432         if (dsor_exp < 0)
 433                 return dsor_exp;
 434         if (dsor_exp > 3)
 435                 dsor_exp = 3;
 436         return clk->parent->rate / (1 << dsor_exp);
 437 }
 438
 439 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 440 {
 441         int dsor_exp;
 442         u16 regval;
 443
 444         dsor_exp = calc_dsor_exp(clk, rate);
 445         if (dsor_exp > 3)
 446                 dsor_exp = -EINVAL;
 447         if (dsor_exp < 0)
 448                 return dsor_exp;
 449
 450         regval = omap_readw(ARM_CKCTL);
 451         regval &= ~(3 << clk->rate_offset);
 452         regval |= dsor_exp << clk->rate_offset;
 453         regval = verify_ckctl_value(regval);
 454         omap_writew(regval, ARM_CKCTL);
 455         clk->rate = clk->parent->rate / (1 << dsor_exp);
 456         return 0;
 457 }
 458
 459 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 460 {
 461         /* Find the highest supported frequency <= rate */
 462         struct mpu_rate * ptr;
 463         long  highest_rate;
 464
 465         highest_rate = -EINVAL;
 466
 467         for (ptr = rate_table; ptr->rate; ptr++) {
 468                 if (ptr->xtal != ck_ref.rate)
 469                         continue;
 470
 471                 highest_rate = ptr->rate;
 472
 473                 /* Can check only after xtal frequency check */
 474                 if (ptr->rate <= rate)
 475                         break;
 476         }
 477
 478         return highest_rate;
 479 }
 480
 481 static unsigned calc_ext_dsor(unsigned long rate)
 482 {
 483         unsigned dsor;
 484
 485         /* MCLK and BCLK divisor selection is not linear:
 486          * freq = 96MHz / dsor
 487          *
 488          * RATIO_SEL range: dsor <-> RATIO_SEL
 489          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 490          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 491          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 492          * can not be used.
 493          */
 494         for (dsor = 2; dsor < 96; ++dsor) {
 495                 if ((dsor & 1) && dsor > 8)
 496                         continue;
 497                 if (rate >= 96000000 / dsor)
 498                         break;
 499         }
 500         return dsor;
 501 }
 502
 503 /* Only needed on 1510 */
 504 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 505 {
 506         unsigned int val;
 507
 508         val = __raw_readl(clk->enable_reg);
 509         if (rate == 12000000)
 510                 val &= ~(1 << clk->enable_bit);
 511         else if (rate == 48000000)
 512                 val |= (1 << clk->enable_bit);
 513         else
 514                 return -EINVAL;
 515         __raw_writel(val, clk->enable_reg);
 516         clk->rate = rate;
 517
 518         return 0;
 519 }
 520
 521 /* External clock (MCLK & BCLK) functions */
 522 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 523 {
 524         unsigned dsor;
 525         __u16 ratio_bits;
 526
 527         dsor = calc_ext_dsor(rate);
 528         clk->rate = 96000000 / dsor;
 529         if (dsor > 8)
 530                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 531         else
 532                 ratio_bits = (dsor - 2) << 2;
 533
 534         ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
 535         __raw_writew(ratio_bits, clk->enable_reg);
 536
 537         return 0;
 538 }
 539
 540 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 541 {
 542         u32 l;
 543         int div;
 544         unsigned long p_rate;
 545
 546         p_rate = clk->parent->rate;
 547         /* Round towards slower frequency */
 548         div = (p_rate + rate - 1) / rate;
 549         div--;
 550         if (div < 0 || div > 7)
 551                 return -EINVAL;
 552
 553         l = omap_readl(MOD_CONF_CTRL_1);
 554         l &= ~(7 << 17);
 555         l |= div << 17;
 556         omap_writel(l, MOD_CONF_CTRL_1);
 557
 558         clk->rate = p_rate / (div + 1);
 559
 560         return 0;
 561 }
 562
 563 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 564 {
 565         return 96000000 / calc_ext_dsor(rate);
 566 }
 567
 568 static void omap1_init_ext_clk(struct clk * clk)
 569 {
 570         unsigned dsor;
 571         __u16 ratio_bits;
 572
 573         /* Determine current rate and ensure clock is based on 96MHz APLL */
 574         ratio_bits = __raw_readw(clk->enable_reg) & ~1;
 575         __raw_writew(ratio_bits, clk->enable_reg);
 576
 577         ratio_bits = (ratio_bits & 0xfc) >> 2;
 578         if (ratio_bits > 6)
 579                 dsor = (ratio_bits - 6) * 2 + 8;
 580         else
 581                 dsor = ratio_bits + 2;
 582
 583         clk-> rate = 96000000 / dsor;
 584 }
 585
 586 static int omap1_clk_enable(struct clk *clk)
 587 {
 588         int ret = 0;
 589
 590         if (clk->usecount++ == 0) {
 591                 if (clk->parent) {
 592                         ret = omap1_clk_enable(clk->parent);
 593                         if (ret)
 594                                 goto err;
 595
 596                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 597                                 omap1_clk_deny_idle(clk->parent);
 598                 }
 599
 600                 ret = clk->ops->enable(clk);
 601                 if (ret) {
 602                         if (clk->parent)
 603                                 omap1_clk_disable(clk->parent);
 604                         goto err;
 605                 }
 606         }
 607         return ret;
 608
 609 err:
 610         clk->usecount--;
 611         return ret;
 612 }
 613
 614 static void omap1_clk_disable(struct clk *clk)
 615 {
 616         if (clk->usecount > 0 && !(--clk->usecount)) {
 617                 clk->ops->disable(clk);
 618                 if (likely(clk->parent)) {
 619                         omap1_clk_disable(clk->parent);
 620                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 621                                 omap1_clk_allow_idle(clk->parent);
 622                 }
 623         }
 624 }
 625
 626 static int omap1_clk_enable_generic(struct clk *clk)
 627 {
 628         __u16 regval16;
 629         __u32 regval32;
 630
 631         if (unlikely(clk->enable_reg == NULL)) {
 632                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 633                        clk->name);
 634                 return -EINVAL;
 635         }
 636
 637         if (clk->flags & ENABLE_REG_32BIT) {
 638                 regval32 = __raw_readl(clk->enable_reg);
 639                 regval32 |= (1 << clk->enable_bit);
 640                 __raw_writel(regval32, clk->enable_reg);
 641         } else {
 642                 regval16 = __raw_readw(clk->enable_reg);
 643                 regval16 |= (1 << clk->enable_bit);
 644                 __raw_writew(regval16, clk->enable_reg);
 645         }
 646
 647         return 0;
 648 }
 649
 650 static void omap1_clk_disable_generic(struct clk *clk)
 651 {
 652         __u16 regval16;
 653         __u32 regval32;
 654
 655         if (clk->enable_reg == NULL)
 656                 return;
 657
 658         if (clk->flags & ENABLE_REG_32BIT) {
 659                 regval32 = __raw_readl(clk->enable_reg);
 660                 regval32 &= ~(1 << clk->enable_bit);
 661                 __raw_writel(regval32, clk->enable_reg);
 662         } else {
 663                 regval16 = __raw_readw(clk->enable_reg);
 664                 regval16 &= ~(1 << clk->enable_bit);
 665                 __raw_writew(regval16, clk->enable_reg);
 666         }
 667 }
 668
 669 static const struct clkops clkops_generic = {
 670         .enable         = &omap1_clk_enable_generic,
 671         .disable        = &omap1_clk_disable_generic,
 672 };
 673
 674 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 675 {
 676         if (clk->flags & RATE_FIXED)
 677                 return clk->rate;
 678
 679         if (clk->round_rate != NULL)
 680                 return clk->round_rate(clk, rate);
 681
 682         return clk->rate;
 683 }
 684
 685 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 686 {
 687         int  ret = -EINVAL;
 688
 689         if (clk->set_rate)
 690                 ret = clk->set_rate(clk, rate);
 691         return ret;
 692 }
 693
 694 /*-------------------------------------------------------------------------
 695  * Omap1 clock reset and init functions
 696  *-------------------------------------------------------------------------*/
 697
 698 #ifdef CONFIG_OMAP_RESET_CLOCKS
 699
 700 static void __init omap1_clk_disable_unused(struct clk *clk)
 701 {
 702         __u32 regval32;
 703
 704         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 705          * has not enabled any DSP clocks */
 706         if (clk->enable_reg == DSP_IDLECT2) {
 707                 printk(KERN_INFO "Skipping reset check for DSP domain "
 708                        "clock \"%s\"\n", clk->name);
 709                 return;
 710         }
 711
 712         /* Is the clock already disabled? */
 713         if (clk->flags & ENABLE_REG_32BIT)
 714                 regval32 = __raw_readl(clk->enable_reg);
 715         else
 716                 regval32 = __raw_readw(clk->enable_reg);
 717
 718         if ((regval32 & (1 << clk->enable_bit)) == 0)
 719                 return;
 720
 721         /* FIXME: This clock seems to be necessary but no-one
 722          * has asked for its activation. */
 723         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 724             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 725             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 726                 ) {
 727                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 728                        clk->name);
 729                 return;
 730         }
 731
 732         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 733         clk->ops->disable(clk);
 734         printk(" done\n");
 735 }
 736
 737 #else
 738 #define omap1_clk_disable_unused        NULL
 739 #endif
 740
 741 static struct clk_functions omap1_clk_functions = {
 742         .clk_enable             = omap1_clk_enable,
 743         .clk_disable            = omap1_clk_disable,
 744         .clk_round_rate         = omap1_clk_round_rate,
 745         .clk_set_rate           = omap1_clk_set_rate,
 746         .clk_disable_unused     = omap1_clk_disable_unused,
 747 };
 748
 749 int __init omap1_clk_init(void)
 750 {
 751         struct omap_clk *c;
 752         const struct omap_clock_config *info;
 753         int crystal_type = 0; /* Default 12 MHz */
 754         u32 reg, cpu_mask;
 755
 756 #ifdef CONFIG_DEBUG_LL
 757         /* Resets some clocks that may be left on from bootloader,
 758          * but leaves serial clocks on.
 759          */
 760         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 761 #endif
 762
 763         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 764         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 765         omap_writew(reg, SOFT_REQ_REG);
 766         if (!cpu_is_omap15xx())
 767                 omap_writew(0, SOFT_REQ_REG2);
 768
 769         clk_init(&omap1_clk_functions);
 770
 771         /* By default all idlect1 clocks are allowed to idle */
 772         arm_idlect1_mask = ~0;
 773
 774         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 775                 clk_preinit(c->lk.clk);
 776
 777         cpu_mask = 0;
 778         if (cpu_is_omap16xx())
 779                 cpu_mask |= CK_16XX;
 780         if (cpu_is_omap1510())
 781                 cpu_mask |= CK_1510;
 782         if (cpu_is_omap7xx())
 783                 cpu_mask |= CK_7XX;
 784         if (cpu_is_omap310())
 785                 cpu_mask |= CK_310;
 786
 787         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 788                 if (c->cpu & cpu_mask) {
 789                         clkdev_add(&c->lk);
 790                         clk_register(c->lk.clk);
 791                 }
 792
 793         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 794         if (info != NULL) {
 795                 if (!cpu_is_omap15xx())
 796                         crystal_type = info->system_clock_type;
 797         }
 798
 799 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 800         ck_ref.rate = 13000000;
 801 #elif defined(CONFIG_ARCH_OMAP16XX)
 802         if (crystal_type == 2)
 803                 ck_ref.rate = 19200000;
 804 #endif
 805
 806         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 807                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 808                omap_readw(ARM_CKCTL));
 809
 810         /* We want to be in syncronous scalable mode */
 811         omap_writew(0x1000, ARM_SYSST);
 812
 813 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 814         /* Use values set by bootloader. Determine PLL rate and recalculate
 815          * dependent clocks as if kernel had changed PLL or divisors.
 816          */
 817         {
 818                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 819
 820                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 821                 if (pll_ctl_val & 0x10) {
 822                         /* PLL enabled, apply multiplier and divisor */
 823                         if (pll_ctl_val & 0xf80)
 824                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 825                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 826                 } else {
 827                         /* PLL disabled, apply bypass divisor */
 828                         switch (pll_ctl_val & 0xc) {
 829                         case 0:
 830                                 break;
 831                         case 0x4:
 832                                 ck_dpll1.rate /= 2;
 833                                 break;
 834                         default:
 835                                 ck_dpll1.rate /= 4;
 836                                 break;
 837                         }
 838                 }
 839         }
 840 #else
 841         /* Find the highest supported frequency and enable it */
 842         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 843                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 844                 /* Guess sane values (60MHz) */
 845                 omap_writew(0x2290, DPLL_CTL);
 846                 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
 847                 ck_dpll1.rate = 60000000;
 848         }
 849 #endif
 850         propagate_rate(&ck_dpll1);
 851         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 852         propagate_rate(&ck_ref);
 853         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 854                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 855                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 856                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 857                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 858
 859 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 860         /* Select slicer output as OMAP input clock */
 861         omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
 862 #endif
 863
 864         /* Amstrad Delta wants BCLK high when inactive */
 865         if (machine_is_ams_delta())
 866                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 867                                 (1 << SDW_MCLK_INV_BIT),
 868                                 ULPD_CLOCK_CTRL);
 869
 870         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 871         /* (on 730, bit 13 must not be cleared) */
 872         if (cpu_is_omap7xx())
 873                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 874         else
 875                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 876
 877         /* Put DSP/MPUI into reset until needed */
 878         omap_writew(0, ARM_RSTCT1);
 879         omap_writew(1, ARM_RSTCT2);
 880         omap_writew(0x400, ARM_IDLECT1);
 881
 882         /*
 883          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 884          * of the ARM_IDLECT2 register must be set to zero. The power-on
 885          * default value of this bit is one.
 886          */
 887         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 888
 889         /*
 890          * Only enable those clocks we will need, let the drivers
 891          * enable other clocks as necessary
 892          */
 893         clk_enable(&armper_ck.clk);
 894         clk_enable(&armxor_ck.clk);
 895         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 896
 897         if (cpu_is_omap15xx())
 898                 clk_enable(&arm_gpio_ck);
 899
 900         return 0;
 901 }