2 * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
4 * Copyright (C) 2012 Marvell
6 * Yehuda Yitschak <yehuday@marvell.com>
7 * Gregory Clement <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * The Armada 370 and Armada XP SOCs have a power management service
15 * unit which is responsible for powering down and waking up CPUs and
19 #define pr_fmt(fmt) "mvebu-pmsu: " fmt
21 #include <linux/clk.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/delay.h>
24 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/mbus.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/platform_device.h>
31 #include <linux/resource.h>
32 #include <linux/slab.h>
33 #include <linux/smp.h>
34 #include <asm/cacheflush.h>
36 #include <asm/smp_scu.h>
37 #include <asm/smp_plat.h>
38 #include <asm/suspend.h>
39 #include <asm/tlbflush.h>
43 #define PMSU_BASE_OFFSET 0x100
44 #define PMSU_REG_SIZE 0x1000
46 /* PMSU MP registers */
47 #define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
48 #define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18)
49 #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16)
50 #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20)
52 #define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
54 #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0)
56 #define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
57 #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16)
58 #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17)
59 #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20)
60 #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21)
61 #define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22)
62 #define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
63 #define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
65 #define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
66 #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1)
67 #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17)
69 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
71 /* PMSU fabric registers */
72 #define L2C_NFABRIC_PM_CTL 0x4
73 #define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
75 /* PMSU delay registers */
76 #define PMSU_POWERDOWN_DELAY 0xF04
77 #define PMSU_POWERDOWN_DELAY_PMU BIT(1)
78 #define PMSU_POWERDOWN_DELAY_MASK 0xFFFE
79 #define PMSU_DFLT_ARMADA38X_DELAY 0x64
81 /* CA9 MPcore SoC Control registers */
83 #define MPCORE_RESET_CTL 0x64
84 #define MPCORE_RESET_CTL_L2 BIT(0)
85 #define MPCORE_RESET_CTL_DEBUG BIT(16)
87 #define SRAM_PHYS_BASE 0xFFFF0000
88 #define BOOTROM_BASE 0xFFF00000
89 #define BOOTROM_SIZE 0x100000
91 #define ARMADA_370_CRYPT0_ENG_TARGET 0x9
92 #define ARMADA_370_CRYPT0_ENG_ATTR 0x1
94 extern void ll_disable_coherency(void);
95 extern void ll_enable_coherency(void);
97 extern void armada_370_xp_cpu_resume(void);
98 extern void armada_38x_cpu_resume(void);
100 static phys_addr_t pmsu_mp_phys_base;
101 static void __iomem *pmsu_mp_base;
103 static void *mvebu_cpu_resume;
105 static const struct of_device_id of_pmsu_table[] = {
106 { .compatible = "marvell,armada-370-pmsu", },
107 { .compatible = "marvell,armada-370-xp-pmsu", },
108 { .compatible = "marvell,armada-380-pmsu", },
109 { /* end of list */ },
112 void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
114 writel(virt_to_phys(boot_addr), pmsu_mp_base +
115 PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
118 extern unsigned char mvebu_boot_wa_start;
119 extern unsigned char mvebu_boot_wa_end;
122 * This function sets up the boot address workaround needed for SMP
123 * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
124 * BootROM Mbus window, and instead remaps a crypto SRAM into which a
125 * custom piece of code is copied to replace the problematic BootROM.
127 int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
128 unsigned int crypto_eng_attribute,
129 phys_addr_t resume_addr_reg)
131 void __iomem *sram_virt_base;
132 u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;
134 mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
135 mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
136 SRAM_PHYS_BASE, SZ_64K);
138 sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
139 if (!sram_virt_base) {
140 pr_err("Unable to map SRAM to setup the boot address WA\n");
144 memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
147 * The last word of the code copied in SRAM must contain the
148 * physical base address of the PMSU register. We
149 * intentionally store this address in the native endianness
152 __raw_writel((unsigned long)resume_addr_reg,
153 sram_virt_base + code_len - 4);
155 iounmap(sram_virt_base);
160 static int __init mvebu_v7_pmsu_init(void)
162 struct device_node *np;
166 np = of_find_matching_node(NULL, of_pmsu_table);
170 pr_info("Initializing Power Management Service Unit\n");
172 if (of_address_to_resource(np, 0, &res)) {
173 pr_err("unable to get resource\n");
178 if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
179 pr_warn(FW_WARN "deprecated pmsu binding\n");
180 res.start = res.start - PMSU_BASE_OFFSET;
181 res.end = res.start + PMSU_REG_SIZE - 1;
184 if (!request_mem_region(res.start, resource_size(&res),
186 pr_err("unable to request region\n");
191 pmsu_mp_phys_base = res.start;
193 pmsu_mp_base = ioremap(res.start, resource_size(&res));
195 pr_err("unable to map registers\n");
196 release_mem_region(res.start, resource_size(&res));
206 static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
210 if (pmsu_mp_base == NULL)
213 /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
214 reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
215 reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
216 writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
219 enum pmsu_idle_prepare_flags {
220 PMSU_PREPARE_NORMAL = 0,
221 PMSU_PREPARE_DEEP_IDLE = BIT(0),
222 PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
225 /* No locking is needed because we only access per-CPU registers */
226 static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
228 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
231 if (pmsu_mp_base == NULL)
235 * Adjust the PMSU configuration to wait for WFI signal, enable
236 * IRQ and FIQ as wakeup events, set wait for snoop queue empty
237 * indication and mask IRQ and FIQ from CPU
239 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
240 reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
241 PMSU_STATUS_AND_MASK_IRQ_WAKEUP |
242 PMSU_STATUS_AND_MASK_FIQ_WAKEUP |
243 PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
244 PMSU_STATUS_AND_MASK_IRQ_MASK |
245 PMSU_STATUS_AND_MASK_FIQ_MASK;
246 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
248 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
249 /* ask HW to power down the L2 Cache if needed */
250 if (flags & PMSU_PREPARE_DEEP_IDLE)
251 reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
253 /* request power down */
254 reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
255 writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
257 if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
258 /* Disable snoop disable by HW - SW is taking care of it */
259 reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
260 reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
261 writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
267 int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
269 unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
273 flags |= PMSU_PREPARE_DEEP_IDLE;
275 ret = mvebu_v7_pmsu_idle_prepare(flags);
279 v7_exit_coherency_flush(all);
281 ll_disable_coherency();
287 /* If we are here, wfi failed. As processors run out of
288 * coherency for some time, tlbs might be stale, so flush them
290 local_flush_tlb_all();
292 ll_enable_coherency();
294 /* Test the CR_C bit and set it if it was cleared */
296 "mrc p15, 0, r0, c1, c0, 0 \n\t"
298 "orreq r0, r0, #(1 << 2) \n\t"
299 "mcreq p15, 0, r0, c1, c0, 0 \n\t"
301 : : "Ir" (CR_C) : "r0");
303 pr_debug("Failed to suspend the system\n");
308 static int armada_370_xp_cpu_suspend(unsigned long deepidle)
310 return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
313 int armada_38x_do_cpu_suspend(unsigned long deepidle)
315 unsigned long flags = 0;
318 flags |= PMSU_PREPARE_DEEP_IDLE;
320 mvebu_v7_pmsu_idle_prepare(flags);
322 * Already flushed cache, but do it again as the outer cache
323 * functions dirty the cache with spinlocks
325 v7_exit_coherency_flush(louis);
327 scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
334 static int armada_38x_cpu_suspend(unsigned long deepidle)
336 return cpu_suspend(false, armada_38x_do_cpu_suspend);
339 /* No locking is needed because we only access per-CPU registers */
340 void mvebu_v7_pmsu_idle_exit(void)
342 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
345 if (pmsu_mp_base == NULL)
347 /* cancel ask HW to power down the L2 Cache if possible */
348 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
349 reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
350 writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
352 /* cancel Enable wakeup events and mask interrupts */
353 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
354 reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
355 reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
356 reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
357 reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
358 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
361 static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
362 unsigned long action, void *hcpu)
364 if (action == CPU_PM_ENTER) {
365 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
366 mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
367 } else if (action == CPU_PM_EXIT) {
368 mvebu_v7_pmsu_idle_exit();
374 static struct notifier_block mvebu_v7_cpu_pm_notifier = {
375 .notifier_call = mvebu_v7_cpu_pm_notify,
378 static struct platform_device mvebu_v7_cpuidle_device;
380 static int broken_idle(struct device_node *np)
382 if (of_property_read_bool(np, "broken-idle")) {
383 pr_warn("CPU idle is currently broken: disabling\n");
390 static __init int armada_370_cpuidle_init(void)
392 struct device_node *np;
393 phys_addr_t redirect_reg;
395 np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
403 * On Armada 370, there is "a slow exit process from the deep
404 * idle state due to heavy L1/L2 cache cleanup operations
405 * performed by the BootROM software". To avoid this, we
406 * replace the restart code of the bootrom by a a simple jump
407 * to the boot address. Then the code located at this boot
408 * address will take care of the initialization.
410 redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
411 mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
412 ARMADA_370_CRYPT0_ENG_ATTR,
415 mvebu_cpu_resume = armada_370_xp_cpu_resume;
416 mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
417 mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
424 static __init int armada_38x_cpuidle_init(void)
426 struct device_node *np;
427 void __iomem *mpsoc_base;
430 pr_warn("CPU idle is currently broken on Armada 38x: disabling\n");
433 np = of_find_compatible_node(NULL, NULL,
434 "marvell,armada-380-coherency-fabric");
443 np = of_find_compatible_node(NULL, NULL,
444 "marvell,armada-380-mpcore-soc-ctrl");
447 mpsoc_base = of_iomap(np, 0);
450 /* Set up reset mask when powering down the cpus */
451 reg = readl(mpsoc_base + MPCORE_RESET_CTL);
452 reg |= MPCORE_RESET_CTL_L2;
453 reg |= MPCORE_RESET_CTL_DEBUG;
454 writel(reg, mpsoc_base + MPCORE_RESET_CTL);
458 reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
459 reg &= ~PMSU_POWERDOWN_DELAY_MASK;
460 reg |= PMSU_DFLT_ARMADA38X_DELAY;
461 reg |= PMSU_POWERDOWN_DELAY_PMU;
462 writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
464 mvebu_cpu_resume = armada_38x_cpu_resume;
465 mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
466 mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
473 static __init int armada_xp_cpuidle_init(void)
475 struct device_node *np;
477 np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
484 mvebu_cpu_resume = armada_370_xp_cpu_resume;
485 mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
486 mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
493 static int __init mvebu_v7_cpu_pm_init(void)
495 struct device_node *np;
498 np = of_find_matching_node(NULL, of_pmsu_table);
504 * Currently the CPU idle support for Armada 38x is broken, as
505 * the CPU hotplug uses some of the CPU idle functions it is
506 * broken too, so let's disable it
508 if (of_machine_is_compatible("marvell,armada380")) {
509 cpu_hotplug_disable();
510 pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n");
513 if (of_machine_is_compatible("marvell,armadaxp"))
514 ret = armada_xp_cpuidle_init();
515 else if (of_machine_is_compatible("marvell,armada370"))
516 ret = armada_370_cpuidle_init();
517 else if (of_machine_is_compatible("marvell,armada380"))
518 ret = armada_38x_cpuidle_init();
525 mvebu_v7_pmsu_enable_l2_powerdown_onidle();
526 if (mvebu_v7_cpuidle_device.name)
527 platform_device_register(&mvebu_v7_cpuidle_device);
528 cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
533 arch_initcall(mvebu_v7_cpu_pm_init);
534 early_initcall(mvebu_v7_pmsu_init);
536 static void mvebu_pmsu_dfs_request_local(void *data)
539 u32 cpu = smp_processor_id();
542 local_irq_save(flags);
544 /* Prepare to enter idle */
545 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
546 reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
547 PMSU_STATUS_AND_MASK_IRQ_MASK |
548 PMSU_STATUS_AND_MASK_FIQ_MASK;
549 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
551 /* Request the DFS transition */
552 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
553 reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
554 writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
556 /* The fact of entering idle will trigger the DFS transition */
560 * We're back from idle, the DFS transition has completed,
561 * clear the idle wait indication.
563 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
564 reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
565 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
567 local_irq_restore(flags);
570 int mvebu_pmsu_dfs_request(int cpu)
572 unsigned long timeout;
573 int hwcpu = cpu_logical_map(cpu);
576 /* Clear any previous DFS DONE event */
577 reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
578 reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
579 writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
581 /* Mask the DFS done interrupt, since we are going to poll */
582 reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
583 reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
584 writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
586 /* Trigger the DFS on the appropriate CPU */
587 smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
590 /* Poll until the DFS done event is generated */
591 timeout = jiffies + HZ;
592 while (time_before(jiffies, timeout)) {
593 reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
594 if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
599 if (time_after(jiffies, timeout))
602 /* Restore the DFS mask to its original state */
603 reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
604 reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
605 writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));