2 * arch/arm/mach-ixp4xx/common-pci.c
4 * IXP4XX PCI routines for all platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright (C) 2002 Intel Corporation.
9 * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
29 #include <asm/dma-mapping.h>
31 #include <asm/cputype.h>
33 #include <asm/sizes.h>
34 #include <asm/system.h>
35 #include <asm/mach/pci.h>
36 #include <mach/hardware.h>
40 * IXP4xx PCI read function is dependent on whether we are
41 * running A0 or B0 (AppleGate) silicon.
43 int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
46 * Base address for PCI regsiter region
48 unsigned long ixp4xx_pci_reg_base = 0;
51 * PCI cfg an I/O routines are done by programming a
52 * command/byte enable register, and then read/writing
53 * the data from a data regsiter. We need to ensure
54 * these transactions are atomic or we will end up
55 * with corrupt data on the bus or in a driver.
57 static DEFINE_SPINLOCK(ixp4xx_pci_lock);
60 * Read from PCI config space
62 static void crp_read(u32 ad_cbe, u32 *data)
65 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
66 *PCI_CRP_AD_CBE = ad_cbe;
67 *data = *PCI_CRP_RDATA;
68 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
72 * Write to PCI config space
74 static void crp_write(u32 ad_cbe, u32 data)
77 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
78 *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
79 *PCI_CRP_WDATA = data;
80 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
83 static inline int check_master_abort(void)
85 /* check Master Abort bit after access */
86 unsigned long isr = *PCI_ISR;
88 if (isr & PCI_ISR_PFE) {
89 /* make sure the Master Abort bit is reset */
90 *PCI_ISR = PCI_ISR_PFE;
91 pr_debug("%s failed\n", __func__);
98 int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
104 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
109 * PCI workaround - only works if NP PCI space reads have
110 * no side effects!!! Read 8 times. last one will be good.
112 for (i = 0; i < 8; i++) {
114 *data = *PCI_NP_RDATA;
115 *data = *PCI_NP_RDATA;
118 if(check_master_abort())
121 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
125 int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
130 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
134 /* set up and execute the read */
137 /* the result of the read is now in NP_RDATA */
138 *data = *PCI_NP_RDATA;
140 if(check_master_abort())
143 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
147 int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
152 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
156 /* set up the write */
159 /* execute the write by writing to NP_WDATA */
160 *PCI_NP_WDATA = data;
162 if(check_master_abort())
165 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
169 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
174 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
178 addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
179 ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
185 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
186 * 0 and 3 are not valid indexes...
188 static u32 bytemask[] = {
196 static u32 local_byte_lane_enable_bits(u32 n, int size)
199 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
201 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
207 static int local_read_config(int where, int size, u32 *value)
210 pr_debug("local_read_config from %d size %d\n", where, size);
212 crp_read(where & ~3, &data);
213 *value = (data >> (8*n)) & bytemask[size];
214 pr_debug("local_read_config read %#x\n", *value);
215 return PCIBIOS_SUCCESSFUL;
218 static int local_write_config(int where, int size, u32 value)
220 u32 n, byte_enables, data;
221 pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
223 byte_enables = local_byte_lane_enable_bits(n, size);
224 if (byte_enables == 0xffffffff)
225 return PCIBIOS_BAD_REGISTER_NUMBER;
226 data = value << (8*n);
227 crp_write((where & ~3) | byte_enables, data);
228 return PCIBIOS_SUCCESSFUL;
231 static u32 byte_lane_enable_bits(u32 n, int size)
234 return (0xf & ~BIT(n)) << 4;
236 return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
242 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
244 u32 n, byte_enables, addr, data;
245 u8 bus_num = bus->number;
247 pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
248 bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
252 byte_enables = byte_lane_enable_bits(n, size);
253 if (byte_enables == 0xffffffff)
254 return PCIBIOS_BAD_REGISTER_NUMBER;
256 addr = ixp4xx_config_addr(bus_num, devfn, where);
257 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
258 return PCIBIOS_DEVICE_NOT_FOUND;
260 *value = (data >> (8*n)) & bytemask[size];
261 pr_debug("read_config_byte read %#x\n", *value);
262 return PCIBIOS_SUCCESSFUL;
265 static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
267 u32 n, byte_enables, addr, data;
268 u8 bus_num = bus->number;
270 pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
271 size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
274 byte_enables = byte_lane_enable_bits(n, size);
275 if (byte_enables == 0xffffffff)
276 return PCIBIOS_BAD_REGISTER_NUMBER;
278 addr = ixp4xx_config_addr(bus_num, devfn, where);
279 data = value << (8*n);
280 if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
281 return PCIBIOS_DEVICE_NOT_FOUND;
283 return PCIBIOS_SUCCESSFUL;
286 struct pci_ops ixp4xx_ops = {
287 .read = ixp4xx_pci_read_config,
288 .write = ixp4xx_pci_write_config,
294 static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
299 local_read_config(PCI_STATUS, 2, &status);
300 pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
301 "status = %#x\n", addr, isr, status);
303 /* make sure the Master Abort bit is reset */
304 *PCI_ISR = PCI_ISR_PFE;
305 status |= PCI_STATUS_REC_MASTER_ABORT;
306 local_write_config(PCI_STATUS, 2, status);
309 * If it was an imprecise abort, then we need to correct the
310 * return address to be _after_ the instruction.
319 static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
321 return dev->bus == &pci_bus_type && (dma_addr + size) >= SZ_64M;
325 * Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
327 static int ixp4xx_pci_platform_notify(struct device *dev)
329 if(dev->bus == &pci_bus_type) {
330 *dev->dma_mask = SZ_64M - 1;
331 dev->coherent_dma_mask = SZ_64M - 1;
332 dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
337 static int ixp4xx_pci_platform_notify_remove(struct device *dev)
339 if(dev->bus == &pci_bus_type) {
340 dmabounce_unregister_dev(dev);
345 void __init ixp4xx_pci_preinit(void)
347 unsigned long cpuid = read_cpuid_id();
350 * Determine which PCI read method to use.
351 * Rev 0 IXP425 requires workaround.
353 if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
354 printk("PCI: IXP42x A0 silicon detected - "
355 "PCI Non-Prefetch Workaround Enabled\n");
356 ixp4xx_pci_read = ixp4xx_pci_read_errata;
358 ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
361 /* hook in our fault handler for PCI errors */
362 hook_fault_code(16+6, abort_handler, SIGBUS, 0,
363 "imprecise external abort");
365 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
368 * We use identity AHB->PCI address translation
369 * in the 0x48000000 to 0x4bffffff address space
371 *PCI_PCIMEMBASE = 0x48494A4B;
374 * We also use identity PCI->AHB address translation
375 * in 4 16MB BARs that begin at the physical memory start
377 *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
378 ((PHYS_OFFSET & 0xFF000000) >> 8) +
379 ((PHYS_OFFSET & 0xFF000000) >> 16) +
380 ((PHYS_OFFSET & 0xFF000000) >> 24) +
383 if (*PCI_CSR & PCI_CSR_HOST) {
384 printk("PCI: IXP4xx is host\n");
386 pr_debug("setup BARs in controller\n");
389 * We configure the PCI inbound memory windows to be
390 * 1:1 mapped to SDRAM
392 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
393 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
394 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
395 local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);
398 * Enable CSR window at 64 MiB to allow PCI masters
399 * to continue prefetching past 64 MiB boundary.
401 local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
404 * Enable the IO window to be way up high, at 0xfffffc00
406 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
408 printk("PCI: IXP4xx is target - No bus scan performed\n");
411 printk("PCI: IXP4xx Using %s access for memory space\n",
412 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
419 pr_debug("clear error bits in ISR\n");
420 *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
423 * Set Initialize Complete in PCI Control Register: allow IXP4XX to
424 * respond to PCI configuration cycles. Specify that the AHB bus is
425 * operating in big endian mode. Set up byte lane swapping between
426 * little-endian PCI and the big-endian AHB bus
429 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
431 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
437 int ixp4xx_setup(int nr, struct pci_sys_data *sys)
439 struct resource *res;
444 res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
447 * If we're out of memory this early, something is wrong,
448 * so we might as well catch it here.
450 panic("PCI: unable to allocate resources?\n");
453 local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
455 res[0].name = "PCI I/O Space";
456 res[0].start = 0x00000000;
457 res[0].end = 0x0000ffff;
458 res[0].flags = IORESOURCE_IO;
460 res[1].name = "PCI Memory Space";
461 res[1].start = PCIBIOS_MIN_MEM;
462 res[1].end = PCIBIOS_MAX_MEM;
463 res[1].flags = IORESOURCE_MEM;
465 request_resource(&ioport_resource, &res[0]);
466 request_resource(&iomem_resource, &res[1]);
468 sys->resource[0] = &res[0];
469 sys->resource[1] = &res[1];
470 sys->resource[2] = NULL;
472 platform_notify = ixp4xx_pci_platform_notify;
473 platform_notify_remove = ixp4xx_pci_platform_notify_remove;
478 struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
480 return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
483 int dma_set_coherent_mask(struct device *dev, u64 mask)
485 if (mask >= SZ_64M - 1)
491 EXPORT_SYMBOL(ixp4xx_pci_read);
492 EXPORT_SYMBOL(ixp4xx_pci_write);
493 EXPORT_SYMBOL(dma_set_coherent_mask);