1 // SPDX-License-Identifier: GPL-2.0-only
3 * iop13xx platform Initialization
4 * Copyright (c) 2005-2006, Intel Corporation.
7 #include <linux/dma-mapping.h>
8 #include <linux/serial_8250.h>
10 #include <linux/reboot.h>
11 #ifdef CONFIG_MTD_PHYSMAP
12 #include <linux/mtd/physmap.h>
14 #include <asm/mach/map.h>
15 #include <mach/hardware.h>
17 #include <asm/hardware/iop_adma.h>
18 #include <mach/irqs.h>
20 #define IOP13XX_UART_XTAL 33334000
21 #define IOP13XX_SETUP_DEBUG 0
22 #define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
24 /* Standard IO mapping for all IOP13XX based systems
26 static struct map_desc iop13xx_std_desc[] __initdata = {
27 { /* mem mapped registers */
28 .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
29 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
30 .length = IOP13XX_PMMR_SIZE,
35 static struct resource iop13xx_uart0_resources[] = {
37 .start = IOP13XX_UART0_PHYS,
38 .end = IOP13XX_UART0_PHYS + 0x3f,
39 .flags = IORESOURCE_MEM,
42 .start = IRQ_IOP13XX_UART0,
43 .end = IRQ_IOP13XX_UART0,
44 .flags = IORESOURCE_IRQ
48 static struct resource iop13xx_uart1_resources[] = {
50 .start = IOP13XX_UART1_PHYS,
51 .end = IOP13XX_UART1_PHYS + 0x3f,
52 .flags = IORESOURCE_MEM,
55 .start = IRQ_IOP13XX_UART1,
56 .end = IRQ_IOP13XX_UART1,
57 .flags = IORESOURCE_IRQ
61 static struct plat_serial8250_port iop13xx_uart0_data[] = {
63 .membase = IOP13XX_UART0_VIRT,
64 .mapbase = IOP13XX_UART0_PHYS,
65 .irq = IRQ_IOP13XX_UART0,
66 .uartclk = IOP13XX_UART_XTAL,
69 .flags = UPF_SKIP_TEST,
74 static struct plat_serial8250_port iop13xx_uart1_data[] = {
76 .membase = IOP13XX_UART1_VIRT,
77 .mapbase = IOP13XX_UART1_PHYS,
78 .irq = IRQ_IOP13XX_UART1,
79 .uartclk = IOP13XX_UART_XTAL,
82 .flags = UPF_SKIP_TEST,
87 /* The ids are fixed up later in iop13xx_platform_init */
88 static struct platform_device iop13xx_uart0 = {
91 .dev.platform_data = iop13xx_uart0_data,
93 .resource = iop13xx_uart0_resources,
96 static struct platform_device iop13xx_uart1 = {
99 .dev.platform_data = iop13xx_uart1_data,
101 .resource = iop13xx_uart1_resources
104 static struct resource iop13xx_i2c_0_resources[] = {
106 .start = IOP13XX_I2C0_PHYS,
107 .end = IOP13XX_I2C0_PHYS + 0x18,
108 .flags = IORESOURCE_MEM,
111 .start = IRQ_IOP13XX_I2C_0,
112 .end = IRQ_IOP13XX_I2C_0,
113 .flags = IORESOURCE_IRQ
117 static struct resource iop13xx_i2c_1_resources[] = {
119 .start = IOP13XX_I2C1_PHYS,
120 .end = IOP13XX_I2C1_PHYS + 0x18,
121 .flags = IORESOURCE_MEM,
124 .start = IRQ_IOP13XX_I2C_1,
125 .end = IRQ_IOP13XX_I2C_1,
126 .flags = IORESOURCE_IRQ
130 static struct resource iop13xx_i2c_2_resources[] = {
132 .start = IOP13XX_I2C2_PHYS,
133 .end = IOP13XX_I2C2_PHYS + 0x18,
134 .flags = IORESOURCE_MEM,
137 .start = IRQ_IOP13XX_I2C_2,
138 .end = IRQ_IOP13XX_I2C_2,
139 .flags = IORESOURCE_IRQ
143 /* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
144 * we just use the same device name.
147 /* The ids are fixed up later in iop13xx_platform_init */
148 static struct platform_device iop13xx_i2c_0_controller = {
149 .name = "IOP3xx-I2C",
152 .resource = iop13xx_i2c_0_resources
155 static struct platform_device iop13xx_i2c_1_controller = {
156 .name = "IOP3xx-I2C",
159 .resource = iop13xx_i2c_1_resources
162 static struct platform_device iop13xx_i2c_2_controller = {
163 .name = "IOP3xx-I2C",
166 .resource = iop13xx_i2c_2_resources
169 #ifdef CONFIG_MTD_PHYSMAP
172 static struct physmap_flash_data iq8134x_flash_data = {
176 static struct resource iq8134x_flash_resource = {
177 .start = IQ81340_FLASHBASE,
179 .flags = IORESOURCE_MEM,
182 static struct platform_device iq8134x_flash = {
183 .name = "physmap-flash",
185 .dev = { .platform_data = &iq8134x_flash_data, },
187 .resource = &iq8134x_flash_resource,
190 static unsigned long iq8134x_probe_flash_size(void)
192 uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
195 unsigned long size = 0;
196 int width = iq8134x_flash_data.width;
199 /* send CFI 'query' command */
200 writew(0x98, flash_addr);
202 /* check for CFI compliance */
203 for (i = 0; i < 3 * width; i += width)
204 query[i / width] = readb(flash_addr + (0x10 * width) + i);
207 if (memcmp(query, "QRY", 3) == 0)
208 size = 1 << readb(flash_addr + (0x27 * width));
210 /* send CFI 'read array' command */
211 writew(0xff, flash_addr);
221 static struct resource iop13xx_adma_0_resources[] = {
223 .start = IOP13XX_ADMA_PHYS_BASE(0),
224 .end = IOP13XX_ADMA_UPPER_PA(0),
225 .flags = IORESOURCE_MEM,
228 .start = IRQ_IOP13XX_ADMA0_EOT,
229 .end = IRQ_IOP13XX_ADMA0_EOT,
230 .flags = IORESOURCE_IRQ
233 .start = IRQ_IOP13XX_ADMA0_EOC,
234 .end = IRQ_IOP13XX_ADMA0_EOC,
235 .flags = IORESOURCE_IRQ
238 .start = IRQ_IOP13XX_ADMA0_ERR,
239 .end = IRQ_IOP13XX_ADMA0_ERR,
240 .flags = IORESOURCE_IRQ
244 static struct resource iop13xx_adma_1_resources[] = {
246 .start = IOP13XX_ADMA_PHYS_BASE(1),
247 .end = IOP13XX_ADMA_UPPER_PA(1),
248 .flags = IORESOURCE_MEM,
251 .start = IRQ_IOP13XX_ADMA1_EOT,
252 .end = IRQ_IOP13XX_ADMA1_EOT,
253 .flags = IORESOURCE_IRQ
256 .start = IRQ_IOP13XX_ADMA1_EOC,
257 .end = IRQ_IOP13XX_ADMA1_EOC,
258 .flags = IORESOURCE_IRQ
261 .start = IRQ_IOP13XX_ADMA1_ERR,
262 .end = IRQ_IOP13XX_ADMA1_ERR,
263 .flags = IORESOURCE_IRQ
267 static struct resource iop13xx_adma_2_resources[] = {
269 .start = IOP13XX_ADMA_PHYS_BASE(2),
270 .end = IOP13XX_ADMA_UPPER_PA(2),
271 .flags = IORESOURCE_MEM,
274 .start = IRQ_IOP13XX_ADMA2_EOT,
275 .end = IRQ_IOP13XX_ADMA2_EOT,
276 .flags = IORESOURCE_IRQ
279 .start = IRQ_IOP13XX_ADMA2_EOC,
280 .end = IRQ_IOP13XX_ADMA2_EOC,
281 .flags = IORESOURCE_IRQ
284 .start = IRQ_IOP13XX_ADMA2_ERR,
285 .end = IRQ_IOP13XX_ADMA2_ERR,
286 .flags = IORESOURCE_IRQ
290 static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(32);
291 static struct iop_adma_platform_data iop13xx_adma_0_data = {
293 .pool_size = PAGE_SIZE,
296 static struct iop_adma_platform_data iop13xx_adma_1_data = {
298 .pool_size = PAGE_SIZE,
301 static struct iop_adma_platform_data iop13xx_adma_2_data = {
303 .pool_size = PAGE_SIZE,
306 /* The ids are fixed up later in iop13xx_platform_init */
307 static struct platform_device iop13xx_adma_0_channel = {
311 .resource = iop13xx_adma_0_resources,
313 .dma_mask = &iop13xx_adma_dmamask,
314 .coherent_dma_mask = DMA_BIT_MASK(32),
315 .platform_data = (void *) &iop13xx_adma_0_data,
319 static struct platform_device iop13xx_adma_1_channel = {
323 .resource = iop13xx_adma_1_resources,
325 .dma_mask = &iop13xx_adma_dmamask,
326 .coherent_dma_mask = DMA_BIT_MASK(32),
327 .platform_data = (void *) &iop13xx_adma_1_data,
331 static struct platform_device iop13xx_adma_2_channel = {
335 .resource = iop13xx_adma_2_resources,
337 .dma_mask = &iop13xx_adma_dmamask,
338 .coherent_dma_mask = DMA_BIT_MASK(32),
339 .platform_data = (void *) &iop13xx_adma_2_data,
343 void __init iop13xx_map_io(void)
345 /* Initialize the Static Page Table maps */
346 iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
349 static int init_uart;
351 static int init_adma;
353 void __init iop13xx_platform_init(void)
356 u32 uart_idx, i2c_idx, adma_idx, plat_idx;
357 struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
359 /* set the bases so we can read the device id */
360 iop13xx_set_atu_mmr_bases();
362 memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
364 if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
365 switch (iop13xx_dev_id()) {
366 /* enable both uarts on iop341 */
371 init_uart |= IOP13XX_INIT_UART_0;
372 init_uart |= IOP13XX_INIT_UART_1;
374 /* only enable uart 1 */
376 init_uart |= IOP13XX_INIT_UART_1;
380 if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
381 switch (iop13xx_dev_id()) {
382 /* enable all i2c units on iop341 and iop342 */
391 init_i2c |= IOP13XX_INIT_I2C_0;
392 init_i2c |= IOP13XX_INIT_I2C_1;
393 init_i2c |= IOP13XX_INIT_I2C_2;
395 /* only enable i2c 1 and 2 */
397 init_i2c |= IOP13XX_INIT_I2C_1;
398 init_i2c |= IOP13XX_INIT_I2C_2;
402 if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
403 init_adma |= IOP13XX_INIT_ADMA_0;
404 init_adma |= IOP13XX_INIT_ADMA_1;
405 init_adma |= IOP13XX_INIT_ADMA_2;
412 /* uart 1 (if enabled) is ttyS0 */
413 if (init_uart & IOP13XX_INIT_UART_1) {
414 PRINTK("Adding uart1 to platform device list\n");
415 iop13xx_uart1.id = uart_idx++;
416 iop13xx_devices[plat_idx++] = &iop13xx_uart1;
418 if (init_uart & IOP13XX_INIT_UART_0) {
419 PRINTK("Adding uart0 to platform device list\n");
420 iop13xx_uart0.id = uart_idx++;
421 iop13xx_devices[plat_idx++] = &iop13xx_uart0;
424 for(i = 0; i < IQ81340_NUM_I2C; i++) {
425 if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
426 printk("Adding i2c%d to platform device list\n", i);
427 switch(init_i2c & (1 << i)) {
428 case IOP13XX_INIT_I2C_0:
429 iop13xx_i2c_0_controller.id = i2c_idx++;
430 iop13xx_devices[plat_idx++] =
431 &iop13xx_i2c_0_controller;
433 case IOP13XX_INIT_I2C_1:
434 iop13xx_i2c_1_controller.id = i2c_idx++;
435 iop13xx_devices[plat_idx++] =
436 &iop13xx_i2c_1_controller;
438 case IOP13XX_INIT_I2C_2:
439 iop13xx_i2c_2_controller.id = i2c_idx++;
440 iop13xx_devices[plat_idx++] =
441 &iop13xx_i2c_2_controller;
446 /* initialize adma channel ids and capabilities */
448 for (i = 0; i < IQ81340_NUM_ADMA; i++) {
449 struct iop_adma_platform_data *plat_data;
450 if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
452 "Adding adma%d to platform device list\n", i);
453 switch (init_adma & (1 << i)) {
454 case IOP13XX_INIT_ADMA_0:
455 iop13xx_adma_0_channel.id = adma_idx++;
456 iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
457 plat_data = &iop13xx_adma_0_data;
458 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
459 dma_cap_set(DMA_XOR, plat_data->cap_mask);
460 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
461 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
463 case IOP13XX_INIT_ADMA_1:
464 iop13xx_adma_1_channel.id = adma_idx++;
465 iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
466 plat_data = &iop13xx_adma_1_data;
467 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
468 dma_cap_set(DMA_XOR, plat_data->cap_mask);
469 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
470 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
472 case IOP13XX_INIT_ADMA_2:
473 iop13xx_adma_2_channel.id = adma_idx++;
474 iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
475 plat_data = &iop13xx_adma_2_data;
476 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
477 dma_cap_set(DMA_XOR, plat_data->cap_mask);
478 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
479 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
480 dma_cap_set(DMA_PQ, plat_data->cap_mask);
481 dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
486 #ifdef CONFIG_MTD_PHYSMAP
487 iq8134x_flash_resource.end = iq8134x_flash_resource.start +
488 iq8134x_probe_flash_size() - 1;
489 if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
490 iop13xx_devices[plat_idx++] = &iq8134x_flash;
492 printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
495 platform_add_devices(iop13xx_devices, plat_idx);
498 static int __init iop13xx_init_uart_setup(char *str)
501 while (*str != '\0') {
504 init_uart |= IOP13XX_INIT_UART_0;
507 init_uart |= IOP13XX_INIT_UART_1;
513 PRINTK("\"iop13xx_init_uart\" malformed"
514 " at character: \'%c\'", *str);
516 init_uart = IOP13XX_INIT_UART_DEFAULT;
524 static int __init iop13xx_init_i2c_setup(char *str)
527 while (*str != '\0') {
530 init_i2c |= IOP13XX_INIT_I2C_0;
533 init_i2c |= IOP13XX_INIT_I2C_1;
536 init_i2c |= IOP13XX_INIT_I2C_2;
542 PRINTK("\"iop13xx_init_i2c\" malformed"
543 " at character: \'%c\'", *str);
545 init_i2c = IOP13XX_INIT_I2C_DEFAULT;
553 static int __init iop13xx_init_adma_setup(char *str)
556 while (*str != '\0') {
559 init_adma |= IOP13XX_INIT_ADMA_0;
562 init_adma |= IOP13XX_INIT_ADMA_1;
565 init_adma |= IOP13XX_INIT_ADMA_2;
571 PRINTK("\"iop13xx_init_adma\" malformed"
572 " at character: \'%c\'", *str);
574 init_adma = IOP13XX_INIT_ADMA_DEFAULT;
582 __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
583 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
584 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
586 void iop13xx_restart(enum reboot_mode mode, const char *cmd)
589 * Reset the internal bus (warning both cores are reset)
591 write_wdtcr(IOP_WDTCR_EN_ARM);
592 write_wdtcr(IOP_WDTCR_EN);
593 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);