1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-iop13xx/msi.c
5 * PCI MSI support for the iop13xx processor
7 * Copyright (c) 2006, Intel Corporation.
10 #include <linux/msi.h>
11 #include <asm/mach/irq.h>
13 #include <mach/irqs.h>
15 /* IMIPR0 CP6 R8 Page 1
17 static u32 read_imipr_0(void)
20 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
23 static void write_imipr_0(u32 val)
25 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
28 /* IMIPR1 CP6 R9 Page 1
30 static u32 read_imipr_1(void)
33 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
36 static void write_imipr_1(u32 val)
38 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
41 /* IMIPR2 CP6 R10 Page 1
43 static u32 read_imipr_2(void)
46 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
49 static void write_imipr_2(u32 val)
51 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
54 /* IMIPR3 CP6 R11 Page 1
56 static u32 read_imipr_3(void)
59 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
62 static void write_imipr_3(u32 val)
64 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
67 static u32 (*read_imipr[])(void) = {
74 static void (*write_imipr[])(u32) = {
81 static void iop13xx_msi_handler(struct irq_desc *desc)
86 /* read IMIPR registers and find any active interrupts,
87 * then call ISR for each active interrupt
89 for (i = 0; i < ARRAY_SIZE(read_imipr); i++) {
90 status = (read_imipr[i])();
95 j = find_first_bit(&status, 32);
96 (write_imipr[i])(1 << j); /* write back to clear bit */
97 generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
98 status = (read_imipr[i])();
103 void __init iop13xx_msi_init(void)
105 irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
108 static void iop13xx_msi_nop(struct irq_data *d)
113 static struct irq_chip iop13xx_msi_chip = {
115 .irq_ack = iop13xx_msi_nop,
116 .irq_enable = pci_msi_unmask_irq,
117 .irq_disable = pci_msi_mask_irq,
118 .irq_mask = pci_msi_mask_irq,
119 .irq_unmask = pci_msi_unmask_irq,
122 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
124 int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
130 if (irq >= NR_IOP13XX_IRQS) {
135 irq_set_msi_desc(irq, desc);
137 msg.address_hi = 0x0;
138 msg.address_lo = IOP13XX_MU_MIMR_PCI;
140 id = iop13xx_cpu_id();
141 msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
143 pci_write_msi_msg(irq, &msg);
144 irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
149 void arch_teardown_msi_irq(unsigned int irq)