2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/delay.h>
16 #include <linux/irq.h>
17 #include <linux/irqchip.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_domain.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/irqchip/arm-gic.h>
28 #define GPC_CNTR 0x000
29 #define GPC_IMR1 0x008
30 #define GPC_PGC_GPU_PDN 0x260
31 #define GPC_PGC_GPU_PUPSCR 0x264
32 #define GPC_PGC_GPU_PDNSCR 0x268
33 #define GPC_PGC_CPU_PDN 0x2a0
34 #define GPC_PGC_CPU_PUPSCR 0x2a4
35 #define GPC_PGC_CPU_PDNSCR 0x2a8
36 #define GPC_PGC_SW2ISO_SHIFT 0x8
37 #define GPC_PGC_SW_SHIFT 0x0
40 #define GPC_MAX_IRQS (IMR_NUM * 32)
42 #define GPU_VPU_PUP_REQ BIT(1)
43 #define GPU_VPU_PDN_REQ BIT(0)
48 struct generic_pm_domain base;
49 struct regulator *reg;
50 struct clk *clk[GPC_CLK_MAX];
54 static void __iomem *gpc_base;
55 static u32 gpc_wake_irqs[IMR_NUM];
56 static u32 gpc_saved_imrs[IMR_NUM];
58 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
60 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
61 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
64 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
66 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
67 (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
70 void imx_gpc_set_arm_power_in_lpm(bool power_off)
72 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
75 void imx_gpc_pre_suspend(bool arm_power_off)
77 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
80 /* Tell GPC to power off ARM core when suspend */
82 imx_gpc_set_arm_power_in_lpm(arm_power_off);
84 for (i = 0; i < IMR_NUM; i++) {
85 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
86 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
90 void imx_gpc_post_resume(void)
92 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
95 /* Keep ARM core powered on for other low-power modes */
96 imx_gpc_set_arm_power_in_lpm(false);
98 for (i = 0; i < IMR_NUM; i++)
99 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
102 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
104 unsigned int idx = d->hwirq / 32;
107 mask = 1 << d->hwirq % 32;
108 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
109 gpc_wake_irqs[idx] & ~mask;
112 * Do *not* call into the parent, as the GIC doesn't have any
113 * wake-up facility...
118 void imx_gpc_mask_all(void)
120 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
123 for (i = 0; i < IMR_NUM; i++) {
124 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
125 writel_relaxed(~0, reg_imr1 + i * 4);
130 void imx_gpc_restore_all(void)
132 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
135 for (i = 0; i < IMR_NUM; i++)
136 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
139 void imx_gpc_hwirq_unmask(unsigned int hwirq)
144 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
145 val = readl_relaxed(reg);
146 val &= ~(1 << hwirq % 32);
147 writel_relaxed(val, reg);
150 void imx_gpc_hwirq_mask(unsigned int hwirq)
155 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
156 val = readl_relaxed(reg);
157 val |= 1 << (hwirq % 32);
158 writel_relaxed(val, reg);
161 static void imx_gpc_irq_unmask(struct irq_data *d)
163 imx_gpc_hwirq_unmask(d->hwirq);
164 irq_chip_unmask_parent(d);
167 static void imx_gpc_irq_mask(struct irq_data *d)
169 imx_gpc_hwirq_mask(d->hwirq);
170 irq_chip_mask_parent(d);
173 static struct irq_chip imx_gpc_chip = {
175 .irq_eoi = irq_chip_eoi_parent,
176 .irq_mask = imx_gpc_irq_mask,
177 .irq_unmask = imx_gpc_irq_unmask,
178 .irq_retrigger = irq_chip_retrigger_hierarchy,
179 .irq_set_wake = imx_gpc_irq_set_wake,
181 .irq_set_affinity = irq_chip_set_affinity_parent,
185 static int imx_gpc_domain_xlate(struct irq_domain *domain,
186 struct device_node *controller,
188 unsigned int intsize,
189 unsigned long *out_hwirq,
190 unsigned int *out_type)
192 if (domain->of_node != controller)
193 return -EINVAL; /* Shouldn't happen, really... */
195 return -EINVAL; /* Not GIC compliant */
197 return -EINVAL; /* No PPI should point to this domain */
199 *out_hwirq = intspec[1];
200 *out_type = intspec[2];
204 static int imx_gpc_domain_alloc(struct irq_domain *domain,
206 unsigned int nr_irqs, void *data)
208 struct of_phandle_args *args = data;
209 struct of_phandle_args parent_args;
210 irq_hw_number_t hwirq;
213 if (args->args_count != 3)
214 return -EINVAL; /* Not GIC compliant */
215 if (args->args[0] != 0)
216 return -EINVAL; /* No PPI should point to this domain */
218 hwirq = args->args[1];
219 if (hwirq >= GPC_MAX_IRQS)
220 return -EINVAL; /* Can't deal with this */
222 for (i = 0; i < nr_irqs; i++)
223 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
224 &imx_gpc_chip, NULL);
227 parent_args.np = domain->parent->of_node;
228 return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
231 static const struct irq_domain_ops imx_gpc_domain_ops = {
232 .xlate = imx_gpc_domain_xlate,
233 .alloc = imx_gpc_domain_alloc,
234 .free = irq_domain_free_irqs_common,
237 static int __init imx_gpc_init(struct device_node *node,
238 struct device_node *parent)
240 struct irq_domain *parent_domain, *domain;
244 pr_err("%s: no parent, giving up\n", node->full_name);
248 parent_domain = irq_find_host(parent);
249 if (!parent_domain) {
250 pr_err("%s: unable to obtain parent domain\n", node->full_name);
254 gpc_base = of_iomap(node, 0);
255 if (WARN_ON(!gpc_base))
258 domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
259 node, &imx_gpc_domain_ops,
266 /* Initially mask all interrupts */
267 for (i = 0; i < IMR_NUM; i++)
268 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
272 IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
274 void __init imx_gpc_check_dt(void)
276 struct device_node *np;
278 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
282 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
283 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
285 /* map GPC, so that at least CPUidle and WARs keep working */
286 gpc_base = of_iomap(np, 0);
290 static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
295 /* Read ISO and ISO2SW power down delays */
296 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
298 iso2sw = (val >> 8) & 0x3f;
300 /* Gate off PU domain when GPU/VPU when powered down */
301 writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
303 /* Request GPC to power down GPU/VPU */
304 val = readl_relaxed(gpc_base + GPC_CNTR);
305 val |= GPU_VPU_PDN_REQ;
306 writel_relaxed(val, gpc_base + GPC_CNTR);
308 /* Wait ISO + ISO2SW IPG clock cycles */
309 ndelay((iso + iso2sw) * 1000 / 66);
312 static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
314 struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
316 _imx6q_pm_pu_power_off(genpd);
319 regulator_disable(pu->reg);
324 static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
326 struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
327 int i, ret, sw, sw2iso;
331 ret = regulator_enable(pu->reg);
332 if (pu->reg && ret) {
333 pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
337 /* Enable reset clocks for all devices in the PU domain */
338 for (i = 0; i < pu->num_clks; i++)
339 clk_prepare_enable(pu->clk[i]);
341 /* Gate off PU domain when GPU/VPU when powered down */
342 writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
344 /* Read ISO and ISO2SW power down delays */
345 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
347 sw2iso = (val >> 8) & 0x3f;
349 /* Request GPC to power up GPU/VPU */
350 val = readl_relaxed(gpc_base + GPC_CNTR);
351 val |= GPU_VPU_PUP_REQ;
352 writel_relaxed(val, gpc_base + GPC_CNTR);
354 /* Wait ISO + ISO2SW IPG clock cycles */
355 ndelay((sw + sw2iso) * 1000 / 66);
357 /* Disable reset clocks for all devices in the PU domain */
358 for (i = 0; i < pu->num_clks; i++)
359 clk_disable_unprepare(pu->clk[i]);
364 static struct generic_pm_domain imx6q_arm_domain = {
368 static struct pu_domain imx6q_pu_domain = {
371 .power_off = imx6q_pm_pu_power_off,
372 .power_on = imx6q_pm_pu_power_on,
373 .power_off_latency_ns = 25000,
374 .power_on_latency_ns = 2000000,
378 static struct generic_pm_domain imx6sl_display_domain = {
382 static struct generic_pm_domain *imx_gpc_domains[] = {
384 &imx6q_pu_domain.base,
385 &imx6sl_display_domain,
388 static struct genpd_onecell_data imx_gpc_onecell_data = {
389 .domains = imx_gpc_domains,
390 .num_domains = ARRAY_SIZE(imx_gpc_domains),
393 static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
398 imx6q_pu_domain.reg = pu_reg;
401 clk = of_clk_get(dev->of_node, i);
404 if (i >= GPC_CLK_MAX) {
405 dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
408 imx6q_pu_domain.clk[i] = clk;
410 imx6q_pu_domain.num_clks = i;
412 /* Enable power always in case bootloader disabled it. */
413 imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
415 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
418 pm_genpd_init(&imx6q_pu_domain.base, NULL, false);
419 return of_genpd_add_provider_onecell(dev->of_node,
420 &imx_gpc_onecell_data);
424 clk_put(imx6q_pu_domain.clk[i]);
428 static int imx_gpc_probe(struct platform_device *pdev)
430 struct regulator *pu_reg;
433 /* bail out if DT too old and doesn't provide the necessary info */
434 if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
437 pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
438 if (PTR_ERR(pu_reg) == -ENODEV)
440 if (IS_ERR(pu_reg)) {
441 ret = PTR_ERR(pu_reg);
442 dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
446 return imx_gpc_genpd_init(&pdev->dev, pu_reg);
449 static const struct of_device_id imx_gpc_dt_ids[] = {
450 { .compatible = "fsl,imx6q-gpc" },
451 { .compatible = "fsl,imx6sl-gpc" },
455 static struct platform_driver imx_gpc_driver = {
458 .of_match_table = imx_gpc_dt_ids,
460 .probe = imx_gpc_probe,
463 static int __init imx_pgc_init(void)
465 return platform_driver_register(&imx_gpc_driver);
467 subsys_initcall(imx_pgc_init);