2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
14 #include <linux/irq.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/irqchip/arm-gic.h>
21 #define GPC_IMR1 0x008
22 #define GPC_PGC_CPU_PDN 0x2a0
26 static void __iomem *gpc_base;
27 static u32 gpc_wake_irqs[IMR_NUM];
28 static u32 gpc_saved_imrs[IMR_NUM];
30 void imx_gpc_pre_suspend(bool arm_power_off)
32 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
35 /* Tell GPC to power off ARM core when suspend */
37 writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
39 for (i = 0; i < IMR_NUM; i++) {
40 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
41 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
45 void imx_gpc_post_resume(void)
47 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
50 /* Keep ARM core powered on for other low-power modes */
51 writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
53 for (i = 0; i < IMR_NUM; i++)
54 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
57 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
59 unsigned int idx = d->hwirq / 32 - 1;
62 /* Sanity check for SPI irq */
66 mask = 1 << d->hwirq % 32;
67 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
68 gpc_wake_irqs[idx] & ~mask;
73 void imx_gpc_mask_all(void)
75 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
78 for (i = 0; i < IMR_NUM; i++) {
79 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
80 writel_relaxed(~0, reg_imr1 + i * 4);
85 void imx_gpc_restore_all(void)
87 void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
90 for (i = 0; i < IMR_NUM; i++)
91 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
94 void imx_gpc_hwirq_unmask(unsigned int hwirq)
99 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
100 val = readl_relaxed(reg);
101 val &= ~(1 << hwirq % 32);
102 writel_relaxed(val, reg);
105 void imx_gpc_hwirq_mask(unsigned int hwirq)
110 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
111 val = readl_relaxed(reg);
112 val |= 1 << (hwirq % 32);
113 writel_relaxed(val, reg);
116 static void imx_gpc_irq_unmask(struct irq_data *d)
118 /* Sanity check for SPI irq */
122 imx_gpc_hwirq_unmask(d->hwirq);
125 static void imx_gpc_irq_mask(struct irq_data *d)
127 /* Sanity check for SPI irq */
131 imx_gpc_hwirq_mask(d->hwirq);
134 void __init imx_gpc_init(void)
136 struct device_node *np;
139 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
140 gpc_base = of_iomap(np, 0);
143 /* Initially mask all interrupts */
144 for (i = 0; i < IMR_NUM; i++)
145 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
147 /* Register GPC as the secondary interrupt controller behind GIC */
148 gic_arch_extn.irq_mask = imx_gpc_irq_mask;
149 gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
150 gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;