2 * Copyright (c) 2013 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 #include <linux/cpu.h>
11 #include <linux/delay.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <asm/cacheflush.h>
16 #include <asm/smp_plat.h>
19 /* Sysctrl registers in Hi3620 SoC */
22 #define SCPERPWREN 0xd0
23 #define SCPERPWRDIS 0xd4
24 #define SCCPUCOREEN 0xf4
25 #define SCCPUCOREDIS 0xf8
26 #define SCPERCTRL0 0x200
27 #define SCCPURSTEN 0x410
28 #define SCCPURSTDIS 0x414
31 * bit definition in SCISOEN/SCPERPWREN/...
33 * CPU2_ISO_CTRL (1 << 5)
34 * CPU3_ISO_CTRL (1 << 6)
37 #define CPU2_ISO_CTRL (1 << 5)
40 * bit definition in SCPERCTRL0
42 * CPU0_WFI_MASK_CFG (1 << 28)
43 * CPU1_WFI_MASK_CFG (1 << 29)
46 #define CPU0_WFI_MASK_CFG (1 << 28)
49 * bit definition in SCCPURSTEN/...
51 * CPU0_SRST_REQ_EN (1 << 0)
52 * CPU1_SRST_REQ_EN (1 << 1)
55 #define CPU0_HPM_SRST_REQ_EN (1 << 22)
56 #define CPU0_DBG_SRST_REQ_EN (1 << 12)
57 #define CPU0_NEON_SRST_REQ_EN (1 << 4)
58 #define CPU0_SRST_REQ_EN (1 << 0)
60 #define HIX5HD2_PERI_CRG20 0x50
61 #define CRG20_CPU1_RESET (1 << 17)
63 #define HIX5HD2_PERI_PMC0 0x1000
64 #define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
65 #define PMC0_CPU1_PMC_ENABLE (1 << 7)
66 #define PMC0_CPU1_POWERDOWN (1 << 3)
73 static void __iomem *ctrl_base;
76 static void set_cpu_hi3620(int cpu, bool enable)
82 if ((cpu == 2) || (cpu == 3))
83 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
84 ctrl_base + SCPERPWREN);
88 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
91 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
93 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
95 val |= CPU0_HPM_SRST_REQ_EN;
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
99 if ((cpu == 2) || (cpu == 3))
100 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
101 ctrl_base + SCISODIS);
105 val = readl_relaxed(ctrl_base + SCPERCTRL0);
106 val &= ~(CPU0_WFI_MASK_CFG << cpu);
107 writel_relaxed(val, ctrl_base + SCPERCTRL0);
110 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
111 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
112 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
115 val = readl_relaxed(ctrl_base + SCPERCTRL0);
116 val |= (CPU0_WFI_MASK_CFG << cpu);
117 writel_relaxed(val, ctrl_base + SCPERCTRL0);
120 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
122 if ((cpu == 2) || (cpu == 3)) {
124 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
125 ctrl_base + SCISOEN);
130 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
131 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
132 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
134 if ((cpu == 2) || (cpu == 3)) {
136 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
137 ctrl_base + SCPERPWRDIS);
143 static int hi3xxx_hotplug_init(void)
145 struct device_node *node;
147 node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
149 ctrl_base = of_iomap(node, 0);
157 void hi3xxx_set_cpu(int cpu, bool enable)
160 if (hi3xxx_hotplug_init() < 0)
164 if (id == HI3620_CTRL)
165 set_cpu_hi3620(cpu, enable);
168 static bool hix5hd2_hotplug_init(void)
170 struct device_node *np;
172 np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
174 ctrl_base = of_iomap(np, 0);
180 void hix5hd2_set_cpu(int cpu, bool enable)
185 if (!hix5hd2_hotplug_init())
190 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
191 val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
192 val |= PMC0_CPU1_PMC_ENABLE;
193 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
195 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
196 val &= ~CRG20_CPU1_RESET;
197 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
199 /* power down cpu1 */
200 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
201 val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
202 val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
203 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
206 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
207 val |= CRG20_CPU1_RESET;
208 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
212 static inline void cpu_enter_lowpower(void)
219 * Turn off coherency and L1 D-cache
222 " mrc p15, 0, %0, c1, c0, 1\n"
223 " bic %0, %0, #0x40\n"
224 " mcr p15, 0, %0, c1, c0, 1\n"
225 " mrc p15, 0, %0, c1, c0, 0\n"
226 " bic %0, %0, #0x04\n"
227 " mcr p15, 0, %0, c1, c0, 0\n"
233 #ifdef CONFIG_HOTPLUG_CPU
234 void hi3xxx_cpu_die(unsigned int cpu)
236 cpu_enter_lowpower();
237 hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
240 /* We should have never returned from idle */
241 panic("cpu %d unexpectedly exit from shutdown\n", cpu);
244 int hi3xxx_cpu_kill(unsigned int cpu)
246 unsigned long timeout = jiffies + msecs_to_jiffies(50);
248 while (hi3xxx_get_cpu_jump(cpu))
249 if (time_after(jiffies, timeout))
251 hi3xxx_set_cpu(cpu, false);
255 void hix5hd2_cpu_die(unsigned int cpu)
258 hix5hd2_set_cpu(cpu, false);