1 /* linux/arch/arm/mach-exynos4/cpu.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/sched.h>
12 #include <linux/sysdev.h>
14 #include <asm/mach/map.h>
15 #include <asm/mach/irq.h>
17 #include <asm/proc-fns.h>
18 #include <asm/hardware/cache-l2x0.h>
19 #include <asm/hardware/gic.h>
22 #include <plat/clock.h>
23 #include <plat/devs.h>
24 #include <plat/exynos4.h>
25 #include <plat/adc-core.h>
26 #include <plat/sdhci.h>
27 #include <plat/devs.h>
28 #include <plat/fb-core.h>
29 #include <plat/fimc-core.h>
30 #include <plat/iic-core.h>
32 #include <mach/regs-irq.h>
34 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
35 unsigned int irq_start);
36 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
38 /* Initial IO mappings */
39 static struct map_desc exynos4_iodesc[] __initdata = {
41 .virtual = (unsigned long)S5P_VA_SYSTIMER,
42 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
46 .virtual = (unsigned long)S5P_VA_SYSRAM,
47 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
51 .virtual = (unsigned long)S5P_VA_CMU,
52 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
56 .virtual = (unsigned long)S5P_VA_PMU,
57 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
61 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
62 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
66 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
67 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
71 .virtual = (unsigned long)S5P_VA_L2CC,
72 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
76 .virtual = (unsigned long)S5P_VA_GPIO1,
77 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
81 .virtual = (unsigned long)S5P_VA_GPIO2,
82 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
86 .virtual = (unsigned long)S5P_VA_GPIO3,
87 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
91 .virtual = (unsigned long)S5P_VA_DMC0,
92 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
96 .virtual = (unsigned long)S3C_VA_UART,
97 .pfn = __phys_to_pfn(S3C_PA_UART),
101 .virtual = (unsigned long)S5P_VA_SROMC,
102 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
106 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
107 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
111 .virtual = (unsigned long)S5P_VA_GIC_CPU,
112 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
116 .virtual = (unsigned long)S5P_VA_GIC_DIST,
117 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
123 static void exynos4_idle(void)
134 * register the standard cpu IO areas
136 void __init exynos4_map_io(void)
138 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
140 /* initialize device information early */
141 exynos4_default_sdhci0();
142 exynos4_default_sdhci1();
143 exynos4_default_sdhci2();
144 exynos4_default_sdhci3();
146 s3c_adc_setname("samsung-adc-v3");
148 s3c_fimc_setname(0, "exynos4-fimc");
149 s3c_fimc_setname(1, "exynos4-fimc");
150 s3c_fimc_setname(2, "exynos4-fimc");
151 s3c_fimc_setname(3, "exynos4-fimc");
153 /* The I2C bus controllers are directly compatible with s3c2440 */
154 s3c_i2c0_setname("s3c2440-i2c");
155 s3c_i2c1_setname("s3c2440-i2c");
156 s3c_i2c2_setname("s3c2440-i2c");
158 s5p_fb_setname(0, "exynos4-fb");
161 void __init exynos4_init_clocks(int xtal)
163 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
165 s3c24xx_register_baseclocks(xtal);
166 s5p_register_clocks(xtal);
167 exynos4_register_clocks();
168 exynos4_setup_clocks();
171 static void exynos4_gic_irq_eoi(struct irq_data *d)
173 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
175 gic_data->cpu_base = S5P_VA_GIC_CPU +
176 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
179 void __init exynos4_init_irq(void)
183 gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
184 gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
186 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
188 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
189 COMBINER_IRQ(irq, 0));
190 combiner_cascade_irq(irq, IRQ_SPI(irq));
193 /* The parameters of s5p_init_irq() are for VIC init.
194 * Theses parameters should be NULL and 0 because EXYNOS4
195 * uses GIC instead of VIC.
197 s5p_init_irq(NULL, 0);
200 struct sysdev_class exynos4_sysclass = {
201 .name = "exynos4-core",
204 static struct sys_device exynos4_sysdev = {
205 .cls = &exynos4_sysclass,
208 static int __init exynos4_core_init(void)
210 return sysdev_class_register(&exynos4_sysclass);
213 core_initcall(exynos4_core_init);
215 #ifdef CONFIG_CACHE_L2X0
216 static int __init exynos4_l2x0_cache_init(void)
218 /* TAG, Data Latency Control: 2cycle */
219 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
220 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
222 /* L2X0 Prefetch Control */
223 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
225 /* L2X0 Power Control */
226 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
227 S5P_VA_L2CC + L2X0_POWER_CTRL);
229 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
234 early_initcall(exynos4_l2x0_cache_init);
237 int __init exynos4_init(void)
239 printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
241 /* set idle function */
242 pm_idle = exynos4_idle;
244 return sysdev_register(&exynos4_sysdev);