arch/arm/mach-exynos4/cpu.c

   1 /* linux/arch/arm/mach-exynos4/cpu.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19 #include <asm/hardware/gic.h>
  20
  21 #include <plat/cpu.h>
  22 #include <plat/clock.h>
  23 #include <plat/devs.h>
  24 #include <plat/exynos4.h>
  25 #include <plat/adc-core.h>
  26 #include <plat/sdhci.h>
  27 #include <plat/fb-core.h>
  28 #include <plat/fimc-core.h>
  29 #include <plat/iic-core.h>
  30 #include <plat/reset.h>
  31
  32 #include <mach/regs-irq.h>
  33 #include <mach/regs-pmu.h>
  34
  35 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  36                          unsigned int irq_start);
  37 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  38
  39 /* Initial IO mappings */
  40 static struct map_desc exynos4_iodesc[] __initdata = {
  41         {
  42                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  43                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  44                 .length         = SZ_4K,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = (unsigned long)S5P_VA_CMU,
  48                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  49                 .length         = SZ_128K,
  50                 .type           = MT_DEVICE,
  51         }, {
  52                 .virtual        = (unsigned long)S5P_VA_PMU,
  53                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  54                 .length         = SZ_64K,
  55                 .type           = MT_DEVICE,
  56         }, {
  57                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  58                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  59                 .length         = SZ_4K,
  60                 .type           = MT_DEVICE,
  61         }, {
  62                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  63                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  64                 .length         = SZ_8K,
  65                 .type           = MT_DEVICE,
  66         }, {
  67                 .virtual        = (unsigned long)S5P_VA_L2CC,
  68                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  69                 .length         = SZ_4K,
  70                 .type           = MT_DEVICE,
  71         }, {
  72                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  73                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
  74                 .length         = SZ_4K,
  75                 .type           = MT_DEVICE,
  76         }, {
  77                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  78                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
  79                 .length         = SZ_4K,
  80                 .type           = MT_DEVICE,
  81         }, {
  82                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  83                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
  84                 .length         = SZ_256,
  85                 .type           = MT_DEVICE,
  86         }, {
  87                 .virtual        = (unsigned long)S5P_VA_DMC0,
  88                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  89                 .length         = SZ_4K,
  90                 .type           = MT_DEVICE,
  91         }, {
  92                 .virtual        = (unsigned long)S3C_VA_UART,
  93                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  94                 .length         = SZ_512K,
  95                 .type           = MT_DEVICE,
  96         }, {
  97                 .virtual        = (unsigned long)S5P_VA_SROMC,
  98                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  99                 .length         = SZ_4K,
 100                 .type           = MT_DEVICE,
 101         }, {
 102                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 103                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 104                 .length         = SZ_4K,
 105                 .type           = MT_DEVICE,
 106         }, {
 107                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 108                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 109                 .length         = SZ_64K,
 110                 .type           = MT_DEVICE,
 111         }, {
 112                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 113                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 114                 .length         = SZ_64K,
 115                 .type           = MT_DEVICE,
 116         },
 117 };
 118
 119 static struct map_desc exynos4_iodesc0[] __initdata = {
 120         {
 121                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 122                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 123                 .length         = SZ_4K,
 124                 .type           = MT_DEVICE,
 125         },
 126 };
 127
 128 static struct map_desc exynos4_iodesc1[] __initdata = {
 129         {
 130                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 131                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 132                 .length         = SZ_4K,
 133                 .type           = MT_DEVICE,
 134         },
 135 };
 136
 137 static void exynos4_idle(void)
 138 {
 139         if (!need_resched())
 140                 cpu_do_idle();
 141
 142         local_irq_enable();
 143 }
 144
 145 static void exynos4_sw_reset(void)
 146 {
 147         __raw_writel(0x1, S5P_SWRESET);
 148 }
 149
 150 /*
 151  * exynos4_map_io
 152  *
 153  * register the standard cpu IO areas
 154  */
 155 void __init exynos4_map_io(void)
 156 {
 157         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 158
 159         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 160                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 161         else
 162                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 163
 164         /* initialize device information early */
 165         exynos4_default_sdhci0();
 166         exynos4_default_sdhci1();
 167         exynos4_default_sdhci2();
 168         exynos4_default_sdhci3();
 169
 170         s3c_adc_setname("samsung-adc-v3");
 171
 172         s3c_fimc_setname(0, "exynos4-fimc");
 173         s3c_fimc_setname(1, "exynos4-fimc");
 174         s3c_fimc_setname(2, "exynos4-fimc");
 175         s3c_fimc_setname(3, "exynos4-fimc");
 176
 177         /* The I2C bus controllers are directly compatible with s3c2440 */
 178         s3c_i2c0_setname("s3c2440-i2c");
 179         s3c_i2c1_setname("s3c2440-i2c");
 180         s3c_i2c2_setname("s3c2440-i2c");
 181
 182         s5p_fb_setname(0, "exynos4-fb");
 183 }
 184
 185 void __init exynos4_init_clocks(int xtal)
 186 {
 187         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 188
 189         s3c24xx_register_baseclocks(xtal);
 190         s5p_register_clocks(xtal);
 191         exynos4_register_clocks();
 192         exynos4_setup_clocks();
 193 }
 194
 195 static void exynos4_gic_irq_eoi(struct irq_data *d)
 196 {
 197         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 198
 199         gic_data->cpu_base = S5P_VA_GIC_CPU +
 200                             (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
 201 }
 202
 203 void __init exynos4_init_irq(void)
 204 {
 205         int irq;
 206
 207         gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 208         gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
 209
 210         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 211
 212                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 213                                 COMBINER_IRQ(irq, 0));
 214                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 215         }
 216
 217         /* The parameters of s5p_init_irq() are for VIC init.
 218          * Theses parameters should be NULL and 0 because EXYNOS4
 219          * uses GIC instead of VIC.
 220          */
 221         s5p_init_irq(NULL, 0);
 222 }
 223
 224 struct sysdev_class exynos4_sysclass = {
 225         .name   = "exynos4-core",
 226 };
 227
 228 static struct sys_device exynos4_sysdev = {
 229         .cls    = &exynos4_sysclass,
 230 };
 231
 232 static int __init exynos4_core_init(void)
 233 {
 234         return sysdev_class_register(&exynos4_sysclass);
 235 }
 236
 237 core_initcall(exynos4_core_init);
 238
 239 #ifdef CONFIG_CACHE_L2X0
 240 static int __init exynos4_l2x0_cache_init(void)
 241 {
 242         /* TAG, Data Latency Control: 2cycle */
 243         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 244         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 245
 246         /* L2X0 Prefetch Control */
 247         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 248
 249         /* L2X0 Power Control */
 250         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 251                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 252
 253         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 254
 255         return 0;
 256 }
 257
 258 early_initcall(exynos4_l2x0_cache_init);
 259 #endif
 260
 261 int __init exynos4_init(void)
 262 {
 263         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 264
 265         /* set idle function */
 266         pm_idle = exynos4_idle;
 267
 268         /* set sw_reset function */
 269         s5p_reset_hook = exynos4_sw_reset;
 270
 271         return sysdev_register(&exynos4_sysdev);
 272 }