2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Suspend support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/of_address.h>
24 #include <linux/err.h>
25 #include <linux/regulator/machine.h>
27 #include <asm/cacheflush.h>
28 #include <asm/hardware/cache-l2x0.h>
29 #include <asm/firmware.h>
31 #include <asm/smp_scu.h>
32 #include <asm/suspend.h>
34 #include <plat/pm-common.h>
37 #include "exynos-pmu.h"
39 #include "regs-srom.h"
41 #define REG_TABLE_END (-1U)
43 #define EXYNOS5420_CPU_STATE 0x28
46 * struct exynos_wkup_irq - PMU IRQ to mask mapping
47 * @hwirq: Hardware IRQ signal of the PMU
48 * @mask: Mask in PMU wake-up mask register
50 struct exynos_wkup_irq {
55 static struct sleep_save exynos_core_save[] = {
57 SAVE_ITEM(S5P_SROM_BW),
58 SAVE_ITEM(S5P_SROM_BC0),
59 SAVE_ITEM(S5P_SROM_BC1),
60 SAVE_ITEM(S5P_SROM_BC2),
61 SAVE_ITEM(S5P_SROM_BC3),
64 struct exynos_pm_data {
65 const struct exynos_wkup_irq *wkup_irq;
66 unsigned int wake_disable_mask;
67 unsigned int *release_ret_regs;
69 void (*pm_prepare)(void);
70 void (*pm_resume_prepare)(void);
71 void (*pm_resume)(void);
72 int (*pm_suspend)(void);
73 int (*cpu_suspend)(unsigned long);
76 static const struct exynos_pm_data *pm_data;
78 static int exynos5420_cpu_state;
79 static unsigned int exynos_pmu_spare3;
85 static u32 exynos_irqwake_intmask = 0xffffffff;
87 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
88 { 73, BIT(1) }, /* RTC alarm */
89 { 74, BIT(2) }, /* RTC tick */
93 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
94 { 44, BIT(1) }, /* RTC alarm */
95 { 45, BIT(2) }, /* RTC tick */
99 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
100 { 43, BIT(1) }, /* RTC alarm */
101 { 44, BIT(2) }, /* RTC tick */
105 static unsigned int exynos_release_ret_regs[] = {
106 S5P_PAD_RET_MAUDIO_OPTION,
107 S5P_PAD_RET_GPIO_OPTION,
108 S5P_PAD_RET_UART_OPTION,
109 S5P_PAD_RET_MMCA_OPTION,
110 S5P_PAD_RET_MMCB_OPTION,
111 S5P_PAD_RET_EBIA_OPTION,
112 S5P_PAD_RET_EBIB_OPTION,
116 static unsigned int exynos3250_release_ret_regs[] = {
117 S5P_PAD_RET_MAUDIO_OPTION,
118 S5P_PAD_RET_GPIO_OPTION,
119 S5P_PAD_RET_UART_OPTION,
120 S5P_PAD_RET_MMCA_OPTION,
121 S5P_PAD_RET_MMCB_OPTION,
122 S5P_PAD_RET_EBIA_OPTION,
123 S5P_PAD_RET_EBIB_OPTION,
124 S5P_PAD_RET_MMC2_OPTION,
125 S5P_PAD_RET_SPI_OPTION,
129 static unsigned int exynos5420_release_ret_regs[] = {
130 EXYNOS_PAD_RET_DRAM_OPTION,
131 EXYNOS_PAD_RET_MAUDIO_OPTION,
132 EXYNOS_PAD_RET_JTAG_OPTION,
133 EXYNOS5420_PAD_RET_GPIO_OPTION,
134 EXYNOS5420_PAD_RET_UART_OPTION,
135 EXYNOS5420_PAD_RET_MMCA_OPTION,
136 EXYNOS5420_PAD_RET_MMCB_OPTION,
137 EXYNOS5420_PAD_RET_MMCC_OPTION,
138 EXYNOS5420_PAD_RET_HSI_OPTION,
139 EXYNOS_PAD_RET_EBIA_OPTION,
140 EXYNOS_PAD_RET_EBIB_OPTION,
141 EXYNOS5420_PAD_RET_SPI_OPTION,
142 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
146 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
148 const struct exynos_wkup_irq *wkup_irq;
150 if (!pm_data->wkup_irq)
152 wkup_irq = pm_data->wkup_irq;
154 while (wkup_irq->mask) {
155 if (wkup_irq->hwirq == data->hwirq) {
157 exynos_irqwake_intmask |= wkup_irq->mask;
159 exynos_irqwake_intmask &= ~wkup_irq->mask;
168 static struct irq_chip exynos_pmu_chip = {
170 .irq_eoi = irq_chip_eoi_parent,
171 .irq_mask = irq_chip_mask_parent,
172 .irq_unmask = irq_chip_unmask_parent,
173 .irq_retrigger = irq_chip_retrigger_hierarchy,
174 .irq_set_wake = exynos_irq_set_wake,
176 .irq_set_affinity = irq_chip_set_affinity_parent,
180 static int exynos_pmu_domain_translate(struct irq_domain *d,
181 struct irq_fwspec *fwspec,
182 unsigned long *hwirq,
185 if (is_of_node(fwspec->fwnode)) {
186 if (fwspec->param_count != 3)
189 /* No PPI should point to this domain */
190 if (fwspec->param[0] != 0)
193 *hwirq = fwspec->param[1];
194 *type = fwspec->param[2];
201 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
203 unsigned int nr_irqs, void *data)
205 struct irq_fwspec *fwspec = data;
206 struct irq_fwspec parent_fwspec;
207 irq_hw_number_t hwirq;
210 if (fwspec->param_count != 3)
211 return -EINVAL; /* Not GIC compliant */
212 if (fwspec->param[0] != 0)
213 return -EINVAL; /* No PPI should point to this domain */
215 hwirq = fwspec->param[1];
217 for (i = 0; i < nr_irqs; i++)
218 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
219 &exynos_pmu_chip, NULL);
221 parent_fwspec = *fwspec;
222 parent_fwspec.fwnode = domain->parent->fwnode;
223 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
227 static const struct irq_domain_ops exynos_pmu_domain_ops = {
228 .translate = exynos_pmu_domain_translate,
229 .alloc = exynos_pmu_domain_alloc,
230 .free = irq_domain_free_irqs_common,
233 static int __init exynos_pmu_irq_init(struct device_node *node,
234 struct device_node *parent)
236 struct irq_domain *parent_domain, *domain;
239 pr_err("%s: no parent, giving up\n", node->full_name);
243 parent_domain = irq_find_host(parent);
244 if (!parent_domain) {
245 pr_err("%s: unable to obtain parent domain\n", node->full_name);
249 pmu_base_addr = of_iomap(node, 0);
251 if (!pmu_base_addr) {
252 pr_err("%s: failed to find exynos pmu register\n",
257 domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
258 node, &exynos_pmu_domain_ops,
261 iounmap(pmu_base_addr);
268 #define EXYNOS_PMU_IRQ(symbol, name) OF_DECLARE_2(irqchip, symbol, name, exynos_pmu_irq_init)
270 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
271 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
272 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
273 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
274 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu");
275 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
276 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
278 static int exynos_cpu_do_idle(void)
280 /* issue the standby signal into the pm unit. */
283 pr_info("Failed to suspend the system\n");
284 return 1; /* Aborting suspend */
286 static void exynos_flush_cache_all(void)
292 static int exynos_cpu_suspend(unsigned long arg)
294 exynos_flush_cache_all();
295 return exynos_cpu_do_idle();
298 static int exynos3250_cpu_suspend(unsigned long arg)
301 return exynos_cpu_do_idle();
304 static int exynos5420_cpu_suspend(unsigned long arg)
306 /* MCPM works with HW CPU identifiers */
307 unsigned int mpidr = read_cpuid_mpidr();
308 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
309 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
311 __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
313 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
314 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
318 pr_info("Failed to suspend the system\n");
320 /* return value != 0 means failure */
324 static void exynos_pm_set_wakeup_mask(void)
326 /* Set wake-up mask registers */
327 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
328 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
331 static void exynos_pm_enter_sleep_mode(void)
333 /* Set value of power down register for sleep mode */
334 exynos_sys_powerdown_conf(SYS_SLEEP);
335 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
338 static void exynos_pm_prepare(void)
340 exynos_set_delayed_reset_assertion(false);
342 /* Set wake-up mask registers */
343 exynos_pm_set_wakeup_mask();
345 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
347 exynos_pm_enter_sleep_mode();
349 /* ensure at least INFORM0 has the resume address */
350 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
353 static void exynos3250_pm_prepare(void)
357 /* Set wake-up mask registers */
358 exynos_pm_set_wakeup_mask();
360 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
361 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
362 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
364 exynos_pm_enter_sleep_mode();
366 /* ensure at least INFORM0 has the resume address */
367 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
370 static void exynos5420_pm_prepare(void)
374 /* Set wake-up mask registers */
375 exynos_pm_set_wakeup_mask();
377 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
379 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
381 * The cpu state needs to be saved and restored so that the
382 * secondary CPUs will enter low power start. Though the U-Boot
383 * is setting the cpu state with low power flag, the kernel
384 * needs to restore it back in case, the primary cpu fails to
385 * suspend for any reason.
387 exynos5420_cpu_state = __raw_readl(sysram_base_addr +
388 EXYNOS5420_CPU_STATE);
390 exynos_pm_enter_sleep_mode();
392 /* ensure at least INFORM0 has the resume address */
393 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
394 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
396 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
397 tmp &= ~EXYNOS5_USE_RETENTION;
398 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
400 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
401 tmp |= EXYNOS5420_UFS;
402 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
404 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
405 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
406 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
408 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
409 tmp |= EXYNOS5420_EMULATION;
410 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
412 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
413 tmp |= EXYNOS5420_EMULATION;
414 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
418 static int exynos_pm_suspend(void)
420 exynos_pm_central_suspend();
422 /* Setting SEQ_OPTION register */
423 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
424 S5P_CENTRAL_SEQ_OPTION);
426 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
427 exynos_cpu_save_register();
432 static int exynos5420_pm_suspend(void)
436 exynos_pm_central_suspend();
438 /* Setting SEQ_OPTION register */
440 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
442 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
443 S5P_CENTRAL_SEQ_OPTION);
445 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
446 S5P_CENTRAL_SEQ_OPTION);
450 static void exynos_pm_release_retention(void)
454 for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
455 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
456 pm_data->release_ret_regs[i]);
459 static void exynos_pm_resume(void)
461 u32 cpuid = read_cpuid_part();
463 if (exynos_pm_central_resume())
466 /* For release retention */
467 exynos_pm_release_retention();
469 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
471 if (cpuid == ARM_CPU_PART_CORTEX_A9)
472 scu_enable(S5P_VA_SCU);
474 if (call_firmware_op(resume) == -ENOSYS
475 && cpuid == ARM_CPU_PART_CORTEX_A9)
476 exynos_cpu_restore_register();
480 /* Clear SLEEP mode set in INFORM1 */
481 pmu_raw_writel(0x0, S5P_INFORM1);
482 exynos_set_delayed_reset_assertion(true);
485 static void exynos3250_pm_resume(void)
487 u32 cpuid = read_cpuid_part();
489 if (exynos_pm_central_resume())
492 /* For release retention */
493 exynos_pm_release_retention();
495 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
497 if (call_firmware_op(resume) == -ENOSYS
498 && cpuid == ARM_CPU_PART_CORTEX_A9)
499 exynos_cpu_restore_register();
503 /* Clear SLEEP mode set in INFORM1 */
504 pmu_raw_writel(0x0, S5P_INFORM1);
507 static void exynos5420_prepare_pm_resume(void)
509 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
510 WARN_ON(mcpm_cpu_powered_up());
513 static void exynos5420_pm_resume(void)
517 /* Restore the CPU0 low power state register */
518 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
519 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
520 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
522 /* Restore the sysram cpu state register */
523 __raw_writel(exynos5420_cpu_state,
524 sysram_base_addr + EXYNOS5420_CPU_STATE);
526 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
527 S5P_CENTRAL_SEQ_OPTION);
529 if (exynos_pm_central_resume())
532 /* For release retention */
533 exynos_pm_release_retention();
535 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
537 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
541 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
542 tmp &= ~EXYNOS5420_UFS;
543 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
545 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
546 tmp &= ~EXYNOS5420_EMULATION;
547 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
549 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
550 tmp &= ~EXYNOS5420_EMULATION;
551 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
553 /* Clear SLEEP mode set in INFORM1 */
554 pmu_raw_writel(0x0, S5P_INFORM1);
561 static int exynos_suspend_enter(suspend_state_t state)
567 S3C_PMDBG("%s: suspending the system...\n", __func__);
569 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
570 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
572 if (exynos_irqwake_intmask == -1U
573 && exynos_get_eint_wake_mask() == -1U) {
574 pr_err("%s: No wake-up sources!\n", __func__);
575 pr_err("%s: Aborting sleep\n", __func__);
580 if (pm_data->pm_prepare)
581 pm_data->pm_prepare();
583 s3c_pm_check_store();
585 ret = call_firmware_op(suspend);
587 ret = cpu_suspend(0, pm_data->cpu_suspend);
591 if (pm_data->pm_resume_prepare)
592 pm_data->pm_resume_prepare();
593 s3c_pm_restore_uarts();
595 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
596 pmu_raw_readl(S5P_WAKEUP_STAT));
598 s3c_pm_check_restore();
600 S3C_PMDBG("%s: resuming the system...\n", __func__);
605 static int exynos_suspend_prepare(void)
610 * REVISIT: It would be better if struct platform_suspend_ops
611 * .prepare handler get the suspend_state_t as a parameter to
612 * avoid hard-coding the suspend to mem state. It's safe to do
613 * it now only because the suspend_valid_only_mem function is
614 * used as the .valid callback used to check if a given state
615 * is supported by the platform anyways.
617 ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
619 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
623 s3c_pm_check_prepare();
628 static void exynos_suspend_finish(void)
632 s3c_pm_check_cleanup();
634 ret = regulator_suspend_finish();
636 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
639 static const struct platform_suspend_ops exynos_suspend_ops = {
640 .enter = exynos_suspend_enter,
641 .prepare = exynos_suspend_prepare,
642 .finish = exynos_suspend_finish,
643 .valid = suspend_valid_only_mem,
646 static const struct exynos_pm_data exynos3250_pm_data = {
647 .wkup_irq = exynos3250_wkup_irq,
648 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
649 .release_ret_regs = exynos3250_release_ret_regs,
650 .pm_suspend = exynos_pm_suspend,
651 .pm_resume = exynos3250_pm_resume,
652 .pm_prepare = exynos3250_pm_prepare,
653 .cpu_suspend = exynos3250_cpu_suspend,
656 static const struct exynos_pm_data exynos4_pm_data = {
657 .wkup_irq = exynos4_wkup_irq,
658 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
659 .release_ret_regs = exynos_release_ret_regs,
660 .pm_suspend = exynos_pm_suspend,
661 .pm_resume = exynos_pm_resume,
662 .pm_prepare = exynos_pm_prepare,
663 .cpu_suspend = exynos_cpu_suspend,
666 static const struct exynos_pm_data exynos5250_pm_data = {
667 .wkup_irq = exynos5250_wkup_irq,
668 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
669 .release_ret_regs = exynos_release_ret_regs,
670 .pm_suspend = exynos_pm_suspend,
671 .pm_resume = exynos_pm_resume,
672 .pm_prepare = exynos_pm_prepare,
673 .cpu_suspend = exynos_cpu_suspend,
676 static const struct exynos_pm_data exynos5420_pm_data = {
677 .wkup_irq = exynos5250_wkup_irq,
678 .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
679 .release_ret_regs = exynos5420_release_ret_regs,
680 .pm_resume_prepare = exynos5420_prepare_pm_resume,
681 .pm_resume = exynos5420_pm_resume,
682 .pm_suspend = exynos5420_pm_suspend,
683 .pm_prepare = exynos5420_pm_prepare,
684 .cpu_suspend = exynos5420_cpu_suspend,
687 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
689 .compatible = "samsung,exynos3250-pmu",
690 .data = &exynos3250_pm_data,
692 .compatible = "samsung,exynos4210-pmu",
693 .data = &exynos4_pm_data,
695 .compatible = "samsung,exynos4212-pmu",
696 .data = &exynos4_pm_data,
698 .compatible = "samsung,exynos4412-pmu",
699 .data = &exynos4_pm_data,
701 .compatible = "samsung,exynos5250-pmu",
702 .data = &exynos5250_pm_data,
704 .compatible = "samsung,exynos5420-pmu",
705 .data = &exynos5420_pm_data,
710 static struct syscore_ops exynos_pm_syscore_ops;
712 void __init exynos_pm_init(void)
714 const struct of_device_id *match;
715 struct device_node *np;
718 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
720 pr_err("Failed to find PMU node\n");
724 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
725 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
729 pm_data = (const struct exynos_pm_data *) match->data;
731 /* All wakeup disable */
732 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
733 tmp |= pm_data->wake_disable_mask;
734 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
736 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
737 exynos_pm_syscore_ops.resume = pm_data->pm_resume;
739 register_syscore_ops(&exynos_pm_syscore_ops);
740 suspend_set_ops(&exynos_suspend_ops);