1 /* linux/arch/arm/mach-exynos4/platsmp.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
23 #include <linux/of_address.h>
25 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
27 #include <asm/smp_scu.h>
28 #include <asm/firmware.h>
35 extern void exynos4_secondary_startup(void);
37 static void __iomem *sysram_base_addr;
38 void __iomem *sysram_ns_base_addr;
40 static void __init exynos_smp_prepare_sysram(void)
42 struct device_node *node;
44 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
45 if (!of_device_is_available(node))
47 sysram_base_addr = of_iomap(node, 0);
51 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
52 if (!of_device_is_available(node))
54 sysram_ns_base_addr = of_iomap(node, 0);
59 static inline void __iomem *cpu_boot_reg_base(void)
61 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
63 return sysram_base_addr;
66 static inline void __iomem *cpu_boot_reg(int cpu)
68 void __iomem *boot_reg;
70 boot_reg = cpu_boot_reg_base();
72 return ERR_PTR(-ENODEV);
73 if (soc_is_exynos4412())
75 else if (soc_is_exynos5420())
81 * Write pen_release in a way that is guaranteed to be visible to all
82 * observers, irrespective of whether they're taking part in coherency
83 * or not. This is necessary for the hotplug code to work reliably.
85 static void write_pen_release(int val)
89 sync_cache_w(&pen_release);
92 static void __iomem *scu_base_addr(void)
94 return (void __iomem *)(S5P_VA_SCU);
97 static DEFINE_SPINLOCK(boot_lock);
99 static void exynos_secondary_init(unsigned int cpu)
102 * let the primary processor know we're out of the
103 * pen, then head off into the C entry point
105 write_pen_release(-1);
108 * Synchronise with the boot thread.
110 spin_lock(&boot_lock);
111 spin_unlock(&boot_lock);
114 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
116 unsigned long timeout;
117 unsigned long phys_cpu = cpu_logical_map(cpu);
121 * Set synchronisation state between this boot processor
122 * and the secondary one
124 spin_lock(&boot_lock);
127 * The secondary processor is waiting to be released from
128 * the holding pen - release it, then wait for it to flag
129 * that it has been released by resetting pen_release.
131 * Note that "pen_release" is the hardware CPU ID, whereas
132 * "cpu" is Linux's internal ID.
134 write_pen_release(phys_cpu);
136 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
137 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
138 S5P_ARM_CORE1_CONFIGURATION);
142 /* wait max 10 ms until cpu1 is on */
143 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
144 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
152 printk(KERN_ERR "cpu1 power enable failed");
153 spin_unlock(&boot_lock);
158 * Send the secondary CPU a soft interrupt, thereby causing
159 * the boot monitor to read the system wide flags register,
160 * and branch to the address found there.
163 timeout = jiffies + (1 * HZ);
164 while (time_before(jiffies, timeout)) {
165 unsigned long boot_addr;
169 boot_addr = virt_to_phys(exynos4_secondary_startup);
172 * Try to set boot address using firmware first
173 * and fall back to boot register if it fails.
175 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
176 if (ret && ret != -ENOSYS)
178 if (ret == -ENOSYS) {
179 void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
181 if (IS_ERR(boot_reg)) {
182 ret = PTR_ERR(boot_reg);
185 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
188 call_firmware_op(cpu_boot, phys_cpu);
190 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
192 if (pen_release == -1)
199 * now the secondary core is starting up let it run its
200 * calibrations, then wait for it to finish
203 spin_unlock(&boot_lock);
205 return pen_release != -1 ? ret : 0;
209 * Initialise the CPU possible map early - this describes the CPUs
210 * which may be present or become present in the system.
213 static void __init exynos_smp_init_cpus(void)
215 void __iomem *scu_base = scu_base_addr();
216 unsigned int i, ncores;
218 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
219 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
222 * CPU Nodes are passed thru DT and set_cpu_possible
223 * is set by "arm_dt_init_cpu_maps".
228 if (ncores > nr_cpu_ids) {
229 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
234 for (i = 0; i < ncores; i++)
235 set_cpu_possible(i, true);
238 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
242 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
243 scu_enable(scu_base_addr());
245 exynos_smp_prepare_sysram();
248 * Write the address of secondary startup into the
249 * system-wide flags register. The boot monitor waits
250 * until it receives a soft interrupt, and then the
251 * secondary CPU branches to this address.
253 * Try using firmware operation first and fall back to
254 * boot register if it fails.
256 for (i = 1; i < max_cpus; ++i) {
257 unsigned long phys_cpu;
258 unsigned long boot_addr;
261 phys_cpu = cpu_logical_map(i);
262 boot_addr = virt_to_phys(exynos4_secondary_startup);
264 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
265 if (ret && ret != -ENOSYS)
267 if (ret == -ENOSYS) {
268 void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
270 if (IS_ERR(boot_reg))
272 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
277 struct smp_operations exynos_smp_ops __initdata = {
278 .smp_init_cpus = exynos_smp_init_cpus,
279 .smp_prepare_cpus = exynos_smp_prepare_cpus,
280 .smp_secondary_init = exynos_secondary_init,
281 .smp_boot_secondary = exynos_boot_secondary,
282 #ifdef CONFIG_HOTPLUG_CPU
283 .cpu_die = exynos_cpu_die,