1 /* linux/arch/arm/mach-exynos/cpu.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/sched.h>
12 #include <linux/device.h>
14 #include <asm/mach/map.h>
15 #include <asm/mach/irq.h>
17 #include <asm/proc-fns.h>
18 #include <asm/hardware/cache-l2x0.h>
19 #include <asm/hardware/gic.h>
22 #include <plat/clock.h>
23 #include <plat/devs.h>
24 #include <plat/exynos4.h>
25 #include <plat/adc-core.h>
26 #include <plat/sdhci.h>
27 #include <plat/fb-core.h>
28 #include <plat/fimc-core.h>
29 #include <plat/iic-core.h>
30 #include <plat/reset.h>
31 #include <plat/tv-core.h>
33 #include <mach/regs-irq.h>
34 #include <mach/regs-pmu.h>
36 unsigned int gic_bank_offset __read_mostly;
38 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
39 unsigned int irq_start);
40 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
42 /* Initial IO mappings */
43 static struct map_desc exynos_iodesc[] __initdata = {
45 .virtual = (unsigned long)S5P_VA_SYSTIMER,
46 .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
50 .virtual = (unsigned long)S5P_VA_PMU,
51 .pfn = __phys_to_pfn(EXYNOS_PA_PMU),
55 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
56 .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
60 .virtual = (unsigned long)S5P_VA_GIC_CPU,
61 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
65 .virtual = (unsigned long)S5P_VA_GIC_DIST,
66 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
70 .virtual = (unsigned long)S3C_VA_UART,
71 .pfn = __phys_to_pfn(S3C_PA_UART),
77 static struct map_desc exynos4_iodesc[] __initdata = {
79 .virtual = (unsigned long)S5P_VA_CMU,
80 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
84 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
85 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
89 .virtual = (unsigned long)S5P_VA_L2CC,
90 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
94 .virtual = (unsigned long)S5P_VA_GPIO1,
95 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
99 .virtual = (unsigned long)S5P_VA_GPIO2,
100 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
104 .virtual = (unsigned long)S5P_VA_GPIO3,
105 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
109 .virtual = (unsigned long)S5P_VA_DMC0,
110 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
114 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
115 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
121 static struct map_desc exynos4_iodesc0[] __initdata = {
123 .virtual = (unsigned long)S5P_VA_SYSRAM,
124 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
130 static struct map_desc exynos4_iodesc1[] __initdata = {
132 .virtual = (unsigned long)S5P_VA_SYSRAM,
133 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
139 static void exynos_idle(void)
147 static void exynos4_sw_reset(void)
149 __raw_writel(0x1, S5P_SWRESET);
155 * register the standard cpu IO areas
157 void __init exynos4_map_io(void)
159 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
160 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
162 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
163 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
165 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
167 /* initialize device information early */
168 exynos4_default_sdhci0();
169 exynos4_default_sdhci1();
170 exynos4_default_sdhci2();
171 exynos4_default_sdhci3();
173 s3c_adc_setname("samsung-adc-v3");
175 s3c_fimc_setname(0, "exynos4-fimc");
176 s3c_fimc_setname(1, "exynos4-fimc");
177 s3c_fimc_setname(2, "exynos4-fimc");
178 s3c_fimc_setname(3, "exynos4-fimc");
180 /* The I2C bus controllers are directly compatible with s3c2440 */
181 s3c_i2c0_setname("s3c2440-i2c");
182 s3c_i2c1_setname("s3c2440-i2c");
183 s3c_i2c2_setname("s3c2440-i2c");
185 s5p_fb_setname(0, "exynos4-fb");
186 s5p_hdmi_setname("exynos4-hdmi");
189 void __init exynos4_init_clocks(int xtal)
191 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
193 s3c24xx_register_baseclocks(xtal);
194 s5p_register_clocks(xtal);
196 if (soc_is_exynos4210())
197 exynos4210_register_clocks();
198 else if (soc_is_exynos4212() || soc_is_exynos4412())
199 exynos4212_register_clocks();
201 exynos4_register_clocks();
202 exynos4_setup_clocks();
205 static void exynos4_gic_irq_fix_base(struct irq_data *d)
207 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
209 gic_data->cpu_base = S5P_VA_GIC_CPU +
210 (gic_bank_offset * smp_processor_id());
212 gic_data->dist_base = S5P_VA_GIC_DIST +
213 (gic_bank_offset * smp_processor_id());
216 void __init exynos4_init_irq(void)
220 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
222 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
223 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
224 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
225 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
227 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
229 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
230 COMBINER_IRQ(irq, 0));
231 combiner_cascade_irq(irq, IRQ_SPI(irq));
234 /* The parameters of s5p_init_irq() are for VIC init.
235 * Theses parameters should be NULL and 0 because EXYNOS4
236 * uses GIC instead of VIC.
238 s5p_init_irq(NULL, 0);
241 struct bus_type exynos4_subsys = {
242 .name = "exynos4-core",
243 .dev_name = "exynos4-core",
246 static struct device exynos4_dev = {
247 .bus = &exynos4_subsys,
250 static int __init exynos4_core_init(void)
252 return subsys_system_register(&exynos4_subsys, NULL);
254 core_initcall(exynos4_core_init);
256 #ifdef CONFIG_CACHE_L2X0
257 static int __init exynos4_l2x0_cache_init(void)
259 /* TAG, Data Latency Control: 2cycle */
260 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
262 if (soc_is_exynos4210())
263 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
264 else if (soc_is_exynos4212() || soc_is_exynos4412())
265 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
267 /* L2X0 Prefetch Control */
268 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
270 /* L2X0 Power Control */
271 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
272 S5P_VA_L2CC + L2X0_POWER_CTRL);
274 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
279 early_initcall(exynos4_l2x0_cache_init);
282 int __init exynos_init(void)
284 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
286 /* set idle function */
287 pm_idle = exynos_idle;
289 /* set sw_reset function */
290 if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
291 s5p_reset_hook = exynos4_sw_reset;
293 return device_register(&exynos4_dev);