arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/of_address.h>
  27 #include <linux/clocksource.h>
  28 #include <linux/clk-provider.h>
  29 #include <linux/irqchip/arm-gic.h>
  30 #include <linux/irqchip/chained_irq.h>
  31
  32 #include <asm/proc-fns.h>
  33 #include <asm/exception.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <mach/regs-irq.h>
  40 #include <mach/regs-pmu.h>
  41 #include <mach/regs-gpio.h>
  42 #include <mach/irqs.h>
  43
  44 #include <plat/cpu.h>
  45 #include <plat/devs.h>
  46 #include <plat/pm.h>
  47 #include <plat/sdhci.h>
  48 #include <plat/gpio-cfg.h>
  49 #include <plat/adc-core.h>
  50 #include <plat/fb-core.h>
  51 #include <plat/fimc-core.h>
  52 #include <plat/iic-core.h>
  53 #include <plat/tv-core.h>
  54 #include <plat/spi-core.h>
  55 #include <plat/regs-serial.h>
  56
  57 #include "common.h"
  58 #define L2_AUX_VAL 0x7C470001
  59 #define L2_AUX_MASK 0xC200ffff
  60
  61 static const char name_exynos4210[] = "EXYNOS4210";
  62 static const char name_exynos4212[] = "EXYNOS4212";
  63 static const char name_exynos4412[] = "EXYNOS4412";
  64 static const char name_exynos5250[] = "EXYNOS5250";
  65 static const char name_exynos5440[] = "EXYNOS5440";
  66
  67 static void exynos4_map_io(void);
  68 static void exynos5_map_io(void);
  69 static void exynos5440_map_io(void);
  70 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  71 static int exynos_init(void);
  72
  73 unsigned long xxti_f = 0, xusbxti_f = 0;
  74
  75 static struct cpu_table cpu_ids[] __initdata = {
  76         {
  77                 .idcode         = EXYNOS4210_CPU_ID,
  78                 .idmask         = EXYNOS4_CPU_MASK,
  79                 .map_io         = exynos4_map_io,
  80                 .init_uarts     = exynos4_init_uarts,
  81                 .init           = exynos_init,
  82                 .name           = name_exynos4210,
  83         }, {
  84                 .idcode         = EXYNOS4212_CPU_ID,
  85                 .idmask         = EXYNOS4_CPU_MASK,
  86                 .map_io         = exynos4_map_io,
  87                 .init_uarts     = exynos4_init_uarts,
  88                 .init           = exynos_init,
  89                 .name           = name_exynos4212,
  90         }, {
  91                 .idcode         = EXYNOS4412_CPU_ID,
  92                 .idmask         = EXYNOS4_CPU_MASK,
  93                 .map_io         = exynos4_map_io,
  94                 .init_uarts     = exynos4_init_uarts,
  95                 .init           = exynos_init,
  96                 .name           = name_exynos4412,
  97         }, {
  98                 .idcode         = EXYNOS5250_SOC_ID,
  99                 .idmask         = EXYNOS5_SOC_MASK,
 100                 .map_io         = exynos5_map_io,
 101                 .init           = exynos_init,
 102                 .name           = name_exynos5250,
 103         }, {
 104                 .idcode         = EXYNOS5440_SOC_ID,
 105                 .idmask         = EXYNOS5_SOC_MASK,
 106                 .map_io         = exynos5440_map_io,
 107                 .init           = exynos_init,
 108                 .name           = name_exynos5440,
 109         },
 110 };
 111
 112 /* Initial IO mappings */
 113
 114 static struct map_desc exynos_iodesc[] __initdata = {
 115         {
 116                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 117                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 118                 .length         = SZ_4K,
 119                 .type           = MT_DEVICE,
 120         },
 121 };
 122
 123 static struct map_desc exynos4_iodesc[] __initdata = {
 124         {
 125                 .virtual        = (unsigned long)S3C_VA_SYS,
 126                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 127                 .length         = SZ_64K,
 128                 .type           = MT_DEVICE,
 129         }, {
 130                 .virtual        = (unsigned long)S3C_VA_TIMER,
 131                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 132                 .length         = SZ_16K,
 133                 .type           = MT_DEVICE,
 134         }, {
 135                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 136                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 137                 .length         = SZ_4K,
 138                 .type           = MT_DEVICE,
 139         }, {
 140                 .virtual        = (unsigned long)S5P_VA_SROMC,
 141                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 142                 .length         = SZ_4K,
 143                 .type           = MT_DEVICE,
 144         }, {
 145                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 146                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 147                 .length         = SZ_4K,
 148                 .type           = MT_DEVICE,
 149         }, {
 150                 .virtual        = (unsigned long)S5P_VA_PMU,
 151                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 152                 .length         = SZ_64K,
 153                 .type           = MT_DEVICE,
 154         }, {
 155                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 156                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 157                 .length         = SZ_4K,
 158                 .type           = MT_DEVICE,
 159         }, {
 160                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 161                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 162                 .length         = SZ_64K,
 163                 .type           = MT_DEVICE,
 164         }, {
 165                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 166                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 167                 .length         = SZ_64K,
 168                 .type           = MT_DEVICE,
 169         }, {
 170                 .virtual        = (unsigned long)S3C_VA_UART,
 171                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 172                 .length         = SZ_512K,
 173                 .type           = MT_DEVICE,
 174         }, {
 175                 .virtual        = (unsigned long)S5P_VA_CMU,
 176                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 177                 .length         = SZ_128K,
 178                 .type           = MT_DEVICE,
 179         }, {
 180                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 181                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 182                 .length         = SZ_8K,
 183                 .type           = MT_DEVICE,
 184         }, {
 185                 .virtual        = (unsigned long)S5P_VA_L2CC,
 186                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 187                 .length         = SZ_4K,
 188                 .type           = MT_DEVICE,
 189         }, {
 190                 .virtual        = (unsigned long)S5P_VA_DMC0,
 191                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 192                 .length         = SZ_64K,
 193                 .type           = MT_DEVICE,
 194         }, {
 195                 .virtual        = (unsigned long)S5P_VA_DMC1,
 196                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 197                 .length         = SZ_64K,
 198                 .type           = MT_DEVICE,
 199         }, {
 200                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 201                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 202                 .length         = SZ_4K,
 203                 .type           = MT_DEVICE,
 204         },
 205 };
 206
 207 static struct map_desc exynos4_iodesc0[] __initdata = {
 208         {
 209                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 210                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 211                 .length         = SZ_4K,
 212                 .type           = MT_DEVICE,
 213         },
 214 };
 215
 216 static struct map_desc exynos4_iodesc1[] __initdata = {
 217         {
 218                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 219                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 220                 .length         = SZ_4K,
 221                 .type           = MT_DEVICE,
 222         },
 223 };
 224
 225 static struct map_desc exynos4210_iodesc[] __initdata = {
 226         {
 227                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 228                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 229                 .length         = SZ_4K,
 230                 .type           = MT_DEVICE,
 231         },
 232 };
 233
 234 static struct map_desc exynos4x12_iodesc[] __initdata = {
 235         {
 236                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 237                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 238                 .length         = SZ_4K,
 239                 .type           = MT_DEVICE,
 240         },
 241 };
 242
 243 static struct map_desc exynos5250_iodesc[] __initdata = {
 244         {
 245                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 246                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 247                 .length         = SZ_4K,
 248                 .type           = MT_DEVICE,
 249         },
 250 };
 251
 252 static struct map_desc exynos5_iodesc[] __initdata = {
 253         {
 254                 .virtual        = (unsigned long)S3C_VA_SYS,
 255                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 256                 .length         = SZ_64K,
 257                 .type           = MT_DEVICE,
 258         }, {
 259                 .virtual        = (unsigned long)S3C_VA_TIMER,
 260                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 261                 .length         = SZ_16K,
 262                 .type           = MT_DEVICE,
 263         }, {
 264                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 265                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 266                 .length         = SZ_4K,
 267                 .type           = MT_DEVICE,
 268         }, {
 269                 .virtual        = (unsigned long)S5P_VA_SROMC,
 270                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 271                 .length         = SZ_4K,
 272                 .type           = MT_DEVICE,
 273         }, {
 274                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 275                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 276                 .length         = SZ_4K,
 277                 .type           = MT_DEVICE,
 278         }, {
 279                 .virtual        = (unsigned long)S5P_VA_CMU,
 280                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 281                 .length         = 144 * SZ_1K,
 282                 .type           = MT_DEVICE,
 283         }, {
 284                 .virtual        = (unsigned long)S5P_VA_PMU,
 285                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 286                 .length         = SZ_64K,
 287                 .type           = MT_DEVICE,
 288         }, {
 289                 .virtual        = (unsigned long)S3C_VA_UART,
 290                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 291                 .length         = SZ_512K,
 292                 .type           = MT_DEVICE,
 293         },
 294 };
 295
 296 static struct map_desc exynos5440_iodesc0[] __initdata = {
 297         {
 298                 .virtual        = (unsigned long)S3C_VA_UART,
 299                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 300                 .length         = SZ_512K,
 301                 .type           = MT_DEVICE,
 302         },
 303 };
 304
 305 void exynos4_restart(char mode, const char *cmd)
 306 {
 307         __raw_writel(0x1, S5P_SWRESET);
 308 }
 309
 310 void exynos5_restart(char mode, const char *cmd)
 311 {
 312         struct device_node *np;
 313         u32 val;
 314         void __iomem *addr;
 315
 316         if (of_machine_is_compatible("samsung,exynos5250")) {
 317                 val = 0x1;
 318                 addr = EXYNOS_SWRESET;
 319         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 320                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 321                 addr = of_iomap(np, 0) + 0xcc;
 322                 val = (0xfff << 20) | (0x1 << 16);
 323         } else {
 324                 pr_err("%s: cannot support non-DT\n", __func__);
 325                 return;
 326         }
 327
 328         __raw_writel(val, addr);
 329 }
 330
 331 void __init exynos_init_late(void)
 332 {
 333         if (of_machine_is_compatible("samsung,exynos5440"))
 334                 /* to be supported later */
 335                 return;
 336
 337         exynos_pm_late_initcall();
 338 }
 339
 340 #ifdef CONFIG_OF
 341 int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 342                                         int depth, void *data)
 343 {
 344         struct map_desc iodesc;
 345         __be32 *reg;
 346         unsigned long len;
 347
 348         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 349                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 350                 return 0;
 351
 352         reg = of_get_flat_dt_prop(node, "reg", &len);
 353         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 354                 return 0;
 355
 356         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 357         iodesc.length = be32_to_cpu(reg[1]) - 1;
 358         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 359         iodesc.type = MT_DEVICE;
 360         iotable_init(&iodesc, 1);
 361         return 1;
 362 }
 363 #endif
 364
 365 /*
 366  * exynos_map_io
 367  *
 368  * register the standard cpu IO areas
 369  */
 370
 371 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 372 {
 373 #ifdef CONFIG_OF
 374         if (initial_boot_params)
 375                 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 376         else
 377 #endif
 378                 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 379
 380         if (mach_desc)
 381                 iotable_init(mach_desc, size);
 382
 383         /* detect cpu id and rev. */
 384         s5p_init_cpu(S5P_VA_CHIPID);
 385
 386         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 387 }
 388
 389 static void __init exynos4_map_io(void)
 390 {
 391         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 392
 393         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 394                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 395         else
 396                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 397
 398         if (soc_is_exynos4210())
 399                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 400         if (soc_is_exynos4212() || soc_is_exynos4412())
 401                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 402
 403         /* initialize device information early */
 404         exynos4_default_sdhci0();
 405         exynos4_default_sdhci1();
 406         exynos4_default_sdhci2();
 407         exynos4_default_sdhci3();
 408
 409         s3c_adc_setname("samsung-adc-v3");
 410
 411         s3c_fimc_setname(0, "exynos4-fimc");
 412         s3c_fimc_setname(1, "exynos4-fimc");
 413         s3c_fimc_setname(2, "exynos4-fimc");
 414         s3c_fimc_setname(3, "exynos4-fimc");
 415
 416         s3c_sdhci_setname(0, "exynos4-sdhci");
 417         s3c_sdhci_setname(1, "exynos4-sdhci");
 418         s3c_sdhci_setname(2, "exynos4-sdhci");
 419         s3c_sdhci_setname(3, "exynos4-sdhci");
 420
 421         /* The I2C bus controllers are directly compatible with s3c2440 */
 422         s3c_i2c0_setname("s3c2440-i2c");
 423         s3c_i2c1_setname("s3c2440-i2c");
 424         s3c_i2c2_setname("s3c2440-i2c");
 425
 426         s5p_fb_setname(0, "exynos4-fb");
 427         s5p_hdmi_setname("exynos4-hdmi");
 428
 429         s3c64xx_spi_setname("exynos4210-spi");
 430 }
 431
 432 static void __init exynos5_map_io(void)
 433 {
 434         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 435
 436         if (soc_is_exynos5250())
 437                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 438 }
 439
 440 static void __init exynos5440_map_io(void)
 441 {
 442         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 443 }
 444
 445 void __init exynos_init_time(void)
 446 {
 447         if (of_have_populated_dt()) {
 448 #ifdef CONFIG_OF
 449                 of_clk_init(NULL);
 450                 clocksource_of_init();
 451 #endif
 452         } else {
 453                 /* todo: remove after migrating legacy E4 platforms to dt */
 454 #ifdef CONFIG_ARCH_EXYNOS4
 455                 exynos4_clk_init(NULL);
 456                 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 457 #endif
 458                 mct_init();
 459         }
 460 }
 461
 462 void __init exynos4_init_irq(void)
 463 {
 464         unsigned int gic_bank_offset;
 465
 466         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 467
 468         if (!of_have_populated_dt())
 469                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 470 #ifdef CONFIG_OF
 471         else
 472                 irqchip_init();
 473 #endif
 474
 475         if (!of_have_populated_dt())
 476                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 477
 478         /*
 479          * The parameters of s5p_init_irq() are for VIC init.
 480          * Theses parameters should be NULL and 0 because EXYNOS4
 481          * uses GIC instead of VIC.
 482          */
 483         s5p_init_irq(NULL, 0);
 484
 485         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 486 }
 487
 488 void __init exynos5_init_irq(void)
 489 {
 490 #ifdef CONFIG_OF
 491         irqchip_init();
 492 #endif
 493         /*
 494          * The parameters of s5p_init_irq() are for VIC init.
 495          * Theses parameters should be NULL and 0 because EXYNOS4
 496          * uses GIC instead of VIC.
 497          */
 498         if (!of_machine_is_compatible("samsung,exynos5440"))
 499                 s5p_init_irq(NULL, 0);
 500
 501         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 502 }
 503
 504 struct bus_type exynos_subsys = {
 505         .name           = "exynos-core",
 506         .dev_name       = "exynos-core",
 507 };
 508
 509 static struct device exynos4_dev = {
 510         .bus    = &exynos_subsys,
 511 };
 512
 513 static int __init exynos_core_init(void)
 514 {
 515         return subsys_system_register(&exynos_subsys, NULL);
 516 }
 517 core_initcall(exynos_core_init);
 518
 519 #ifdef CONFIG_CACHE_L2X0
 520 static int __init exynos4_l2x0_cache_init(void)
 521 {
 522         int ret;
 523
 524         if (soc_is_exynos5250() || soc_is_exynos5440())
 525                 return 0;
 526
 527         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 528         if (!ret) {
 529                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 530                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 531                 return 0;
 532         }
 533
 534         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 535                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 536                 /* TAG, Data Latency Control: 2 cycles */
 537                 l2x0_saved_regs.tag_latency = 0x110;
 538
 539                 if (soc_is_exynos4212() || soc_is_exynos4412())
 540                         l2x0_saved_regs.data_latency = 0x120;
 541                 else
 542                         l2x0_saved_regs.data_latency = 0x110;
 543
 544                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 545                 l2x0_saved_regs.pwr_ctrl =
 546                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 547
 548                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 549
 550                 __raw_writel(l2x0_saved_regs.tag_latency,
 551                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 552                 __raw_writel(l2x0_saved_regs.data_latency,
 553                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 554
 555                 /* L2X0 Prefetch Control */
 556                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 557                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 558
 559                 /* L2X0 Power Control */
 560                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 561                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 562
 563                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 564                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 565         }
 566
 567         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 568         return 0;
 569 }
 570 early_initcall(exynos4_l2x0_cache_init);
 571 #endif
 572
 573 static int __init exynos_init(void)
 574 {
 575         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 576
 577         return device_register(&exynos4_dev);
 578 }
 579
 580 /* uart registration process */
 581
 582 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 583 {
 584         struct s3c2410_uartcfg *tcfg = cfg;
 585         u32 ucnt;
 586
 587         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 588                 tcfg->has_fracval = 1;
 589
 590         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 591 }
 592
 593 static void __iomem *exynos_eint_base;
 594
 595 static DEFINE_SPINLOCK(eint_lock);
 596
 597 static unsigned int eint0_15_data[16];
 598
 599 static inline int exynos4_irq_to_gpio(unsigned int irq)
 600 {
 601         if (irq < IRQ_EINT(0))
 602                 return -EINVAL;
 603
 604         irq -= IRQ_EINT(0);
 605         if (irq < 8)
 606                 return EXYNOS4_GPX0(irq);
 607
 608         irq -= 8;
 609         if (irq < 8)
 610                 return EXYNOS4_GPX1(irq);
 611
 612         irq -= 8;
 613         if (irq < 8)
 614                 return EXYNOS4_GPX2(irq);
 615
 616         irq -= 8;
 617         if (irq < 8)
 618                 return EXYNOS4_GPX3(irq);
 619
 620         return -EINVAL;
 621 }
 622
 623 static inline int exynos5_irq_to_gpio(unsigned int irq)
 624 {
 625         if (irq < IRQ_EINT(0))
 626                 return -EINVAL;
 627
 628         irq -= IRQ_EINT(0);
 629         if (irq < 8)
 630                 return EXYNOS5_GPX0(irq);
 631
 632         irq -= 8;
 633         if (irq < 8)
 634                 return EXYNOS5_GPX1(irq);
 635
 636         irq -= 8;
 637         if (irq < 8)
 638                 return EXYNOS5_GPX2(irq);
 639
 640         irq -= 8;
 641         if (irq < 8)
 642                 return EXYNOS5_GPX3(irq);
 643
 644         return -EINVAL;
 645 }
 646
 647 static unsigned int exynos4_eint0_15_src_int[16] = {
 648         EXYNOS4_IRQ_EINT0,
 649         EXYNOS4_IRQ_EINT1,
 650         EXYNOS4_IRQ_EINT2,
 651         EXYNOS4_IRQ_EINT3,
 652         EXYNOS4_IRQ_EINT4,
 653         EXYNOS4_IRQ_EINT5,
 654         EXYNOS4_IRQ_EINT6,
 655         EXYNOS4_IRQ_EINT7,
 656         EXYNOS4_IRQ_EINT8,
 657         EXYNOS4_IRQ_EINT9,
 658         EXYNOS4_IRQ_EINT10,
 659         EXYNOS4_IRQ_EINT11,
 660         EXYNOS4_IRQ_EINT12,
 661         EXYNOS4_IRQ_EINT13,
 662         EXYNOS4_IRQ_EINT14,
 663         EXYNOS4_IRQ_EINT15,
 664 };
 665
 666 static unsigned int exynos5_eint0_15_src_int[16] = {
 667         EXYNOS5_IRQ_EINT0,
 668         EXYNOS5_IRQ_EINT1,
 669         EXYNOS5_IRQ_EINT2,
 670         EXYNOS5_IRQ_EINT3,
 671         EXYNOS5_IRQ_EINT4,
 672         EXYNOS5_IRQ_EINT5,
 673         EXYNOS5_IRQ_EINT6,
 674         EXYNOS5_IRQ_EINT7,
 675         EXYNOS5_IRQ_EINT8,
 676         EXYNOS5_IRQ_EINT9,
 677         EXYNOS5_IRQ_EINT10,
 678         EXYNOS5_IRQ_EINT11,
 679         EXYNOS5_IRQ_EINT12,
 680         EXYNOS5_IRQ_EINT13,
 681         EXYNOS5_IRQ_EINT14,
 682         EXYNOS5_IRQ_EINT15,
 683 };
 684 static inline void exynos_irq_eint_mask(struct irq_data *data)
 685 {
 686         u32 mask;
 687
 688         spin_lock(&eint_lock);
 689         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 690         mask |= EINT_OFFSET_BIT(data->irq);
 691         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 692         spin_unlock(&eint_lock);
 693 }
 694
 695 static void exynos_irq_eint_unmask(struct irq_data *data)
 696 {
 697         u32 mask;
 698
 699         spin_lock(&eint_lock);
 700         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 701         mask &= ~(EINT_OFFSET_BIT(data->irq));
 702         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 703         spin_unlock(&eint_lock);
 704 }
 705
 706 static inline void exynos_irq_eint_ack(struct irq_data *data)
 707 {
 708         __raw_writel(EINT_OFFSET_BIT(data->irq),
 709                      EINT_PEND(exynos_eint_base, data->irq));
 710 }
 711
 712 static void exynos_irq_eint_maskack(struct irq_data *data)
 713 {
 714         exynos_irq_eint_mask(data);
 715         exynos_irq_eint_ack(data);
 716 }
 717
 718 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 719 {
 720         int offs = EINT_OFFSET(data->irq);
 721         int shift;
 722         u32 ctrl, mask;
 723         u32 newvalue = 0;
 724
 725         switch (type) {
 726         case IRQ_TYPE_EDGE_RISING:
 727                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 728                 break;
 729
 730         case IRQ_TYPE_EDGE_FALLING:
 731                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 732                 break;
 733
 734         case IRQ_TYPE_EDGE_BOTH:
 735                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 736                 break;
 737
 738         case IRQ_TYPE_LEVEL_LOW:
 739                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 740                 break;
 741
 742         case IRQ_TYPE_LEVEL_HIGH:
 743                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 744                 break;
 745
 746         default:
 747                 printk(KERN_ERR "No such irq type %d", type);
 748                 return -EINVAL;
 749         }
 750
 751         shift = (offs & 0x7) * 4;
 752         mask = 0x7 << shift;
 753
 754         spin_lock(&eint_lock);
 755         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 756         ctrl &= ~mask;
 757         ctrl |= newvalue << shift;
 758         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 759         spin_unlock(&eint_lock);
 760
 761         if (soc_is_exynos5250())
 762                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 763         else
 764                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 765
 766         return 0;
 767 }
 768
 769 static struct irq_chip exynos_irq_eint = {
 770         .name           = "exynos-eint",
 771         .irq_mask       = exynos_irq_eint_mask,
 772         .irq_unmask     = exynos_irq_eint_unmask,
 773         .irq_mask_ack   = exynos_irq_eint_maskack,
 774         .irq_ack        = exynos_irq_eint_ack,
 775         .irq_set_type   = exynos_irq_eint_set_type,
 776 #ifdef CONFIG_PM
 777         .irq_set_wake   = s3c_irqext_wake,
 778 #endif
 779 };
 780
 781 /*
 782  * exynos4_irq_demux_eint
 783  *
 784  * This function demuxes the IRQ from from EINTs 16 to 31.
 785  * It is designed to be inlined into the specific handler
 786  * s5p_irq_demux_eintX_Y.
 787  *
 788  * Each EINT pend/mask registers handle eight of them.
 789  */
 790 static inline void exynos_irq_demux_eint(unsigned int start)
 791 {
 792         unsigned int irq;
 793
 794         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 795         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 796
 797         status &= ~mask;
 798         status &= 0xff;
 799
 800         while (status) {
 801                 irq = fls(status) - 1;
 802                 generic_handle_irq(irq + start);
 803                 status &= ~(1 << irq);
 804         }
 805 }
 806
 807 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 808 {
 809         struct irq_chip *chip = irq_get_chip(irq);
 810         chained_irq_enter(chip, desc);
 811         exynos_irq_demux_eint(IRQ_EINT(16));
 812         exynos_irq_demux_eint(IRQ_EINT(24));
 813         chained_irq_exit(chip, desc);
 814 }
 815
 816 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 817 {
 818         u32 *irq_data = irq_get_handler_data(irq);
 819         struct irq_chip *chip = irq_get_chip(irq);
 820
 821         chained_irq_enter(chip, desc);
 822         generic_handle_irq(*irq_data);
 823         chained_irq_exit(chip, desc);
 824 }
 825
 826 static int __init exynos_init_irq_eint(void)
 827 {
 828         int irq;
 829
 830 #ifdef CONFIG_PINCTRL_SAMSUNG
 831         /*
 832          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 833          * functionality along with support for external gpio and wakeup
 834          * interrupts. If the samsung pinctrl driver is enabled and includes
 835          * the wakeup interrupt support, then the setting up external wakeup
 836          * interrupts here can be skipped. This check here is temporary to
 837          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 838          * co-exist with platforms that do. When all of the Samsung Exynos4
 839          * platforms switch over to using the pinctrl driver, the wakeup
 840          * interrupt support code here can be completely removed.
 841          */
 842         static const struct of_device_id exynos_pinctrl_ids[] = {
 843                 { .compatible = "samsung,exynos4210-pinctrl", },
 844                 { .compatible = "samsung,exynos4x12-pinctrl", },
 845                 { .compatible = "samsung,exynos5250-pinctrl", },
 846         };
 847         struct device_node *pctrl_np, *wkup_np;
 848         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 849
 850         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 851                 if (of_device_is_available(pctrl_np)) {
 852                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 853                                                         wkup_compat);
 854                         if (wkup_np)
 855                                 return -ENODEV;
 856                 }
 857         }
 858 #endif
 859         if (soc_is_exynos5440())
 860                 return 0;
 861
 862         if (soc_is_exynos5250())
 863                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 864         else
 865                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 866
 867         if (exynos_eint_base == NULL) {
 868                 pr_err("unable to ioremap for EINT base address\n");
 869                 return -ENOMEM;
 870         }
 871
 872         for (irq = 0 ; irq <= 31 ; irq++) {
 873                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 874                                          handle_level_irq);
 875                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 876         }
 877
 878         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 879
 880         for (irq = 0 ; irq <= 15 ; irq++) {
 881                 eint0_15_data[irq] = IRQ_EINT(irq);
 882
 883                 if (soc_is_exynos5250()) {
 884                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 885                                              &eint0_15_data[irq]);
 886                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 887                                                 exynos_irq_eint0_15);
 888                 } else {
 889                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 890                                              &eint0_15_data[irq]);
 891                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 892                                                 exynos_irq_eint0_15);
 893                 }
 894         }
 895
 896         return 0;
 897 }
 898 arch_initcall(exynos_init_irq_eint);
 899
 900 static struct resource exynos4_pmu_resource[] = {
 901         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
 902         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
 903 #if defined(CONFIG_SOC_EXYNOS4412)
 904         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
 905         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
 906 #endif
 907 };
 908
 909 static struct platform_device exynos4_device_pmu = {
 910         .name           = "arm-pmu",
 911         .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
 912         .resource       = exynos4_pmu_resource,
 913 };
 914
 915 static int __init exynos_armpmu_init(void)
 916 {
 917         if (!of_have_populated_dt()) {
 918                 if (soc_is_exynos4210() || soc_is_exynos4212())
 919                         exynos4_device_pmu.num_resources = 2;
 920                 platform_device_register(&exynos4_device_pmu);
 921         }
 922
 923         return 0;
 924 }
 925 arch_initcall(exynos_armpmu_init);