arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/of_address.h>
  27 #include <linux/clocksource.h>
  28 #include <linux/clk-provider.h>
  29 #include <linux/irqchip/arm-gic.h>
  30 #include <linux/irqchip/chained_irq.h>
  31
  32 #include <asm/proc-fns.h>
  33 #include <asm/exception.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <mach/regs-irq.h>
  40 #include <mach/regs-pmu.h>
  41 #include <mach/regs-gpio.h>
  42 #include <mach/irqs.h>
  43
  44 #include <plat/cpu.h>
  45 #include <plat/devs.h>
  46 #include <plat/pm.h>
  47 #include <plat/sdhci.h>
  48 #include <plat/gpio-cfg.h>
  49 #include <plat/adc-core.h>
  50 #include <plat/fb-core.h>
  51 #include <plat/fimc-core.h>
  52 #include <plat/iic-core.h>
  53 #include <plat/tv-core.h>
  54 #include <plat/spi-core.h>
  55 #include <plat/regs-serial.h>
  56
  57 #include "common.h"
  58 #define L2_AUX_VAL 0x7C470001
  59 #define L2_AUX_MASK 0xC200ffff
  60
  61 static const char name_exynos4210[] = "EXYNOS4210";
  62 static const char name_exynos4212[] = "EXYNOS4212";
  63 static const char name_exynos4412[] = "EXYNOS4412";
  64 static const char name_exynos5250[] = "EXYNOS5250";
  65 static const char name_exynos5440[] = "EXYNOS5440";
  66
  67 static void exynos4_map_io(void);
  68 static void exynos5_map_io(void);
  69 static void exynos5440_map_io(void);
  70 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  71 static int exynos_init(void);
  72
  73 unsigned long xxti_f = 0, xusbxti_f = 0;
  74
  75 static struct cpu_table cpu_ids[] __initdata = {
  76         {
  77                 .idcode         = EXYNOS4210_CPU_ID,
  78                 .idmask         = EXYNOS4_CPU_MASK,
  79                 .map_io         = exynos4_map_io,
  80                 .init_uarts     = exynos4_init_uarts,
  81                 .init           = exynos_init,
  82                 .name           = name_exynos4210,
  83         }, {
  84                 .idcode         = EXYNOS4212_CPU_ID,
  85                 .idmask         = EXYNOS4_CPU_MASK,
  86                 .map_io         = exynos4_map_io,
  87                 .init_uarts     = exynos4_init_uarts,
  88                 .init           = exynos_init,
  89                 .name           = name_exynos4212,
  90         }, {
  91                 .idcode         = EXYNOS4412_CPU_ID,
  92                 .idmask         = EXYNOS4_CPU_MASK,
  93                 .map_io         = exynos4_map_io,
  94                 .init_uarts     = exynos4_init_uarts,
  95                 .init           = exynos_init,
  96                 .name           = name_exynos4412,
  97         }, {
  98                 .idcode         = EXYNOS5250_SOC_ID,
  99                 .idmask         = EXYNOS5_SOC_MASK,
 100                 .map_io         = exynos5_map_io,
 101                 .init           = exynos_init,
 102                 .name           = name_exynos5250,
 103         }, {
 104                 .idcode         = EXYNOS5440_SOC_ID,
 105                 .idmask         = EXYNOS5_SOC_MASK,
 106                 .map_io         = exynos5440_map_io,
 107                 .init           = exynos_init,
 108                 .name           = name_exynos5440,
 109         },
 110 };
 111
 112 /* Initial IO mappings */
 113
 114 static struct map_desc exynos_iodesc[] __initdata = {
 115         {
 116                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 117                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 118                 .length         = SZ_4K,
 119                 .type           = MT_DEVICE,
 120         },
 121 };
 122
 123 #ifdef CONFIG_ARCH_EXYNOS5
 124 static struct map_desc exynos5440_iodesc[] __initdata = {
 125         {
 126                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 127                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 128                 .length         = SZ_4K,
 129                 .type           = MT_DEVICE,
 130         },
 131 };
 132 #endif
 133
 134 static struct map_desc exynos4_iodesc[] __initdata = {
 135         {
 136                 .virtual        = (unsigned long)S3C_VA_SYS,
 137                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 138                 .length         = SZ_64K,
 139                 .type           = MT_DEVICE,
 140         }, {
 141                 .virtual        = (unsigned long)S3C_VA_TIMER,
 142                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 143                 .length         = SZ_16K,
 144                 .type           = MT_DEVICE,
 145         }, {
 146                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 147                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 148                 .length         = SZ_4K,
 149                 .type           = MT_DEVICE,
 150         }, {
 151                 .virtual        = (unsigned long)S5P_VA_SROMC,
 152                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 153                 .length         = SZ_4K,
 154                 .type           = MT_DEVICE,
 155         }, {
 156                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 157                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 158                 .length         = SZ_4K,
 159                 .type           = MT_DEVICE,
 160         }, {
 161                 .virtual        = (unsigned long)S5P_VA_PMU,
 162                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 163                 .length         = SZ_64K,
 164                 .type           = MT_DEVICE,
 165         }, {
 166                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 167                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 168                 .length         = SZ_4K,
 169                 .type           = MT_DEVICE,
 170         }, {
 171                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 172                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 173                 .length         = SZ_64K,
 174                 .type           = MT_DEVICE,
 175         }, {
 176                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 177                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 178                 .length         = SZ_64K,
 179                 .type           = MT_DEVICE,
 180         }, {
 181                 .virtual        = (unsigned long)S3C_VA_UART,
 182                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 183                 .length         = SZ_512K,
 184                 .type           = MT_DEVICE,
 185         }, {
 186                 .virtual        = (unsigned long)S5P_VA_CMU,
 187                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 188                 .length         = SZ_128K,
 189                 .type           = MT_DEVICE,
 190         }, {
 191                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 192                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 193                 .length         = SZ_8K,
 194                 .type           = MT_DEVICE,
 195         }, {
 196                 .virtual        = (unsigned long)S5P_VA_L2CC,
 197                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 198                 .length         = SZ_4K,
 199                 .type           = MT_DEVICE,
 200         }, {
 201                 .virtual        = (unsigned long)S5P_VA_DMC0,
 202                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 203                 .length         = SZ_64K,
 204                 .type           = MT_DEVICE,
 205         }, {
 206                 .virtual        = (unsigned long)S5P_VA_DMC1,
 207                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 208                 .length         = SZ_64K,
 209                 .type           = MT_DEVICE,
 210         }, {
 211                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 212                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 213                 .length         = SZ_4K,
 214                 .type           = MT_DEVICE,
 215         },
 216 };
 217
 218 static struct map_desc exynos4_iodesc0[] __initdata = {
 219         {
 220                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 221                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 222                 .length         = SZ_4K,
 223                 .type           = MT_DEVICE,
 224         },
 225 };
 226
 227 static struct map_desc exynos4_iodesc1[] __initdata = {
 228         {
 229                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 230                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 231                 .length         = SZ_4K,
 232                 .type           = MT_DEVICE,
 233         },
 234 };
 235
 236 static struct map_desc exynos5_iodesc[] __initdata = {
 237         {
 238                 .virtual        = (unsigned long)S3C_VA_SYS,
 239                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 240                 .length         = SZ_64K,
 241                 .type           = MT_DEVICE,
 242         }, {
 243                 .virtual        = (unsigned long)S3C_VA_TIMER,
 244                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 245                 .length         = SZ_16K,
 246                 .type           = MT_DEVICE,
 247         }, {
 248                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 249                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 250                 .length         = SZ_4K,
 251                 .type           = MT_DEVICE,
 252         }, {
 253                 .virtual        = (unsigned long)S5P_VA_SROMC,
 254                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 255                 .length         = SZ_4K,
 256                 .type           = MT_DEVICE,
 257         }, {
 258                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 259                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 260                 .length         = SZ_4K,
 261                 .type           = MT_DEVICE,
 262         }, {
 263                 .virtual        = (unsigned long)S5P_VA_CMU,
 264                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 265                 .length         = 144 * SZ_1K,
 266                 .type           = MT_DEVICE,
 267         }, {
 268                 .virtual        = (unsigned long)S5P_VA_PMU,
 269                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 270                 .length         = SZ_64K,
 271                 .type           = MT_DEVICE,
 272         }, {
 273                 .virtual        = (unsigned long)S3C_VA_UART,
 274                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 275                 .length         = SZ_512K,
 276                 .type           = MT_DEVICE,
 277         },
 278 };
 279
 280 static struct map_desc exynos5440_iodesc0[] __initdata = {
 281         {
 282                 .virtual        = (unsigned long)S3C_VA_UART,
 283                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 284                 .length         = SZ_512K,
 285                 .type           = MT_DEVICE,
 286         },
 287 };
 288
 289 void exynos4_restart(char mode, const char *cmd)
 290 {
 291         __raw_writel(0x1, S5P_SWRESET);
 292 }
 293
 294 void exynos5_restart(char mode, const char *cmd)
 295 {
 296         struct device_node *np;
 297         u32 val;
 298         void __iomem *addr;
 299
 300         if (of_machine_is_compatible("samsung,exynos5250")) {
 301                 val = 0x1;
 302                 addr = EXYNOS_SWRESET;
 303         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 304                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 305                 addr = of_iomap(np, 0) + 0xcc;
 306                 val = (0xfff << 20) | (0x1 << 16);
 307         } else {
 308                 pr_err("%s: cannot support non-DT\n", __func__);
 309                 return;
 310         }
 311
 312         __raw_writel(val, addr);
 313 }
 314
 315 void __init exynos_init_late(void)
 316 {
 317         if (of_machine_is_compatible("samsung,exynos5440"))
 318                 /* to be supported later */
 319                 return;
 320
 321         exynos_pm_late_initcall();
 322 }
 323
 324 /*
 325  * exynos_map_io
 326  *
 327  * register the standard cpu IO areas
 328  */
 329
 330 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 331 {
 332         struct map_desc *iodesc = exynos_iodesc;
 333         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 334 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 335         unsigned long root = of_get_flat_dt_root();
 336
 337         /* initialize the io descriptors we need for initialization */
 338         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 339                 iodesc = exynos5440_iodesc;
 340                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 341         }
 342 #endif
 343
 344         iotable_init(iodesc, iodesc_sz);
 345
 346         if (mach_desc)
 347                 iotable_init(mach_desc, size);
 348
 349         /* detect cpu id and rev. */
 350         s5p_init_cpu(S5P_VA_CHIPID);
 351
 352         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 353 }
 354
 355 static void __init exynos4_map_io(void)
 356 {
 357         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 358
 359         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 360                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 361         else
 362                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 363
 364         /* initialize device information early */
 365         exynos4_default_sdhci0();
 366         exynos4_default_sdhci1();
 367         exynos4_default_sdhci2();
 368         exynos4_default_sdhci3();
 369
 370         s3c_adc_setname("samsung-adc-v3");
 371
 372         s3c_fimc_setname(0, "exynos4-fimc");
 373         s3c_fimc_setname(1, "exynos4-fimc");
 374         s3c_fimc_setname(2, "exynos4-fimc");
 375         s3c_fimc_setname(3, "exynos4-fimc");
 376
 377         s3c_sdhci_setname(0, "exynos4-sdhci");
 378         s3c_sdhci_setname(1, "exynos4-sdhci");
 379         s3c_sdhci_setname(2, "exynos4-sdhci");
 380         s3c_sdhci_setname(3, "exynos4-sdhci");
 381
 382         /* The I2C bus controllers are directly compatible with s3c2440 */
 383         s3c_i2c0_setname("s3c2440-i2c");
 384         s3c_i2c1_setname("s3c2440-i2c");
 385         s3c_i2c2_setname("s3c2440-i2c");
 386
 387         s5p_fb_setname(0, "exynos4-fb");
 388         s5p_hdmi_setname("exynos4-hdmi");
 389
 390         s3c64xx_spi_setname("exynos4210-spi");
 391 }
 392
 393 static void __init exynos5_map_io(void)
 394 {
 395         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 396 }
 397
 398 static void __init exynos5440_map_io(void)
 399 {
 400         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 401 }
 402
 403 void __init exynos_init_time(void)
 404 {
 405         if (of_have_populated_dt()) {
 406 #ifdef CONFIG_OF
 407                 of_clk_init(NULL);
 408                 clocksource_of_init();
 409 #endif
 410         } else {
 411                 /* todo: remove after migrating legacy E4 platforms to dt */
 412 #ifdef CONFIG_ARCH_EXYNOS4
 413                 exynos4_clk_init(NULL);
 414                 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 415 #endif
 416                 mct_init();
 417         }
 418 }
 419
 420 void __init exynos4_init_irq(void)
 421 {
 422         unsigned int gic_bank_offset;
 423
 424         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 425
 426         if (!of_have_populated_dt())
 427                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 428 #ifdef CONFIG_OF
 429         else
 430                 irqchip_init();
 431 #endif
 432
 433         if (!of_have_populated_dt())
 434                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 435
 436         /*
 437          * The parameters of s5p_init_irq() are for VIC init.
 438          * Theses parameters should be NULL and 0 because EXYNOS4
 439          * uses GIC instead of VIC.
 440          */
 441         s5p_init_irq(NULL, 0);
 442
 443         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 444 }
 445
 446 void __init exynos5_init_irq(void)
 447 {
 448 #ifdef CONFIG_OF
 449         irqchip_init();
 450 #endif
 451         /*
 452          * The parameters of s5p_init_irq() are for VIC init.
 453          * Theses parameters should be NULL and 0 because EXYNOS4
 454          * uses GIC instead of VIC.
 455          */
 456         if (!of_machine_is_compatible("samsung,exynos5440"))
 457                 s5p_init_irq(NULL, 0);
 458
 459         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 460 }
 461
 462 struct bus_type exynos_subsys = {
 463         .name           = "exynos-core",
 464         .dev_name       = "exynos-core",
 465 };
 466
 467 static struct device exynos4_dev = {
 468         .bus    = &exynos_subsys,
 469 };
 470
 471 static int __init exynos_core_init(void)
 472 {
 473         return subsys_system_register(&exynos_subsys, NULL);
 474 }
 475 core_initcall(exynos_core_init);
 476
 477 #ifdef CONFIG_CACHE_L2X0
 478 static int __init exynos4_l2x0_cache_init(void)
 479 {
 480         int ret;
 481
 482         if (soc_is_exynos5250() || soc_is_exynos5440())
 483                 return 0;
 484
 485         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 486         if (!ret) {
 487                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 488                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 489                 return 0;
 490         }
 491
 492         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 493                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 494                 /* TAG, Data Latency Control: 2 cycles */
 495                 l2x0_saved_regs.tag_latency = 0x110;
 496
 497                 if (soc_is_exynos4212() || soc_is_exynos4412())
 498                         l2x0_saved_regs.data_latency = 0x120;
 499                 else
 500                         l2x0_saved_regs.data_latency = 0x110;
 501
 502                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 503                 l2x0_saved_regs.pwr_ctrl =
 504                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 505
 506                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 507
 508                 __raw_writel(l2x0_saved_regs.tag_latency,
 509                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 510                 __raw_writel(l2x0_saved_regs.data_latency,
 511                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 512
 513                 /* L2X0 Prefetch Control */
 514                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 515                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 516
 517                 /* L2X0 Power Control */
 518                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 519                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 520
 521                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 522                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 523         }
 524
 525         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 526         return 0;
 527 }
 528 early_initcall(exynos4_l2x0_cache_init);
 529 #endif
 530
 531 static int __init exynos_init(void)
 532 {
 533         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 534
 535         return device_register(&exynos4_dev);
 536 }
 537
 538 /* uart registration process */
 539
 540 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 541 {
 542         struct s3c2410_uartcfg *tcfg = cfg;
 543         u32 ucnt;
 544
 545         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 546                 tcfg->has_fracval = 1;
 547
 548         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 549 }
 550
 551 static void __iomem *exynos_eint_base;
 552
 553 static DEFINE_SPINLOCK(eint_lock);
 554
 555 static unsigned int eint0_15_data[16];
 556
 557 static inline int exynos4_irq_to_gpio(unsigned int irq)
 558 {
 559         if (irq < IRQ_EINT(0))
 560                 return -EINVAL;
 561
 562         irq -= IRQ_EINT(0);
 563         if (irq < 8)
 564                 return EXYNOS4_GPX0(irq);
 565
 566         irq -= 8;
 567         if (irq < 8)
 568                 return EXYNOS4_GPX1(irq);
 569
 570         irq -= 8;
 571         if (irq < 8)
 572                 return EXYNOS4_GPX2(irq);
 573
 574         irq -= 8;
 575         if (irq < 8)
 576                 return EXYNOS4_GPX3(irq);
 577
 578         return -EINVAL;
 579 }
 580
 581 static inline int exynos5_irq_to_gpio(unsigned int irq)
 582 {
 583         if (irq < IRQ_EINT(0))
 584                 return -EINVAL;
 585
 586         irq -= IRQ_EINT(0);
 587         if (irq < 8)
 588                 return EXYNOS5_GPX0(irq);
 589
 590         irq -= 8;
 591         if (irq < 8)
 592                 return EXYNOS5_GPX1(irq);
 593
 594         irq -= 8;
 595         if (irq < 8)
 596                 return EXYNOS5_GPX2(irq);
 597
 598         irq -= 8;
 599         if (irq < 8)
 600                 return EXYNOS5_GPX3(irq);
 601
 602         return -EINVAL;
 603 }
 604
 605 static unsigned int exynos4_eint0_15_src_int[16] = {
 606         EXYNOS4_IRQ_EINT0,
 607         EXYNOS4_IRQ_EINT1,
 608         EXYNOS4_IRQ_EINT2,
 609         EXYNOS4_IRQ_EINT3,
 610         EXYNOS4_IRQ_EINT4,
 611         EXYNOS4_IRQ_EINT5,
 612         EXYNOS4_IRQ_EINT6,
 613         EXYNOS4_IRQ_EINT7,
 614         EXYNOS4_IRQ_EINT8,
 615         EXYNOS4_IRQ_EINT9,
 616         EXYNOS4_IRQ_EINT10,
 617         EXYNOS4_IRQ_EINT11,
 618         EXYNOS4_IRQ_EINT12,
 619         EXYNOS4_IRQ_EINT13,
 620         EXYNOS4_IRQ_EINT14,
 621         EXYNOS4_IRQ_EINT15,
 622 };
 623
 624 static unsigned int exynos5_eint0_15_src_int[16] = {
 625         EXYNOS5_IRQ_EINT0,
 626         EXYNOS5_IRQ_EINT1,
 627         EXYNOS5_IRQ_EINT2,
 628         EXYNOS5_IRQ_EINT3,
 629         EXYNOS5_IRQ_EINT4,
 630         EXYNOS5_IRQ_EINT5,
 631         EXYNOS5_IRQ_EINT6,
 632         EXYNOS5_IRQ_EINT7,
 633         EXYNOS5_IRQ_EINT8,
 634         EXYNOS5_IRQ_EINT9,
 635         EXYNOS5_IRQ_EINT10,
 636         EXYNOS5_IRQ_EINT11,
 637         EXYNOS5_IRQ_EINT12,
 638         EXYNOS5_IRQ_EINT13,
 639         EXYNOS5_IRQ_EINT14,
 640         EXYNOS5_IRQ_EINT15,
 641 };
 642 static inline void exynos_irq_eint_mask(struct irq_data *data)
 643 {
 644         u32 mask;
 645
 646         spin_lock(&eint_lock);
 647         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 648         mask |= EINT_OFFSET_BIT(data->irq);
 649         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 650         spin_unlock(&eint_lock);
 651 }
 652
 653 static void exynos_irq_eint_unmask(struct irq_data *data)
 654 {
 655         u32 mask;
 656
 657         spin_lock(&eint_lock);
 658         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 659         mask &= ~(EINT_OFFSET_BIT(data->irq));
 660         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 661         spin_unlock(&eint_lock);
 662 }
 663
 664 static inline void exynos_irq_eint_ack(struct irq_data *data)
 665 {
 666         __raw_writel(EINT_OFFSET_BIT(data->irq),
 667                      EINT_PEND(exynos_eint_base, data->irq));
 668 }
 669
 670 static void exynos_irq_eint_maskack(struct irq_data *data)
 671 {
 672         exynos_irq_eint_mask(data);
 673         exynos_irq_eint_ack(data);
 674 }
 675
 676 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 677 {
 678         int offs = EINT_OFFSET(data->irq);
 679         int shift;
 680         u32 ctrl, mask;
 681         u32 newvalue = 0;
 682
 683         switch (type) {
 684         case IRQ_TYPE_EDGE_RISING:
 685                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 686                 break;
 687
 688         case IRQ_TYPE_EDGE_FALLING:
 689                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 690                 break;
 691
 692         case IRQ_TYPE_EDGE_BOTH:
 693                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 694                 break;
 695
 696         case IRQ_TYPE_LEVEL_LOW:
 697                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 698                 break;
 699
 700         case IRQ_TYPE_LEVEL_HIGH:
 701                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 702                 break;
 703
 704         default:
 705                 printk(KERN_ERR "No such irq type %d", type);
 706                 return -EINVAL;
 707         }
 708
 709         shift = (offs & 0x7) * 4;
 710         mask = 0x7 << shift;
 711
 712         spin_lock(&eint_lock);
 713         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 714         ctrl &= ~mask;
 715         ctrl |= newvalue << shift;
 716         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 717         spin_unlock(&eint_lock);
 718
 719         if (soc_is_exynos5250())
 720                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 721         else
 722                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 723
 724         return 0;
 725 }
 726
 727 static struct irq_chip exynos_irq_eint = {
 728         .name           = "exynos-eint",
 729         .irq_mask       = exynos_irq_eint_mask,
 730         .irq_unmask     = exynos_irq_eint_unmask,
 731         .irq_mask_ack   = exynos_irq_eint_maskack,
 732         .irq_ack        = exynos_irq_eint_ack,
 733         .irq_set_type   = exynos_irq_eint_set_type,
 734 #ifdef CONFIG_PM
 735         .irq_set_wake   = s3c_irqext_wake,
 736 #endif
 737 };
 738
 739 /*
 740  * exynos4_irq_demux_eint
 741  *
 742  * This function demuxes the IRQ from from EINTs 16 to 31.
 743  * It is designed to be inlined into the specific handler
 744  * s5p_irq_demux_eintX_Y.
 745  *
 746  * Each EINT pend/mask registers handle eight of them.
 747  */
 748 static inline void exynos_irq_demux_eint(unsigned int start)
 749 {
 750         unsigned int irq;
 751
 752         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 753         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 754
 755         status &= ~mask;
 756         status &= 0xff;
 757
 758         while (status) {
 759                 irq = fls(status) - 1;
 760                 generic_handle_irq(irq + start);
 761                 status &= ~(1 << irq);
 762         }
 763 }
 764
 765 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 766 {
 767         struct irq_chip *chip = irq_get_chip(irq);
 768         chained_irq_enter(chip, desc);
 769         exynos_irq_demux_eint(IRQ_EINT(16));
 770         exynos_irq_demux_eint(IRQ_EINT(24));
 771         chained_irq_exit(chip, desc);
 772 }
 773
 774 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 775 {
 776         u32 *irq_data = irq_get_handler_data(irq);
 777         struct irq_chip *chip = irq_get_chip(irq);
 778
 779         chained_irq_enter(chip, desc);
 780         generic_handle_irq(*irq_data);
 781         chained_irq_exit(chip, desc);
 782 }
 783
 784 static int __init exynos_init_irq_eint(void)
 785 {
 786         int irq;
 787
 788 #ifdef CONFIG_PINCTRL_SAMSUNG
 789         /*
 790          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 791          * functionality along with support for external gpio and wakeup
 792          * interrupts. If the samsung pinctrl driver is enabled and includes
 793          * the wakeup interrupt support, then the setting up external wakeup
 794          * interrupts here can be skipped. This check here is temporary to
 795          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 796          * co-exist with platforms that do. When all of the Samsung Exynos4
 797          * platforms switch over to using the pinctrl driver, the wakeup
 798          * interrupt support code here can be completely removed.
 799          */
 800         static const struct of_device_id exynos_pinctrl_ids[] = {
 801                 { .compatible = "samsung,exynos4210-pinctrl", },
 802                 { .compatible = "samsung,exynos4x12-pinctrl", },
 803                 { .compatible = "samsung,exynos5250-pinctrl", },
 804         };
 805         struct device_node *pctrl_np, *wkup_np;
 806         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 807
 808         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 809                 if (of_device_is_available(pctrl_np)) {
 810                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 811                                                         wkup_compat);
 812                         if (wkup_np)
 813                                 return -ENODEV;
 814                 }
 815         }
 816 #endif
 817         if (soc_is_exynos5440())
 818                 return 0;
 819
 820         if (soc_is_exynos5250())
 821                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 822         else
 823                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 824
 825         if (exynos_eint_base == NULL) {
 826                 pr_err("unable to ioremap for EINT base address\n");
 827                 return -ENOMEM;
 828         }
 829
 830         for (irq = 0 ; irq <= 31 ; irq++) {
 831                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 832                                          handle_level_irq);
 833                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 834         }
 835
 836         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 837
 838         for (irq = 0 ; irq <= 15 ; irq++) {
 839                 eint0_15_data[irq] = IRQ_EINT(irq);
 840
 841                 if (soc_is_exynos5250()) {
 842                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 843                                              &eint0_15_data[irq]);
 844                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 845                                                 exynos_irq_eint0_15);
 846                 } else {
 847                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 848                                              &eint0_15_data[irq]);
 849                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 850                                                 exynos_irq_eint0_15);
 851                 }
 852         }
 853
 854         return 0;
 855 }
 856 arch_initcall(exynos_init_irq_eint);
 857
 858 static struct resource exynos4_pmu_resource[] = {
 859         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
 860         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
 861 #if defined(CONFIG_SOC_EXYNOS4412)
 862         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
 863         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
 864 #endif
 865 };
 866
 867 static struct platform_device exynos4_device_pmu = {
 868         .name           = "arm-pmu",
 869         .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
 870         .resource       = exynos4_pmu_resource,
 871 };
 872
 873 static int __init exynos_armpmu_init(void)
 874 {
 875         if (!of_have_populated_dt()) {
 876                 if (soc_is_exynos4210() || soc_is_exynos4212())
 877                         exynos4_device_pmu.num_resources = 2;
 878                 platform_device_register(&exynos4_device_pmu);
 879         }
 880
 881         return 0;
 882 }
 883 arch_initcall(exynos_armpmu_init);