arch/arm/mach-exynos/clock-exynos5.c

   1 /*
   2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Clock support for EXYNOS5 SoCs
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30
  31 #ifdef CONFIG_PM_SLEEP
  32 static struct sleep_save exynos5_clock_save[] = {
  33         /* will be implemented */
  34 };
  35 #endif
  36
  37 static struct clk exynos5_clk_sclk_dptxphy = {
  38         .name           = "sclk_dptx",
  39 };
  40
  41 static struct clk exynos5_clk_sclk_hdmi24m = {
  42         .name           = "sclk_hdmi24m",
  43         .rate           = 24000000,
  44 };
  45
  46 static struct clk exynos5_clk_sclk_hdmi27m = {
  47         .name           = "sclk_hdmi27m",
  48         .rate           = 27000000,
  49 };
  50
  51 static struct clk exynos5_clk_sclk_hdmiphy = {
  52         .name           = "sclk_hdmiphy",
  53 };
  54
  55 static struct clk exynos5_clk_sclk_usbphy = {
  56         .name           = "sclk_usbphy",
  57         .rate           = 48000000,
  58 };
  59
  60 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
  61 {
  62         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
  63 }
  64
  65 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
  66 {
  67         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
  68 }
  69
  70 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
  71 {
  72         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
  73 }
  74
  75 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
  76 {
  77         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
  78 }
  79
  80 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
  81 {
  82         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
  83 }
  84
  85 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
  86 {
  87         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
  88 }
  89
  90 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
  91 {
  92         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
  93 }
  94
  95 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
  96 {
  97         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
  98 }
  99
 100 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 101 {
 102         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
 103 }
 104
 105 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
 106 {
 107         return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
 108 }
 109
 110 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
 111 {
 112         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 113 }
 114
 115 static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
 116 {
 117         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
 118 }
 119
 120 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 121 {
 122         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
 123 }
 124
 125 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
 126 {
 127         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
 128 }
 129
 130 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 131 {
 132         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 133 }
 134
 135 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
 136 {
 137         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
 138 }
 139
 140 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
 141 {
 142         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
 143 }
 144
 145 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
 146 {
 147         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 148 }
 149
 150 /* Core list of CMU_CPU side */
 151
 152 static struct clksrc_clk exynos5_clk_mout_apll = {
 153         .clk    = {
 154                 .name           = "mout_apll",
 155         },
 156         .sources = &clk_src_apll,
 157         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
 158 };
 159
 160 static struct clksrc_clk exynos5_clk_sclk_apll = {
 161         .clk    = {
 162                 .name           = "sclk_apll",
 163                 .parent         = &exynos5_clk_mout_apll.clk,
 164         },
 165         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 166 };
 167
 168 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
 169         .clk    = {
 170                 .name           = "mout_bpll_fout",
 171         },
 172         .sources = &clk_src_bpll_fout,
 173         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
 174 };
 175
 176 static struct clk *exynos5_clk_src_bpll_list[] = {
 177         [0] = &clk_fin_bpll,
 178         [1] = &exynos5_clk_mout_bpll_fout.clk,
 179 };
 180
 181 static struct clksrc_sources exynos5_clk_src_bpll = {
 182         .sources        = exynos5_clk_src_bpll_list,
 183         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
 184 };
 185
 186 static struct clksrc_clk exynos5_clk_mout_bpll = {
 187         .clk    = {
 188                 .name           = "mout_bpll",
 189         },
 190         .sources = &exynos5_clk_src_bpll,
 191         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 192 };
 193
 194 static struct clk *exynos5_clk_src_bpll_user_list[] = {
 195         [0] = &clk_fin_mpll,
 196         [1] = &exynos5_clk_mout_bpll.clk,
 197 };
 198
 199 static struct clksrc_sources exynos5_clk_src_bpll_user = {
 200         .sources        = exynos5_clk_src_bpll_user_list,
 201         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
 202 };
 203
 204 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
 205         .clk    = {
 206                 .name           = "mout_bpll_user",
 207         },
 208         .sources = &exynos5_clk_src_bpll_user,
 209         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
 210 };
 211
 212 static struct clksrc_clk exynos5_clk_mout_cpll = {
 213         .clk    = {
 214                 .name           = "mout_cpll",
 215         },
 216         .sources = &clk_src_cpll,
 217         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
 218 };
 219
 220 static struct clksrc_clk exynos5_clk_mout_epll = {
 221         .clk    = {
 222                 .name           = "mout_epll",
 223         },
 224         .sources = &clk_src_epll,
 225         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 226 };
 227
 228 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
 229         .clk    = {
 230                 .name           = "mout_mpll_fout",
 231         },
 232         .sources = &clk_src_mpll_fout,
 233         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
 234 };
 235
 236 static struct clk *exynos5_clk_src_mpll_list[] = {
 237         [0] = &clk_fin_mpll,
 238         [1] = &exynos5_clk_mout_mpll_fout.clk,
 239 };
 240
 241 static struct clksrc_sources exynos5_clk_src_mpll = {
 242         .sources        = exynos5_clk_src_mpll_list,
 243         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
 244 };
 245
 246 struct clksrc_clk exynos5_clk_mout_mpll = {
 247         .clk = {
 248                 .name           = "mout_mpll",
 249         },
 250         .sources = &exynos5_clk_src_mpll,
 251         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 252 };
 253
 254 static struct clk *exynos_clkset_vpllsrc_list[] = {
 255         [0] = &clk_fin_vpll,
 256         [1] = &exynos5_clk_sclk_hdmi27m,
 257 };
 258
 259 static struct clksrc_sources exynos5_clkset_vpllsrc = {
 260         .sources        = exynos_clkset_vpllsrc_list,
 261         .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
 262 };
 263
 264 static struct clksrc_clk exynos5_clk_vpllsrc = {
 265         .clk    = {
 266                 .name           = "vpll_src",
 267                 .enable         = exynos5_clksrc_mask_top_ctrl,
 268                 .ctrlbit        = (1 << 0),
 269         },
 270         .sources = &exynos5_clkset_vpllsrc,
 271         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
 272 };
 273
 274 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
 275         [0] = &exynos5_clk_vpllsrc.clk,
 276         [1] = &clk_fout_vpll,
 277 };
 278
 279 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
 280         .sources        = exynos5_clkset_sclk_vpll_list,
 281         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
 282 };
 283
 284 static struct clksrc_clk exynos5_clk_sclk_vpll = {
 285         .clk    = {
 286                 .name           = "sclk_vpll",
 287         },
 288         .sources = &exynos5_clkset_sclk_vpll,
 289         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
 290 };
 291
 292 static struct clksrc_clk exynos5_clk_sclk_pixel = {
 293         .clk    = {
 294                 .name           = "sclk_pixel",
 295                 .parent         = &exynos5_clk_sclk_vpll.clk,
 296         },
 297         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
 298 };
 299
 300 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
 301         [0] = &exynos5_clk_sclk_pixel.clk,
 302         [1] = &exynos5_clk_sclk_hdmiphy,
 303 };
 304
 305 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
 306         .sources        = exynos5_clkset_sclk_hdmi_list,
 307         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
 308 };
 309
 310 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
 311         .clk    = {
 312                 .name           = "sclk_hdmi",
 313                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 314                 .ctrlbit        = (1 << 20),
 315         },
 316         .sources = &exynos5_clkset_sclk_hdmi,
 317         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
 318 };
 319
 320 static struct clksrc_clk *exynos5_sclk_tv[] = {
 321         &exynos5_clk_sclk_pixel,
 322         &exynos5_clk_sclk_hdmi,
 323 };
 324
 325 static struct clk *exynos5_clk_src_mpll_user_list[] = {
 326         [0] = &clk_fin_mpll,
 327         [1] = &exynos5_clk_mout_mpll.clk,
 328 };
 329
 330 static struct clksrc_sources exynos5_clk_src_mpll_user = {
 331         .sources        = exynos5_clk_src_mpll_user_list,
 332         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
 333 };
 334
 335 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
 336         .clk    = {
 337                 .name           = "mout_mpll_user",
 338         },
 339         .sources = &exynos5_clk_src_mpll_user,
 340         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
 341 };
 342
 343 static struct clk *exynos5_clkset_mout_cpu_list[] = {
 344         [0] = &exynos5_clk_mout_apll.clk,
 345         [1] = &exynos5_clk_mout_mpll.clk,
 346 };
 347
 348 static struct clksrc_sources exynos5_clkset_mout_cpu = {
 349         .sources        = exynos5_clkset_mout_cpu_list,
 350         .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
 351 };
 352
 353 static struct clksrc_clk exynos5_clk_mout_cpu = {
 354         .clk    = {
 355                 .name           = "mout_cpu",
 356         },
 357         .sources = &exynos5_clkset_mout_cpu,
 358         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
 359 };
 360
 361 static struct clksrc_clk exynos5_clk_dout_armclk = {
 362         .clk    = {
 363                 .name           = "dout_armclk",
 364                 .parent         = &exynos5_clk_mout_cpu.clk,
 365         },
 366         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
 367 };
 368
 369 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
 370         .clk    = {
 371                 .name           = "dout_arm2clk",
 372                 .parent         = &exynos5_clk_dout_armclk.clk,
 373         },
 374         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
 375 };
 376
 377 static struct clk exynos5_clk_armclk = {
 378         .name           = "armclk",
 379         .parent         = &exynos5_clk_dout_arm2clk.clk,
 380 };
 381
 382 /* Core list of CMU_CDREX side */
 383
 384 static struct clk *exynos5_clkset_cdrex_list[] = {
 385         [0] = &exynos5_clk_mout_mpll.clk,
 386         [1] = &exynos5_clk_mout_bpll.clk,
 387 };
 388
 389 static struct clksrc_sources exynos5_clkset_cdrex = {
 390         .sources        = exynos5_clkset_cdrex_list,
 391         .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
 392 };
 393
 394 static struct clksrc_clk exynos5_clk_cdrex = {
 395         .clk    = {
 396                 .name           = "clk_cdrex",
 397         },
 398         .sources = &exynos5_clkset_cdrex,
 399         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
 400         .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
 401 };
 402
 403 static struct clksrc_clk exynos5_clk_aclk_acp = {
 404         .clk    = {
 405                 .name           = "aclk_acp",
 406                 .parent         = &exynos5_clk_mout_mpll.clk,
 407         },
 408         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
 409 };
 410
 411 static struct clksrc_clk exynos5_clk_pclk_acp = {
 412         .clk    = {
 413                 .name           = "pclk_acp",
 414                 .parent         = &exynos5_clk_aclk_acp.clk,
 415         },
 416         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
 417 };
 418
 419 /* Core list of CMU_TOP side */
 420
 421 struct clk *exynos5_clkset_aclk_top_list[] = {
 422         [0] = &exynos5_clk_mout_mpll_user.clk,
 423         [1] = &exynos5_clk_mout_bpll_user.clk,
 424 };
 425
 426 struct clksrc_sources exynos5_clkset_aclk = {
 427         .sources        = exynos5_clkset_aclk_top_list,
 428         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
 429 };
 430
 431 static struct clksrc_clk exynos5_clk_aclk_400 = {
 432         .clk    = {
 433                 .name           = "aclk_400",
 434         },
 435         .sources = &exynos5_clkset_aclk,
 436         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
 437         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
 438 };
 439
 440 struct clk *exynos5_clkset_aclk_333_166_list[] = {
 441         [0] = &exynos5_clk_mout_cpll.clk,
 442         [1] = &exynos5_clk_mout_mpll_user.clk,
 443 };
 444
 445 struct clksrc_sources exynos5_clkset_aclk_333_166 = {
 446         .sources        = exynos5_clkset_aclk_333_166_list,
 447         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
 448 };
 449
 450 static struct clksrc_clk exynos5_clk_aclk_333 = {
 451         .clk    = {
 452                 .name           = "aclk_333",
 453         },
 454         .sources = &exynos5_clkset_aclk_333_166,
 455         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
 456         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
 457 };
 458
 459 static struct clksrc_clk exynos5_clk_aclk_166 = {
 460         .clk    = {
 461                 .name           = "aclk_166",
 462         },
 463         .sources = &exynos5_clkset_aclk_333_166,
 464         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
 465         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
 466 };
 467
 468 static struct clksrc_clk exynos5_clk_aclk_266 = {
 469         .clk    = {
 470                 .name           = "aclk_266",
 471                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 472         },
 473         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
 474 };
 475
 476 static struct clksrc_clk exynos5_clk_aclk_200 = {
 477         .clk    = {
 478                 .name           = "aclk_200",
 479         },
 480         .sources = &exynos5_clkset_aclk,
 481         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
 482         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
 483 };
 484
 485 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
 486         .clk    = {
 487                 .name           = "aclk_66_pre",
 488                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 489         },
 490         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
 491 };
 492
 493 static struct clksrc_clk exynos5_clk_aclk_66 = {
 494         .clk    = {
 495                 .name           = "aclk_66",
 496                 .parent         = &exynos5_clk_aclk_66_pre.clk,
 497         },
 498         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 499 };
 500
 501 static struct clk exynos5_init_clocks_off[] = {
 502         {
 503                 .name           = "timers",
 504                 .parent         = &exynos5_clk_aclk_66.clk,
 505                 .enable         = exynos5_clk_ip_peric_ctrl,
 506                 .ctrlbit        = (1 << 24),
 507         }, {
 508                 .name           = "rtc",
 509                 .parent         = &exynos5_clk_aclk_66.clk,
 510                 .enable         = exynos5_clk_ip_peris_ctrl,
 511                 .ctrlbit        = (1 << 20),
 512         }, {
 513                 .name           = "watchdog",
 514                 .parent         = &exynos5_clk_aclk_66.clk,
 515                 .enable         = exynos5_clk_ip_peris_ctrl,
 516                 .ctrlbit        = (1 << 19),
 517         }, {
 518                 .name           = "hsmmc",
 519                 .devname        = "exynos4-sdhci.0",
 520                 .parent         = &exynos5_clk_aclk_200.clk,
 521                 .enable         = exynos5_clk_ip_fsys_ctrl,
 522                 .ctrlbit        = (1 << 12),
 523         }, {
 524                 .name           = "hsmmc",
 525                 .devname        = "exynos4-sdhci.1",
 526                 .parent         = &exynos5_clk_aclk_200.clk,
 527                 .enable         = exynos5_clk_ip_fsys_ctrl,
 528                 .ctrlbit        = (1 << 13),
 529         }, {
 530                 .name           = "hsmmc",
 531                 .devname        = "exynos4-sdhci.2",
 532                 .parent         = &exynos5_clk_aclk_200.clk,
 533                 .enable         = exynos5_clk_ip_fsys_ctrl,
 534                 .ctrlbit        = (1 << 14),
 535         }, {
 536                 .name           = "hsmmc",
 537                 .devname        = "exynos4-sdhci.3",
 538                 .parent         = &exynos5_clk_aclk_200.clk,
 539                 .enable         = exynos5_clk_ip_fsys_ctrl,
 540                 .ctrlbit        = (1 << 15),
 541         }, {
 542                 .name           = "dwmci",
 543                 .parent         = &exynos5_clk_aclk_200.clk,
 544                 .enable         = exynos5_clk_ip_fsys_ctrl,
 545                 .ctrlbit        = (1 << 16),
 546         }, {
 547                 .name           = "sata",
 548                 .devname        = "ahci",
 549                 .enable         = exynos5_clk_ip_fsys_ctrl,
 550                 .ctrlbit        = (1 << 6),
 551         }, {
 552                 .name           = "sata_phy",
 553                 .enable         = exynos5_clk_ip_fsys_ctrl,
 554                 .ctrlbit        = (1 << 24),
 555         }, {
 556                 .name           = "sata_phy_i2c",
 557                 .enable         = exynos5_clk_ip_fsys_ctrl,
 558                 .ctrlbit        = (1 << 25),
 559         }, {
 560                 .name           = "mfc",
 561                 .devname        = "s5p-mfc",
 562                 .enable         = exynos5_clk_ip_mfc_ctrl,
 563                 .ctrlbit        = (1 << 0),
 564         }, {
 565                 .name           = "hdmi",
 566                 .devname        = "exynos4-hdmi",
 567                 .enable         = exynos5_clk_ip_disp1_ctrl,
 568                 .ctrlbit        = (1 << 6),
 569         }, {
 570                 .name           = "mixer",
 571                 .devname        = "s5p-mixer",
 572                 .enable         = exynos5_clk_ip_disp1_ctrl,
 573                 .ctrlbit        = (1 << 5),
 574         }, {
 575                 .name           = "jpeg",
 576                 .enable         = exynos5_clk_ip_gen_ctrl,
 577                 .ctrlbit        = (1 << 2),
 578         }, {
 579                 .name           = "dsim0",
 580                 .enable         = exynos5_clk_ip_disp1_ctrl,
 581                 .ctrlbit        = (1 << 3),
 582         }, {
 583                 .name           = "iis",
 584                 .devname        = "samsung-i2s.1",
 585                 .enable         = exynos5_clk_ip_peric_ctrl,
 586                 .ctrlbit        = (1 << 20),
 587         }, {
 588                 .name           = "iis",
 589                 .devname        = "samsung-i2s.2",
 590                 .enable         = exynos5_clk_ip_peric_ctrl,
 591                 .ctrlbit        = (1 << 21),
 592         }, {
 593                 .name           = "pcm",
 594                 .devname        = "samsung-pcm.1",
 595                 .enable         = exynos5_clk_ip_peric_ctrl,
 596                 .ctrlbit        = (1 << 22),
 597         }, {
 598                 .name           = "pcm",
 599                 .devname        = "samsung-pcm.2",
 600                 .enable         = exynos5_clk_ip_peric_ctrl,
 601                 .ctrlbit        = (1 << 23),
 602         }, {
 603                 .name           = "spdif",
 604                 .devname        = "samsung-spdif",
 605                 .enable         = exynos5_clk_ip_peric_ctrl,
 606                 .ctrlbit        = (1 << 26),
 607         }, {
 608                 .name           = "ac97",
 609                 .devname        = "samsung-ac97",
 610                 .enable         = exynos5_clk_ip_peric_ctrl,
 611                 .ctrlbit        = (1 << 27),
 612         }, {
 613                 .name           = "usbhost",
 614                 .enable         = exynos5_clk_ip_fsys_ctrl ,
 615                 .ctrlbit        = (1 << 18),
 616         }, {
 617                 .name           = "usbotg",
 618                 .enable         = exynos5_clk_ip_fsys_ctrl,
 619                 .ctrlbit        = (1 << 7),
 620         }, {
 621                 .name           = "gps",
 622                 .enable         = exynos5_clk_ip_gps_ctrl,
 623                 .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
 624         }, {
 625                 .name           = "nfcon",
 626                 .enable         = exynos5_clk_ip_fsys_ctrl,
 627                 .ctrlbit        = (1 << 22),
 628         }, {
 629                 .name           = "iop",
 630                 .enable         = exynos5_clk_ip_fsys_ctrl,
 631                 .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
 632         }, {
 633                 .name           = "core_iop",
 634                 .enable         = exynos5_clk_ip_core_ctrl,
 635                 .ctrlbit        = ((1 << 21) | (1 << 3)),
 636         }, {
 637                 .name           = "mcu_iop",
 638                 .enable         = exynos5_clk_ip_fsys_ctrl,
 639                 .ctrlbit        = (1 << 0),
 640         }, {
 641                 .name           = "i2c",
 642                 .devname        = "s3c2440-i2c.0",
 643                 .parent         = &exynos5_clk_aclk_66.clk,
 644                 .enable         = exynos5_clk_ip_peric_ctrl,
 645                 .ctrlbit        = (1 << 6),
 646         }, {
 647                 .name           = "i2c",
 648                 .devname        = "s3c2440-i2c.1",
 649                 .parent         = &exynos5_clk_aclk_66.clk,
 650                 .enable         = exynos5_clk_ip_peric_ctrl,
 651                 .ctrlbit        = (1 << 7),
 652         }, {
 653                 .name           = "i2c",
 654                 .devname        = "s3c2440-i2c.2",
 655                 .parent         = &exynos5_clk_aclk_66.clk,
 656                 .enable         = exynos5_clk_ip_peric_ctrl,
 657                 .ctrlbit        = (1 << 8),
 658         }, {
 659                 .name           = "i2c",
 660                 .devname        = "s3c2440-i2c.3",
 661                 .parent         = &exynos5_clk_aclk_66.clk,
 662                 .enable         = exynos5_clk_ip_peric_ctrl,
 663                 .ctrlbit        = (1 << 9),
 664         }, {
 665                 .name           = "i2c",
 666                 .devname        = "s3c2440-i2c.4",
 667                 .parent         = &exynos5_clk_aclk_66.clk,
 668                 .enable         = exynos5_clk_ip_peric_ctrl,
 669                 .ctrlbit        = (1 << 10),
 670         }, {
 671                 .name           = "i2c",
 672                 .devname        = "s3c2440-i2c.5",
 673                 .parent         = &exynos5_clk_aclk_66.clk,
 674                 .enable         = exynos5_clk_ip_peric_ctrl,
 675                 .ctrlbit        = (1 << 11),
 676         }, {
 677                 .name           = "i2c",
 678                 .devname        = "s3c2440-i2c.6",
 679                 .parent         = &exynos5_clk_aclk_66.clk,
 680                 .enable         = exynos5_clk_ip_peric_ctrl,
 681                 .ctrlbit        = (1 << 12),
 682         }, {
 683                 .name           = "i2c",
 684                 .devname        = "s3c2440-i2c.7",
 685                 .parent         = &exynos5_clk_aclk_66.clk,
 686                 .enable         = exynos5_clk_ip_peric_ctrl,
 687                 .ctrlbit        = (1 << 13),
 688         }, {
 689                 .name           = "i2c",
 690                 .devname        = "s3c2440-hdmiphy-i2c",
 691                 .parent         = &exynos5_clk_aclk_66.clk,
 692                 .enable         = exynos5_clk_ip_peric_ctrl,
 693                 .ctrlbit        = (1 << 14),
 694         }, {
 695                 .name           = SYSMMU_CLOCK_NAME,
 696                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 697                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 698                 .ctrlbit        = (1 << 1),
 699         }, {
 700                 .name           = SYSMMU_CLOCK_NAME,
 701                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 702                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 703                 .ctrlbit        = (1 << 2),
 704         }, {
 705                 .name           = SYSMMU_CLOCK_NAME,
 706                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 707                 .enable         = &exynos5_clk_ip_disp1_ctrl,
 708                 .ctrlbit        = (1 << 9)
 709         }, {
 710                 .name           = SYSMMU_CLOCK_NAME,
 711                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 712                 .enable         = &exynos5_clk_ip_gen_ctrl,
 713                 .ctrlbit        = (1 << 7),
 714         }, {
 715                 .name           = SYSMMU_CLOCK_NAME,
 716                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 717                 .enable         = &exynos5_clk_ip_gen_ctrl,
 718                 .ctrlbit        = (1 << 6)
 719         }, {
 720                 .name           = SYSMMU_CLOCK_NAME,
 721                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
 722                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 723                 .ctrlbit        = (1 << 7),
 724         }, {
 725                 .name           = SYSMMU_CLOCK_NAME,
 726                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
 727                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 728                 .ctrlbit        = (1 << 8),
 729         }, {
 730                 .name           = SYSMMU_CLOCK_NAME,
 731                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
 732                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 733                 .ctrlbit        = (1 << 9),
 734         }, {
 735                 .name           = SYSMMU_CLOCK_NAME,
 736                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
 737                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 738                 .ctrlbit        = (1 << 10),
 739         }, {
 740                 .name           = SYSMMU_CLOCK_NAME,
 741                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 742                 .enable         = &exynos5_clk_ip_isp0_ctrl,
 743                 .ctrlbit        = (0x3F << 8),
 744         }, {
 745                 .name           = SYSMMU_CLOCK_NAME2,
 746                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 747                 .enable         = &exynos5_clk_ip_isp1_ctrl,
 748                 .ctrlbit        = (0xF << 4),
 749         }, {
 750                 .name           = SYSMMU_CLOCK_NAME,
 751                 .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
 752                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 753                 .ctrlbit        = (1 << 11),
 754         }, {
 755                 .name           = SYSMMU_CLOCK_NAME,
 756                 .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
 757                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 758                 .ctrlbit        = (1 << 12),
 759         }, {
 760                 .name           = SYSMMU_CLOCK_NAME,
 761                 .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
 762                 .enable         = &exynos5_clk_ip_acp_ctrl,
 763                 .ctrlbit        = (1 << 7)
 764         }
 765 };
 766
 767 static struct clk exynos5_init_clocks_on[] = {
 768         {
 769                 .name           = "uart",
 770                 .devname        = "s5pv210-uart.0",
 771                 .enable         = exynos5_clk_ip_peric_ctrl,
 772                 .ctrlbit        = (1 << 0),
 773         }, {
 774                 .name           = "uart",
 775                 .devname        = "s5pv210-uart.1",
 776                 .enable         = exynos5_clk_ip_peric_ctrl,
 777                 .ctrlbit        = (1 << 1),
 778         }, {
 779                 .name           = "uart",
 780                 .devname        = "s5pv210-uart.2",
 781                 .enable         = exynos5_clk_ip_peric_ctrl,
 782                 .ctrlbit        = (1 << 2),
 783         }, {
 784                 .name           = "uart",
 785                 .devname        = "s5pv210-uart.3",
 786                 .enable         = exynos5_clk_ip_peric_ctrl,
 787                 .ctrlbit        = (1 << 3),
 788         }, {
 789                 .name           = "uart",
 790                 .devname        = "s5pv210-uart.4",
 791                 .enable         = exynos5_clk_ip_peric_ctrl,
 792                 .ctrlbit        = (1 << 4),
 793         }, {
 794                 .name           = "uart",
 795                 .devname        = "s5pv210-uart.5",
 796                 .enable         = exynos5_clk_ip_peric_ctrl,
 797                 .ctrlbit        = (1 << 5),
 798         }
 799 };
 800
 801 static struct clk exynos5_clk_pdma0 = {
 802         .name           = "dma",
 803         .devname        = "dma-pl330.0",
 804         .enable         = exynos5_clk_ip_fsys_ctrl,
 805         .ctrlbit        = (1 << 1),
 806 };
 807
 808 static struct clk exynos5_clk_pdma1 = {
 809         .name           = "dma",
 810         .devname        = "dma-pl330.1",
 811         .enable         = exynos5_clk_ip_fsys_ctrl,
 812         .ctrlbit        = (1 << 2),
 813 };
 814
 815 static struct clk exynos5_clk_mdma1 = {
 816         .name           = "dma",
 817         .devname        = "dma-pl330.2",
 818         .enable         = exynos5_clk_ip_gen_ctrl,
 819         .ctrlbit        = (1 << 4),
 820 };
 821
 822 struct clk *exynos5_clkset_group_list[] = {
 823         [0] = &clk_ext_xtal_mux,
 824         [1] = NULL,
 825         [2] = &exynos5_clk_sclk_hdmi24m,
 826         [3] = &exynos5_clk_sclk_dptxphy,
 827         [4] = &exynos5_clk_sclk_usbphy,
 828         [5] = &exynos5_clk_sclk_hdmiphy,
 829         [6] = &exynos5_clk_mout_mpll_user.clk,
 830         [7] = &exynos5_clk_mout_epll.clk,
 831         [8] = &exynos5_clk_sclk_vpll.clk,
 832         [9] = &exynos5_clk_mout_cpll.clk,
 833 };
 834
 835 struct clksrc_sources exynos5_clkset_group = {
 836         .sources        = exynos5_clkset_group_list,
 837         .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 838 };
 839
 840 /* Possible clock sources for aclk_266_gscl_sub Mux */
 841 static struct clk *clk_src_gscl_266_list[] = {
 842         [0] = &clk_ext_xtal_mux,
 843         [1] = &exynos5_clk_aclk_266.clk,
 844 };
 845
 846 static struct clksrc_sources clk_src_gscl_266 = {
 847         .sources        = clk_src_gscl_266_list,
 848         .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
 849 };
 850
 851 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
 852         .clk            = {
 853                 .name           = "dout_mmc0",
 854         },
 855         .sources = &exynos5_clkset_group,
 856         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
 857         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 858 };
 859
 860 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
 861         .clk            = {
 862                 .name           = "dout_mmc1",
 863         },
 864         .sources = &exynos5_clkset_group,
 865         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
 866         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 867 };
 868
 869 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
 870         .clk            = {
 871                 .name           = "dout_mmc2",
 872         },
 873         .sources = &exynos5_clkset_group,
 874         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
 875         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 876 };
 877
 878 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
 879         .clk            = {
 880                 .name           = "dout_mmc3",
 881         },
 882         .sources = &exynos5_clkset_group,
 883         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
 884         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 885 };
 886
 887 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
 888         .clk            = {
 889                 .name           = "dout_mmc4",
 890         },
 891         .sources = &exynos5_clkset_group,
 892         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
 893         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 894 };
 895
 896 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
 897         .clk    = {
 898                 .name           = "uclk1",
 899                 .devname        = "exynos4210-uart.0",
 900                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 901                 .ctrlbit        = (1 << 0),
 902         },
 903         .sources = &exynos5_clkset_group,
 904         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
 905         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
 906 };
 907
 908 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
 909         .clk    = {
 910                 .name           = "uclk1",
 911                 .devname        = "exynos4210-uart.1",
 912                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 913                 .ctrlbit        = (1 << 4),
 914         },
 915         .sources = &exynos5_clkset_group,
 916         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
 917         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
 918 };
 919
 920 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
 921         .clk    = {
 922                 .name           = "uclk1",
 923                 .devname        = "exynos4210-uart.2",
 924                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 925                 .ctrlbit        = (1 << 8),
 926         },
 927         .sources = &exynos5_clkset_group,
 928         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
 929         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
 930 };
 931
 932 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 933         .clk    = {
 934                 .name           = "uclk1",
 935                 .devname        = "exynos4210-uart.3",
 936                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 937                 .ctrlbit        = (1 << 12),
 938         },
 939         .sources = &exynos5_clkset_group,
 940         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
 941         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
 942 };
 943
 944 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 945         .clk    = {
 946                 .name           = "sclk_mmc",
 947                 .devname        = "exynos4-sdhci.0",
 948                 .parent         = &exynos5_clk_dout_mmc0.clk,
 949                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
 950                 .ctrlbit        = (1 << 0),
 951         },
 952         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
 953 };
 954
 955 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 956         .clk    = {
 957                 .name           = "sclk_mmc",
 958                 .devname        = "exynos4-sdhci.1",
 959                 .parent         = &exynos5_clk_dout_mmc1.clk,
 960                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
 961                 .ctrlbit        = (1 << 4),
 962         },
 963         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
 964 };
 965
 966 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 967         .clk    = {
 968                 .name           = "sclk_mmc",
 969                 .devname        = "exynos4-sdhci.2",
 970                 .parent         = &exynos5_clk_dout_mmc2.clk,
 971                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
 972                 .ctrlbit        = (1 << 8),
 973         },
 974         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
 975 };
 976
 977 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
 978         .clk    = {
 979                 .name           = "sclk_mmc",
 980                 .devname        = "exynos4-sdhci.3",
 981                 .parent         = &exynos5_clk_dout_mmc3.clk,
 982                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
 983                 .ctrlbit        = (1 << 12),
 984         },
 985         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
 986 };
 987
 988 static struct clksrc_clk exynos5_clksrcs[] = {
 989         {
 990                 .clk    = {
 991                         .name           = "sclk_dwmci",
 992                         .parent         = &exynos5_clk_dout_mmc4.clk,
 993                         .enable         = exynos5_clksrc_mask_fsys_ctrl,
 994                         .ctrlbit        = (1 << 16),
 995                 },
 996                 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
 997         }, {
 998                 .clk    = {
 999                         .name           = "sclk_fimd",
1000                         .devname        = "s3cfb.1",
1001                         .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
1002                         .ctrlbit        = (1 << 0),
1003                 },
1004                 .sources = &exynos5_clkset_group,
1005                 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1006                 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1007         }, {
1008                 .clk    = {
1009                         .name           = "aclk_266_gscl",
1010                 },
1011                 .sources = &clk_src_gscl_266,
1012                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1013         }, {
1014                 .clk    = {
1015                         .name           = "sclk_g3d",
1016                         .devname        = "mali-t604.0",
1017                         .enable         = exynos5_clk_block_ctrl,
1018                         .ctrlbit        = (1 << 1),
1019                 },
1020                 .sources = &exynos5_clkset_aclk,
1021                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1022                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1023         }, {
1024                 .clk    = {
1025                         .name           = "sclk_gscl_wrap",
1026                         .devname        = "s5p-mipi-csis.0",
1027                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1028                         .ctrlbit        = (1 << 24),
1029                 },
1030                 .sources = &exynos5_clkset_group,
1031                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1032                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1033         }, {
1034                 .clk    = {
1035                         .name           = "sclk_gscl_wrap",
1036                         .devname        = "s5p-mipi-csis.1",
1037                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1038                         .ctrlbit        = (1 << 28),
1039                 },
1040                 .sources = &exynos5_clkset_group,
1041                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1042                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1043         }, {
1044                 .clk    = {
1045                         .name           = "sclk_cam0",
1046                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1047                         .ctrlbit        = (1 << 16),
1048                 },
1049                 .sources = &exynos5_clkset_group,
1050                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1051                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1052         }, {
1053                 .clk    = {
1054                         .name           = "sclk_cam1",
1055                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1056                         .ctrlbit        = (1 << 20),
1057                 },
1058                 .sources = &exynos5_clkset_group,
1059                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1060                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1061         }, {
1062                 .clk    = {
1063                         .name           = "sclk_jpeg",
1064                         .parent         = &exynos5_clk_mout_cpll.clk,
1065                 },
1066                 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1067         },
1068 };
1069
1070 /* Clock initialization code */
1071 static struct clksrc_clk *exynos5_sysclks[] = {
1072         &exynos5_clk_mout_apll,
1073         &exynos5_clk_sclk_apll,
1074         &exynos5_clk_mout_bpll,
1075         &exynos5_clk_mout_bpll_fout,
1076         &exynos5_clk_mout_bpll_user,
1077         &exynos5_clk_mout_cpll,
1078         &exynos5_clk_mout_epll,
1079         &exynos5_clk_mout_mpll,
1080         &exynos5_clk_mout_mpll_fout,
1081         &exynos5_clk_mout_mpll_user,
1082         &exynos5_clk_vpllsrc,
1083         &exynos5_clk_sclk_vpll,
1084         &exynos5_clk_mout_cpu,
1085         &exynos5_clk_dout_armclk,
1086         &exynos5_clk_dout_arm2clk,
1087         &exynos5_clk_cdrex,
1088         &exynos5_clk_aclk_400,
1089         &exynos5_clk_aclk_333,
1090         &exynos5_clk_aclk_266,
1091         &exynos5_clk_aclk_200,
1092         &exynos5_clk_aclk_166,
1093         &exynos5_clk_aclk_66_pre,
1094         &exynos5_clk_aclk_66,
1095         &exynos5_clk_dout_mmc0,
1096         &exynos5_clk_dout_mmc1,
1097         &exynos5_clk_dout_mmc2,
1098         &exynos5_clk_dout_mmc3,
1099         &exynos5_clk_dout_mmc4,
1100         &exynos5_clk_aclk_acp,
1101         &exynos5_clk_pclk_acp,
1102 };
1103
1104 static struct clk *exynos5_clk_cdev[] = {
1105         &exynos5_clk_pdma0,
1106         &exynos5_clk_pdma1,
1107         &exynos5_clk_mdma1,
1108 };
1109
1110 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1111         &exynos5_clk_sclk_uart0,
1112         &exynos5_clk_sclk_uart1,
1113         &exynos5_clk_sclk_uart2,
1114         &exynos5_clk_sclk_uart3,
1115         &exynos5_clk_sclk_mmc0,
1116         &exynos5_clk_sclk_mmc1,
1117         &exynos5_clk_sclk_mmc2,
1118         &exynos5_clk_sclk_mmc3,
1119 };
1120
1121 static struct clk_lookup exynos5_clk_lookup[] = {
1122         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1123         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1124         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1125         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1126         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1127         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1128         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1129         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1130         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1131         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1132         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1133 };
1134
1135 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1136 {
1137         return clk->rate;
1138 }
1139
1140 static struct clk *exynos5_clks[] __initdata = {
1141         &exynos5_clk_sclk_hdmi27m,
1142         &exynos5_clk_sclk_hdmiphy,
1143         &clk_fout_bpll,
1144         &clk_fout_bpll_div2,
1145         &clk_fout_cpll,
1146         &clk_fout_mpll_div2,
1147         &exynos5_clk_armclk,
1148 };
1149
1150 static u32 epll_div[][6] = {
1151         { 192000000, 0, 48, 3, 1, 0 },
1152         { 180000000, 0, 45, 3, 1, 0 },
1153         {  73728000, 1, 73, 3, 3, 47710 },
1154         {  67737600, 1, 90, 4, 3, 20762 },
1155         {  49152000, 0, 49, 3, 3, 9961 },
1156         {  45158400, 0, 45, 3, 3, 10381 },
1157         { 180633600, 0, 45, 3, 1, 10381 },
1158 };
1159
1160 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1161 {
1162         unsigned int epll_con, epll_con_k;
1163         unsigned int i;
1164         unsigned int tmp;
1165         unsigned int epll_rate;
1166         unsigned int locktime;
1167         unsigned int lockcnt;
1168
1169         /* Return if nothing changed */
1170         if (clk->rate == rate)
1171                 return 0;
1172
1173         if (clk->parent)
1174                 epll_rate = clk_get_rate(clk->parent);
1175         else
1176                 epll_rate = clk_ext_xtal_mux.rate;
1177
1178         if (epll_rate != 24000000) {
1179                 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1180                 return -EINVAL;
1181         }
1182
1183         epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1184         epll_con &= ~(0x1 << 27 | \
1185                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
1186                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1187                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1188
1189         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1190                 if (epll_div[i][0] == rate) {
1191                         epll_con_k = epll_div[i][5] << 0;
1192                         epll_con |= epll_div[i][1] << 27;
1193                         epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1194                         epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1195                         epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1196                         break;
1197                 }
1198         }
1199
1200         if (i == ARRAY_SIZE(epll_div)) {
1201                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1202                                 __func__);
1203                 return -EINVAL;
1204         }
1205
1206         epll_rate /= 1000000;
1207
1208         /* 3000 max_cycls : specification data */
1209         locktime = 3000 / epll_rate * epll_div[i][3];
1210         lockcnt = locktime * 10000 / (10000 / epll_rate);
1211
1212         __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1213
1214         __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1215         __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1216
1217         do {
1218                 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1219         } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1220
1221         clk->rate = rate;
1222
1223         return 0;
1224 }
1225
1226 static struct clk_ops exynos5_epll_ops = {
1227         .get_rate = exynos5_epll_get_rate,
1228         .set_rate = exynos5_epll_set_rate,
1229 };
1230
1231 static int xtal_rate;
1232
1233 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1234 {
1235         return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1236 }
1237
1238 static struct clk_ops exynos5_fout_apll_ops = {
1239         .get_rate = exynos5_fout_apll_get_rate,
1240 };
1241
1242 #ifdef CONFIG_PM
1243 static int exynos5_clock_suspend(void)
1244 {
1245         s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1246
1247         return 0;
1248 }
1249
1250 static void exynos5_clock_resume(void)
1251 {
1252         s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1253 }
1254 #else
1255 #define exynos5_clock_suspend NULL
1256 #define exynos5_clock_resume NULL
1257 #endif
1258
1259 struct syscore_ops exynos5_clock_syscore_ops = {
1260         .suspend        = exynos5_clock_suspend,
1261         .resume         = exynos5_clock_resume,
1262 };
1263
1264 void __init_or_cpufreq exynos5_setup_clocks(void)
1265 {
1266         struct clk *xtal_clk;
1267         unsigned long apll;
1268         unsigned long bpll;
1269         unsigned long cpll;
1270         unsigned long mpll;
1271         unsigned long epll;
1272         unsigned long vpll;
1273         unsigned long vpllsrc;
1274         unsigned long xtal;
1275         unsigned long armclk;
1276         unsigned long mout_cdrex;
1277         unsigned long aclk_400;
1278         unsigned long aclk_333;
1279         unsigned long aclk_266;
1280         unsigned long aclk_200;
1281         unsigned long aclk_166;
1282         unsigned long aclk_66;
1283         unsigned int ptr;
1284
1285         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1286
1287         xtal_clk = clk_get(NULL, "xtal");
1288         BUG_ON(IS_ERR(xtal_clk));
1289
1290         xtal = clk_get_rate(xtal_clk);
1291
1292         xtal_rate = xtal;
1293
1294         clk_put(xtal_clk);
1295
1296         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1297
1298         apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1299         bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1300         cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1301         mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1302         epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1303                         __raw_readl(EXYNOS5_EPLL_CON1));
1304
1305         vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1306         vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1307                         __raw_readl(EXYNOS5_VPLL_CON1));
1308
1309         clk_fout_apll.ops = &exynos5_fout_apll_ops;
1310         clk_fout_bpll.rate = bpll;
1311         clk_fout_bpll_div2.rate = bpll >> 1;
1312         clk_fout_cpll.rate = cpll;
1313         clk_fout_mpll.rate = mpll;
1314         clk_fout_mpll_div2.rate = mpll >> 1;
1315         clk_fout_epll.rate = epll;
1316         clk_fout_vpll.rate = vpll;
1317
1318         printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1319                         "M=%ld, E=%ld V=%ld",
1320                         apll, bpll, cpll, mpll, epll, vpll);
1321
1322         armclk = clk_get_rate(&exynos5_clk_armclk);
1323         mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1324
1325         aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1326         aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1327         aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1328         aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1329         aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1330         aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1331
1332         printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1333                         "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1334                         "ACLK166=%ld, ACLK66=%ld\n",
1335                         armclk, mout_cdrex, aclk_400,
1336                         aclk_333, aclk_266, aclk_200,
1337                         aclk_166, aclk_66);
1338
1339
1340         clk_fout_epll.ops = &exynos5_epll_ops;
1341
1342         if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1343                 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1344                                 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1345
1346         clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1347         clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1348
1349         clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1350         clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1351
1352         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1353                 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1354 }
1355
1356 void __init exynos5_register_clocks(void)
1357 {
1358         int ptr;
1359
1360         s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1361
1362         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1363                 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1364
1365         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1366                 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1367
1368         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1369                 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1370
1371         s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1372         s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1373
1374         s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1375         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1376                 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1377
1378         s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1379         s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1380         clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1381
1382         register_syscore_ops(&exynos5_clock_syscore_ops);
1383         s3c_pwmclk_init();
1384 }