2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/init.h>
19 #include <linux/irqchip/irq-davinci-aintc.h>
20 #include <linux/platform_data/edma.h>
21 #include <linux/platform_data/gpio-davinci.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial_8250.h>
25 #include <asm/mach/map.h>
27 #include <mach/common.h>
28 #include <mach/cputype.h>
30 #include <mach/serial.h>
31 #include <mach/time.h>
38 #define DAVINCI_VPIF_BASE (0x01C12000)
40 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
42 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
45 #define DM646X_EMAC_BASE 0x01c80000
46 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
47 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
48 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
49 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
50 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
52 static struct emac_platform_data dm646x_emac_pdata = {
53 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
54 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
55 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
56 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
57 .version = EMAC_VERSION_2,
60 static struct resource dm646x_emac_resources[] = {
62 .start = DM646X_EMAC_BASE,
63 .end = DM646X_EMAC_BASE + SZ_16K - 1,
64 .flags = IORESOURCE_MEM,
67 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
68 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
69 .flags = IORESOURCE_IRQ,
72 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
73 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
74 .flags = IORESOURCE_IRQ,
77 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
78 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
79 .flags = IORESOURCE_IRQ,
82 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
83 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
84 .flags = IORESOURCE_IRQ,
88 static struct platform_device dm646x_emac_device = {
89 .name = "davinci_emac",
92 .platform_data = &dm646x_emac_pdata,
94 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
95 .resource = dm646x_emac_resources,
98 static struct resource dm646x_mdio_resources[] = {
100 .start = DM646X_EMAC_MDIO_BASE,
101 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
102 .flags = IORESOURCE_MEM,
106 static struct platform_device dm646x_mdio_device = {
107 .name = "davinci_mdio",
109 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
110 .resource = dm646x_mdio_resources,
114 * Device specific mux setup
116 * soc description mux mode mode mux dbg
117 * reg offset mask mode
119 static const struct mux_config dm646x_pins[] = {
120 #ifdef CONFIG_DAVINCI_MUX
121 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
123 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
125 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
127 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
129 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
131 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
133 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
135 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
137 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
139 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
141 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
143 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
145 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
147 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
151 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
152 [IRQ_DM646X_VP_VERTINT0] = 7,
153 [IRQ_DM646X_VP_VERTINT1] = 7,
154 [IRQ_DM646X_VP_VERTINT2] = 7,
155 [IRQ_DM646X_VP_VERTINT3] = 7,
156 [IRQ_DM646X_VP_ERRINT] = 7,
157 [IRQ_DM646X_RESERVED_1] = 7,
158 [IRQ_DM646X_RESERVED_2] = 7,
159 [IRQ_DM646X_WDINT] = 7,
160 [IRQ_DM646X_CRGENINT0] = 7,
161 [IRQ_DM646X_CRGENINT1] = 7,
162 [IRQ_DM646X_TSIFINT0] = 7,
163 [IRQ_DM646X_TSIFINT1] = 7,
164 [IRQ_DM646X_VDCEINT] = 7,
165 [IRQ_DM646X_USBINT] = 7,
166 [IRQ_DM646X_USBDMAINT] = 7,
167 [IRQ_DM646X_PCIINT] = 7,
168 [IRQ_CCINT0] = 7, /* dma */
169 [IRQ_CCERRINT] = 7, /* dma */
170 [IRQ_TCERRINT0] = 7, /* dma */
171 [IRQ_TCERRINT] = 7, /* dma */
172 [IRQ_DM646X_TCERRINT2] = 7,
173 [IRQ_DM646X_TCERRINT3] = 7,
174 [IRQ_DM646X_IDE] = 7,
175 [IRQ_DM646X_HPIINT] = 7,
176 [IRQ_DM646X_EMACRXTHINT] = 7,
177 [IRQ_DM646X_EMACRXINT] = 7,
178 [IRQ_DM646X_EMACTXINT] = 7,
179 [IRQ_DM646X_EMACMISCINT] = 7,
180 [IRQ_DM646X_MCASP0TXINT] = 7,
181 [IRQ_DM646X_MCASP0RXINT] = 7,
182 [IRQ_DM646X_RESERVED_3] = 7,
183 [IRQ_DM646X_MCASP1TXINT] = 7,
184 [IRQ_TINT0_TINT12] = 7, /* clockevent */
185 [IRQ_TINT0_TINT34] = 7, /* clocksource */
186 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
187 [IRQ_TINT1_TINT34] = 7, /* system tick */
190 [IRQ_DM646X_VLQINT] = 7,
194 [IRQ_DM646X_UARTINT2] = 7,
195 [IRQ_DM646X_SPINT0] = 7,
196 [IRQ_DM646X_SPINT1] = 7,
197 [IRQ_DM646X_DSP2ARMINT] = 7,
198 [IRQ_DM646X_RESERVED_4] = 7,
199 [IRQ_DM646X_PSCINT] = 7,
200 [IRQ_DM646X_GPIO0] = 7,
201 [IRQ_DM646X_GPIO1] = 7,
202 [IRQ_DM646X_GPIO2] = 7,
203 [IRQ_DM646X_GPIO3] = 7,
204 [IRQ_DM646X_GPIO4] = 7,
205 [IRQ_DM646X_GPIO5] = 7,
206 [IRQ_DM646X_GPIO6] = 7,
207 [IRQ_DM646X_GPIO7] = 7,
208 [IRQ_DM646X_GPIOBNK0] = 7,
209 [IRQ_DM646X_GPIOBNK1] = 7,
210 [IRQ_DM646X_GPIOBNK2] = 7,
211 [IRQ_DM646X_DDRINT] = 7,
212 [IRQ_DM646X_AEMIFINT] = 7,
218 /*----------------------------------------------------------------------*/
220 /* Four Transfer Controllers on DM646x */
221 static s8 dm646x_queue_priority_mapping[][2] = {
222 /* {event queue no, Priority} */
230 static const struct dma_slave_map dm646x_edma_map[] = {
231 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
232 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
233 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
234 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
235 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
238 static struct edma_soc_info dm646x_edma_pdata = {
239 .queue_priority_mapping = dm646x_queue_priority_mapping,
240 .default_queue = EVENTQ_1,
241 .slave_map = dm646x_edma_map,
242 .slavecnt = ARRAY_SIZE(dm646x_edma_map),
245 static struct resource edma_resources[] = {
249 .end = 0x01c00000 + SZ_64K - 1,
250 .flags = IORESOURCE_MEM,
255 .end = 0x01c10000 + SZ_1K - 1,
256 .flags = IORESOURCE_MEM,
261 .end = 0x01c10400 + SZ_1K - 1,
262 .flags = IORESOURCE_MEM,
267 .end = 0x01c10800 + SZ_1K - 1,
268 .flags = IORESOURCE_MEM,
273 .end = 0x01c10c00 + SZ_1K - 1,
274 .flags = IORESOURCE_MEM,
277 .name = "edma3_ccint",
278 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
279 .flags = IORESOURCE_IRQ,
282 .name = "edma3_ccerrint",
283 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
284 .flags = IORESOURCE_IRQ,
286 /* not using TC*_ERR */
289 static const struct platform_device_info dm646x_edma_device __initconst = {
292 .dma_mask = DMA_BIT_MASK(32),
293 .res = edma_resources,
294 .num_res = ARRAY_SIZE(edma_resources),
295 .data = &dm646x_edma_pdata,
296 .size_data = sizeof(dm646x_edma_pdata),
299 static struct resource dm646x_mcasp0_resources[] = {
302 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
303 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
304 .flags = IORESOURCE_MEM,
308 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
309 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
310 .flags = IORESOURCE_DMA,
314 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
315 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
316 .flags = IORESOURCE_DMA,
320 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
321 .flags = IORESOURCE_IRQ,
325 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
326 .flags = IORESOURCE_IRQ,
330 /* DIT mode only, rx is not supported */
331 static struct resource dm646x_mcasp1_resources[] = {
334 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
335 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
336 .flags = IORESOURCE_MEM,
340 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
341 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
342 .flags = IORESOURCE_DMA,
346 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
347 .flags = IORESOURCE_IRQ,
351 static struct platform_device dm646x_mcasp0_device = {
352 .name = "davinci-mcasp",
354 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
355 .resource = dm646x_mcasp0_resources,
358 static struct platform_device dm646x_mcasp1_device = {
359 .name = "davinci-mcasp",
361 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
362 .resource = dm646x_mcasp1_resources,
365 static struct platform_device dm646x_dit_device = {
370 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
372 static struct resource vpif_resource[] = {
374 .start = DAVINCI_VPIF_BASE,
375 .end = DAVINCI_VPIF_BASE + 0x03ff,
376 .flags = IORESOURCE_MEM,
380 static struct platform_device vpif_dev = {
384 .dma_mask = &vpif_dma_mask,
385 .coherent_dma_mask = DMA_BIT_MASK(32),
387 .resource = vpif_resource,
388 .num_resources = ARRAY_SIZE(vpif_resource),
391 static struct resource vpif_display_resource[] = {
393 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
394 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
395 .flags = IORESOURCE_IRQ,
398 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
399 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
400 .flags = IORESOURCE_IRQ,
404 static struct platform_device vpif_display_dev = {
405 .name = "vpif_display",
408 .dma_mask = &vpif_dma_mask,
409 .coherent_dma_mask = DMA_BIT_MASK(32),
411 .resource = vpif_display_resource,
412 .num_resources = ARRAY_SIZE(vpif_display_resource),
415 static struct resource vpif_capture_resource[] = {
417 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
418 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
419 .flags = IORESOURCE_IRQ,
422 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
423 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
424 .flags = IORESOURCE_IRQ,
428 static struct platform_device vpif_capture_dev = {
429 .name = "vpif_capture",
432 .dma_mask = &vpif_dma_mask,
433 .coherent_dma_mask = DMA_BIT_MASK(32),
435 .resource = vpif_capture_resource,
436 .num_resources = ARRAY_SIZE(vpif_capture_resource),
439 static struct resource dm646x_gpio_resources[] = {
441 .start = DAVINCI_GPIO_BASE,
442 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
443 .flags = IORESOURCE_MEM,
446 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
447 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
448 .flags = IORESOURCE_IRQ,
451 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
452 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
453 .flags = IORESOURCE_IRQ,
456 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
457 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
458 .flags = IORESOURCE_IRQ,
462 static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
463 .no_auto_base = true,
468 int __init dm646x_gpio_register(void)
470 return davinci_gpio_register(dm646x_gpio_resources,
471 ARRAY_SIZE(dm646x_gpio_resources),
472 &dm646x_gpio_platform_data);
474 /*----------------------------------------------------------------------*/
476 static struct map_desc dm646x_io_desc[] = {
479 .pfn = __phys_to_pfn(IO_PHYS),
485 /* Contents of JTAG ID register used to identify exact cpu type */
486 static struct davinci_id dm646x_ids[] = {
490 .manufacturer = 0x017,
491 .cpu_id = DAVINCI_CPU_ID_DM6467,
492 .name = "dm6467_rev1.x",
497 .manufacturer = 0x017,
498 .cpu_id = DAVINCI_CPU_ID_DM6467,
499 .name = "dm6467_rev3.x",
504 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
505 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
506 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
507 * T1_TOP: Timer 1, top : <unused>
509 static struct davinci_timer_info dm646x_timer_info = {
510 .timers = davinci_timer_instance,
511 .clockevent_id = T0_BOT,
512 .clocksource_id = T0_TOP,
515 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
517 .mapbase = DAVINCI_UART0_BASE,
518 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
519 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
521 .iotype = UPIO_MEM32,
528 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
530 .mapbase = DAVINCI_UART1_BASE,
531 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
532 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
534 .iotype = UPIO_MEM32,
541 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
543 .mapbase = DAVINCI_UART2_BASE,
544 .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
545 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
547 .iotype = UPIO_MEM32,
555 struct platform_device dm646x_serial_device[] = {
557 .name = "serial8250",
558 .id = PLAT8250_DEV_PLATFORM,
560 .platform_data = dm646x_serial0_platform_data,
564 .name = "serial8250",
565 .id = PLAT8250_DEV_PLATFORM1,
567 .platform_data = dm646x_serial1_platform_data,
571 .name = "serial8250",
572 .id = PLAT8250_DEV_PLATFORM2,
574 .platform_data = dm646x_serial2_platform_data,
581 static const struct davinci_soc_info davinci_soc_info_dm646x = {
582 .io_desc = dm646x_io_desc,
583 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
584 .jtag_id_reg = 0x01c40028,
586 .ids_num = ARRAY_SIZE(dm646x_ids),
587 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
588 .pinmux_pins = dm646x_pins,
589 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
590 .timer_info = &dm646x_timer_info,
591 .emac_pdata = &dm646x_emac_pdata,
592 .sram_dma = 0x10010000,
596 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
598 dm646x_mcasp0_device.dev.platform_data = pdata;
599 platform_device_register(&dm646x_mcasp0_device);
602 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
604 dm646x_mcasp1_device.dev.platform_data = pdata;
605 platform_device_register(&dm646x_mcasp1_device);
606 platform_device_register(&dm646x_dit_device);
609 void dm646x_setup_vpif(struct vpif_display_config *display_config,
610 struct vpif_capture_config *capture_config)
614 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
615 value &= ~VSCLKDIS_MASK;
616 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
618 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
619 value &= ~VDD3P3V_VID_MASK;
620 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
622 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
623 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
624 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
625 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
627 vpif_display_dev.dev.platform_data = display_config;
628 vpif_capture_dev.dev.platform_data = capture_config;
629 platform_device_register(&vpif_dev);
630 platform_device_register(&vpif_display_dev);
631 platform_device_register(&vpif_capture_dev);
634 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
636 struct platform_device *edma_pdev;
638 dm646x_edma_pdata.rsv = rsv;
640 edma_pdev = platform_device_register_full(&dm646x_edma_device);
641 return PTR_ERR_OR_ZERO(edma_pdev);
644 void __init dm646x_init(void)
646 davinci_common_init(&davinci_soc_info_dm646x);
647 davinci_map_sysmod();
650 void __init dm646x_init_time(unsigned long ref_clk_rate,
651 unsigned long aux_clkin_rate)
653 void __iomem *pll1, *psc;
656 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
657 clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
659 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
660 dm646x_pll1_init(NULL, pll1, NULL);
662 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
663 dm646x_psc_init(NULL, psc);
665 clk = clk_get(NULL, "timer0");
667 davinci_timer_init(clk);
670 static struct resource dm646x_pll2_resources[] = {
672 .start = DAVINCI_PLL2_BASE,
673 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
674 .flags = IORESOURCE_MEM,
678 static struct platform_device dm646x_pll2_device = {
679 .name = "dm646x-pll2",
681 .resource = dm646x_pll2_resources,
682 .num_resources = ARRAY_SIZE(dm646x_pll2_resources),
685 void __init dm646x_register_clocks(void)
687 /* PLL1 and PSC are registered in dm646x_init_time() */
688 platform_device_register(&dm646x_pll2_device);
691 static const struct davinci_aintc_config dm646x_aintc_config = {
693 .start = DAVINCI_ARM_INTC_BASE,
694 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
695 .flags = IORESOURCE_MEM,
698 .prios = dm646x_default_priorities,
701 void __init dm646x_init_irq(void)
703 davinci_aintc_init(&dm646x_aintc_config);
706 static int __init dm646x_init_devices(void)
710 if (!cpu_is_davinci_dm646x())
713 platform_device_register(&dm646x_mdio_device);
714 platform_device_register(&dm646x_emac_device);
716 ret = davinci_init_wdt();
718 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
722 postcore_initcall(dm646x_init_devices);