2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/init.h>
14 #include <linux/clk.h>
15 #include <linux/serial_8250.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/edma.h>
18 #include <linux/platform_data/gpio-davinci.h>
20 #include <asm/mach/map.h>
22 #include <mach/cputype.h>
23 #include <mach/irqs.h>
26 #include <mach/time.h>
27 #include <mach/serial.h>
28 #include <mach/common.h>
35 #define DAVINCI_VPIF_BASE (0x01C12000)
37 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
39 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
42 #define DM646X_EMAC_BASE 0x01c80000
43 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
44 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
45 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
46 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
47 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
49 static struct pll_data pll1_data = {
51 .phys_base = DAVINCI_PLL1_BASE,
54 static struct pll_data pll2_data = {
56 .phys_base = DAVINCI_PLL2_BASE,
59 static struct clk ref_clk = {
61 /* rate is initialized in dm646x_init_time() */
64 static struct clk aux_clkin = {
66 /* rate is initialized in dm646x_init_time() */
69 static struct clk pll1_clk = {
72 .pll_data = &pll1_data,
76 static struct clk pll1_sysclk1 = {
77 .name = "pll1_sysclk1",
83 static struct clk pll1_sysclk2 = {
84 .name = "pll1_sysclk2",
90 static struct clk pll1_sysclk3 = {
91 .name = "pll1_sysclk3",
97 static struct clk pll1_sysclk4 = {
98 .name = "pll1_sysclk4",
104 static struct clk pll1_sysclk5 = {
105 .name = "pll1_sysclk5",
111 static struct clk pll1_sysclk6 = {
112 .name = "pll1_sysclk6",
118 static struct clk pll1_sysclk8 = {
119 .name = "pll1_sysclk8",
125 static struct clk pll1_sysclk9 = {
126 .name = "pll1_sysclk9",
132 static struct clk pll1_sysclkbp = {
133 .name = "pll1_sysclkbp",
135 .flags = CLK_PLL | PRE_PLL,
139 static struct clk pll1_aux_clk = {
140 .name = "pll1_aux_clk",
142 .flags = CLK_PLL | PRE_PLL,
145 static struct clk pll2_clk = {
148 .pll_data = &pll2_data,
152 static struct clk pll2_sysclk1 = {
153 .name = "pll2_sysclk1",
159 static struct clk dsp_clk = {
161 .parent = &pll1_sysclk1,
162 .lpsc = DM646X_LPSC_C64X_CPU,
163 .usecount = 1, /* REVISIT how to disable? */
166 static struct clk arm_clk = {
168 .parent = &pll1_sysclk2,
169 .lpsc = DM646X_LPSC_ARM,
170 .flags = ALWAYS_ENABLED,
173 static struct clk edma_cc_clk = {
175 .parent = &pll1_sysclk2,
176 .lpsc = DM646X_LPSC_TPCC,
177 .flags = ALWAYS_ENABLED,
180 static struct clk edma_tc0_clk = {
182 .parent = &pll1_sysclk2,
183 .lpsc = DM646X_LPSC_TPTC0,
184 .flags = ALWAYS_ENABLED,
187 static struct clk edma_tc1_clk = {
189 .parent = &pll1_sysclk2,
190 .lpsc = DM646X_LPSC_TPTC1,
191 .flags = ALWAYS_ENABLED,
194 static struct clk edma_tc2_clk = {
196 .parent = &pll1_sysclk2,
197 .lpsc = DM646X_LPSC_TPTC2,
198 .flags = ALWAYS_ENABLED,
201 static struct clk edma_tc3_clk = {
203 .parent = &pll1_sysclk2,
204 .lpsc = DM646X_LPSC_TPTC3,
205 .flags = ALWAYS_ENABLED,
208 static struct clk uart0_clk = {
210 .parent = &aux_clkin,
211 .lpsc = DM646X_LPSC_UART0,
214 static struct clk uart1_clk = {
216 .parent = &aux_clkin,
217 .lpsc = DM646X_LPSC_UART1,
220 static struct clk uart2_clk = {
222 .parent = &aux_clkin,
223 .lpsc = DM646X_LPSC_UART2,
226 static struct clk i2c_clk = {
228 .parent = &pll1_sysclk3,
229 .lpsc = DM646X_LPSC_I2C,
232 static struct clk gpio_clk = {
234 .parent = &pll1_sysclk3,
235 .lpsc = DM646X_LPSC_GPIO,
238 static struct clk mcasp0_clk = {
240 .parent = &pll1_sysclk3,
241 .lpsc = DM646X_LPSC_McASP0,
244 static struct clk mcasp1_clk = {
246 .parent = &pll1_sysclk3,
247 .lpsc = DM646X_LPSC_McASP1,
250 static struct clk aemif_clk = {
252 .parent = &pll1_sysclk3,
253 .lpsc = DM646X_LPSC_AEMIF,
254 .flags = ALWAYS_ENABLED,
257 static struct clk emac_clk = {
259 .parent = &pll1_sysclk3,
260 .lpsc = DM646X_LPSC_EMAC,
263 static struct clk pwm0_clk = {
265 .parent = &pll1_sysclk3,
266 .lpsc = DM646X_LPSC_PWM0,
267 .usecount = 1, /* REVIST: disabling hangs system */
270 static struct clk pwm1_clk = {
272 .parent = &pll1_sysclk3,
273 .lpsc = DM646X_LPSC_PWM1,
274 .usecount = 1, /* REVIST: disabling hangs system */
277 static struct clk timer0_clk = {
279 .parent = &pll1_sysclk3,
280 .lpsc = DM646X_LPSC_TIMER0,
283 static struct clk timer1_clk = {
285 .parent = &pll1_sysclk3,
286 .lpsc = DM646X_LPSC_TIMER1,
289 static struct clk timer2_clk = {
291 .parent = &pll1_sysclk3,
292 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
296 static struct clk ide_clk = {
298 .parent = &pll1_sysclk4,
299 .lpsc = DAVINCI_LPSC_ATA,
302 static struct clk vpif0_clk = {
305 .lpsc = DM646X_LPSC_VPSSMSTR,
306 .flags = ALWAYS_ENABLED,
309 static struct clk vpif1_clk = {
312 .lpsc = DM646X_LPSC_VPSSSLV,
313 .flags = ALWAYS_ENABLED,
316 static struct clk_lookup dm646x_clks[] = {
317 CLK(NULL, "ref", &ref_clk),
318 CLK(NULL, "aux", &aux_clkin),
319 CLK(NULL, "pll1", &pll1_clk),
320 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
321 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
322 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
323 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
324 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
325 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
329 CLK(NULL, "pll1_aux", &pll1_aux_clk),
330 CLK(NULL, "pll2", &pll2_clk),
331 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
332 CLK(NULL, "dsp", &dsp_clk),
333 CLK(NULL, "arm", &arm_clk),
334 CLK(NULL, "edma_cc", &edma_cc_clk),
335 CLK(NULL, "edma_tc0", &edma_tc0_clk),
336 CLK(NULL, "edma_tc1", &edma_tc1_clk),
337 CLK(NULL, "edma_tc2", &edma_tc2_clk),
338 CLK(NULL, "edma_tc3", &edma_tc3_clk),
339 CLK("serial8250.0", NULL, &uart0_clk),
340 CLK("serial8250.1", NULL, &uart1_clk),
341 CLK("serial8250.2", NULL, &uart2_clk),
342 CLK("i2c_davinci.1", NULL, &i2c_clk),
343 CLK(NULL, "gpio", &gpio_clk),
344 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
345 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
346 CLK(NULL, "aemif", &aemif_clk),
347 CLK("davinci_emac.1", NULL, &emac_clk),
348 CLK("davinci_mdio.0", "fck", &emac_clk),
349 CLK(NULL, "pwm0", &pwm0_clk),
350 CLK(NULL, "pwm1", &pwm1_clk),
351 CLK(NULL, "timer0", &timer0_clk),
352 CLK(NULL, "timer1", &timer1_clk),
353 CLK("davinci-wdt", NULL, &timer2_clk),
354 CLK("palm_bk3710", NULL, &ide_clk),
355 CLK(NULL, "vpif0", &vpif0_clk),
356 CLK(NULL, "vpif1", &vpif1_clk),
357 CLK(NULL, NULL, NULL),
360 static struct emac_platform_data dm646x_emac_pdata = {
361 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
362 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
363 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
364 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
365 .version = EMAC_VERSION_2,
368 static struct resource dm646x_emac_resources[] = {
370 .start = DM646X_EMAC_BASE,
371 .end = DM646X_EMAC_BASE + SZ_16K - 1,
372 .flags = IORESOURCE_MEM,
375 .start = IRQ_DM646X_EMACRXTHINT,
376 .end = IRQ_DM646X_EMACRXTHINT,
377 .flags = IORESOURCE_IRQ,
380 .start = IRQ_DM646X_EMACRXINT,
381 .end = IRQ_DM646X_EMACRXINT,
382 .flags = IORESOURCE_IRQ,
385 .start = IRQ_DM646X_EMACTXINT,
386 .end = IRQ_DM646X_EMACTXINT,
387 .flags = IORESOURCE_IRQ,
390 .start = IRQ_DM646X_EMACMISCINT,
391 .end = IRQ_DM646X_EMACMISCINT,
392 .flags = IORESOURCE_IRQ,
396 static struct platform_device dm646x_emac_device = {
397 .name = "davinci_emac",
400 .platform_data = &dm646x_emac_pdata,
402 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
403 .resource = dm646x_emac_resources,
406 static struct resource dm646x_mdio_resources[] = {
408 .start = DM646X_EMAC_MDIO_BASE,
409 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
410 .flags = IORESOURCE_MEM,
414 static struct platform_device dm646x_mdio_device = {
415 .name = "davinci_mdio",
417 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
418 .resource = dm646x_mdio_resources,
422 * Device specific mux setup
424 * soc description mux mode mode mux dbg
425 * reg offset mask mode
427 static const struct mux_config dm646x_pins[] = {
428 #ifdef CONFIG_DAVINCI_MUX
429 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
431 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
433 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
435 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
437 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
439 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
441 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
443 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
445 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
447 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
449 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
451 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
453 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
455 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
459 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
460 [IRQ_DM646X_VP_VERTINT0] = 7,
461 [IRQ_DM646X_VP_VERTINT1] = 7,
462 [IRQ_DM646X_VP_VERTINT2] = 7,
463 [IRQ_DM646X_VP_VERTINT3] = 7,
464 [IRQ_DM646X_VP_ERRINT] = 7,
465 [IRQ_DM646X_RESERVED_1] = 7,
466 [IRQ_DM646X_RESERVED_2] = 7,
467 [IRQ_DM646X_WDINT] = 7,
468 [IRQ_DM646X_CRGENINT0] = 7,
469 [IRQ_DM646X_CRGENINT1] = 7,
470 [IRQ_DM646X_TSIFINT0] = 7,
471 [IRQ_DM646X_TSIFINT1] = 7,
472 [IRQ_DM646X_VDCEINT] = 7,
473 [IRQ_DM646X_USBINT] = 7,
474 [IRQ_DM646X_USBDMAINT] = 7,
475 [IRQ_DM646X_PCIINT] = 7,
476 [IRQ_CCINT0] = 7, /* dma */
477 [IRQ_CCERRINT] = 7, /* dma */
478 [IRQ_TCERRINT0] = 7, /* dma */
479 [IRQ_TCERRINT] = 7, /* dma */
480 [IRQ_DM646X_TCERRINT2] = 7,
481 [IRQ_DM646X_TCERRINT3] = 7,
482 [IRQ_DM646X_IDE] = 7,
483 [IRQ_DM646X_HPIINT] = 7,
484 [IRQ_DM646X_EMACRXTHINT] = 7,
485 [IRQ_DM646X_EMACRXINT] = 7,
486 [IRQ_DM646X_EMACTXINT] = 7,
487 [IRQ_DM646X_EMACMISCINT] = 7,
488 [IRQ_DM646X_MCASP0TXINT] = 7,
489 [IRQ_DM646X_MCASP0RXINT] = 7,
490 [IRQ_DM646X_RESERVED_3] = 7,
491 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
492 [IRQ_TINT0_TINT34] = 7, /* clocksource */
493 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
494 [IRQ_TINT1_TINT34] = 7, /* system tick */
497 [IRQ_DM646X_VLQINT] = 7,
501 [IRQ_DM646X_UARTINT2] = 7,
502 [IRQ_DM646X_SPINT0] = 7,
503 [IRQ_DM646X_SPINT1] = 7,
504 [IRQ_DM646X_DSP2ARMINT] = 7,
505 [IRQ_DM646X_RESERVED_4] = 7,
506 [IRQ_DM646X_PSCINT] = 7,
507 [IRQ_DM646X_GPIO0] = 7,
508 [IRQ_DM646X_GPIO1] = 7,
509 [IRQ_DM646X_GPIO2] = 7,
510 [IRQ_DM646X_GPIO3] = 7,
511 [IRQ_DM646X_GPIO4] = 7,
512 [IRQ_DM646X_GPIO5] = 7,
513 [IRQ_DM646X_GPIO6] = 7,
514 [IRQ_DM646X_GPIO7] = 7,
515 [IRQ_DM646X_GPIOBNK0] = 7,
516 [IRQ_DM646X_GPIOBNK1] = 7,
517 [IRQ_DM646X_GPIOBNK2] = 7,
518 [IRQ_DM646X_DDRINT] = 7,
519 [IRQ_DM646X_AEMIFINT] = 7,
525 /*----------------------------------------------------------------------*/
527 /* Four Transfer Controllers on DM646x */
528 static s8 dm646x_queue_priority_mapping[][2] = {
529 /* {event queue no, Priority} */
537 static const struct dma_slave_map dm646x_edma_map[] = {
538 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
539 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
540 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
541 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
542 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
545 static struct edma_soc_info dm646x_edma_pdata = {
546 .queue_priority_mapping = dm646x_queue_priority_mapping,
547 .default_queue = EVENTQ_1,
548 .slave_map = dm646x_edma_map,
549 .slavecnt = ARRAY_SIZE(dm646x_edma_map),
552 static struct resource edma_resources[] = {
556 .end = 0x01c00000 + SZ_64K - 1,
557 .flags = IORESOURCE_MEM,
562 .end = 0x01c10000 + SZ_1K - 1,
563 .flags = IORESOURCE_MEM,
568 .end = 0x01c10400 + SZ_1K - 1,
569 .flags = IORESOURCE_MEM,
574 .end = 0x01c10800 + SZ_1K - 1,
575 .flags = IORESOURCE_MEM,
580 .end = 0x01c10c00 + SZ_1K - 1,
581 .flags = IORESOURCE_MEM,
584 .name = "edma3_ccint",
586 .flags = IORESOURCE_IRQ,
589 .name = "edma3_ccerrint",
590 .start = IRQ_CCERRINT,
591 .flags = IORESOURCE_IRQ,
593 /* not using TC*_ERR */
596 static const struct platform_device_info dm646x_edma_device __initconst = {
599 .dma_mask = DMA_BIT_MASK(32),
600 .res = edma_resources,
601 .num_res = ARRAY_SIZE(edma_resources),
602 .data = &dm646x_edma_pdata,
603 .size_data = sizeof(dm646x_edma_pdata),
606 static struct resource dm646x_mcasp0_resources[] = {
609 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
610 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
611 .flags = IORESOURCE_MEM,
615 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
616 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
617 .flags = IORESOURCE_DMA,
621 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
622 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
623 .flags = IORESOURCE_DMA,
627 .start = IRQ_DM646X_MCASP0TXINT,
628 .flags = IORESOURCE_IRQ,
632 .start = IRQ_DM646X_MCASP0RXINT,
633 .flags = IORESOURCE_IRQ,
637 /* DIT mode only, rx is not supported */
638 static struct resource dm646x_mcasp1_resources[] = {
641 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
642 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
643 .flags = IORESOURCE_MEM,
647 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
648 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
649 .flags = IORESOURCE_DMA,
653 .start = IRQ_DM646X_MCASP1TXINT,
654 .flags = IORESOURCE_IRQ,
658 static struct platform_device dm646x_mcasp0_device = {
659 .name = "davinci-mcasp",
661 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
662 .resource = dm646x_mcasp0_resources,
665 static struct platform_device dm646x_mcasp1_device = {
666 .name = "davinci-mcasp",
668 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
669 .resource = dm646x_mcasp1_resources,
672 static struct platform_device dm646x_dit_device = {
677 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
679 static struct resource vpif_resource[] = {
681 .start = DAVINCI_VPIF_BASE,
682 .end = DAVINCI_VPIF_BASE + 0x03ff,
683 .flags = IORESOURCE_MEM,
687 static struct platform_device vpif_dev = {
691 .dma_mask = &vpif_dma_mask,
692 .coherent_dma_mask = DMA_BIT_MASK(32),
694 .resource = vpif_resource,
695 .num_resources = ARRAY_SIZE(vpif_resource),
698 static struct resource vpif_display_resource[] = {
700 .start = IRQ_DM646X_VP_VERTINT2,
701 .end = IRQ_DM646X_VP_VERTINT2,
702 .flags = IORESOURCE_IRQ,
705 .start = IRQ_DM646X_VP_VERTINT3,
706 .end = IRQ_DM646X_VP_VERTINT3,
707 .flags = IORESOURCE_IRQ,
711 static struct platform_device vpif_display_dev = {
712 .name = "vpif_display",
715 .dma_mask = &vpif_dma_mask,
716 .coherent_dma_mask = DMA_BIT_MASK(32),
718 .resource = vpif_display_resource,
719 .num_resources = ARRAY_SIZE(vpif_display_resource),
722 static struct resource vpif_capture_resource[] = {
724 .start = IRQ_DM646X_VP_VERTINT0,
725 .end = IRQ_DM646X_VP_VERTINT0,
726 .flags = IORESOURCE_IRQ,
729 .start = IRQ_DM646X_VP_VERTINT1,
730 .end = IRQ_DM646X_VP_VERTINT1,
731 .flags = IORESOURCE_IRQ,
735 static struct platform_device vpif_capture_dev = {
736 .name = "vpif_capture",
739 .dma_mask = &vpif_dma_mask,
740 .coherent_dma_mask = DMA_BIT_MASK(32),
742 .resource = vpif_capture_resource,
743 .num_resources = ARRAY_SIZE(vpif_capture_resource),
746 static struct resource dm646x_gpio_resources[] = {
748 .start = DAVINCI_GPIO_BASE,
749 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
750 .flags = IORESOURCE_MEM,
753 .start = IRQ_DM646X_GPIOBNK0,
754 .end = IRQ_DM646X_GPIOBNK2,
755 .flags = IORESOURCE_IRQ,
759 static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
763 int __init dm646x_gpio_register(void)
765 return davinci_gpio_register(dm646x_gpio_resources,
766 ARRAY_SIZE(dm646x_gpio_resources),
767 &dm646x_gpio_platform_data);
769 /*----------------------------------------------------------------------*/
771 static struct map_desc dm646x_io_desc[] = {
774 .pfn = __phys_to_pfn(IO_PHYS),
780 /* Contents of JTAG ID register used to identify exact cpu type */
781 static struct davinci_id dm646x_ids[] = {
785 .manufacturer = 0x017,
786 .cpu_id = DAVINCI_CPU_ID_DM6467,
787 .name = "dm6467_rev1.x",
792 .manufacturer = 0x017,
793 .cpu_id = DAVINCI_CPU_ID_DM6467,
794 .name = "dm6467_rev3.x",
798 static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
801 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
802 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
803 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
804 * T1_TOP: Timer 1, top : <unused>
806 static struct davinci_timer_info dm646x_timer_info = {
807 .timers = davinci_timer_instance,
808 .clockevent_id = T0_BOT,
809 .clocksource_id = T0_TOP,
812 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
814 .mapbase = DAVINCI_UART0_BASE,
816 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
818 .iotype = UPIO_MEM32,
825 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
827 .mapbase = DAVINCI_UART1_BASE,
829 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
831 .iotype = UPIO_MEM32,
838 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
840 .mapbase = DAVINCI_UART2_BASE,
841 .irq = IRQ_DM646X_UARTINT2,
842 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
844 .iotype = UPIO_MEM32,
852 struct platform_device dm646x_serial_device[] = {
854 .name = "serial8250",
855 .id = PLAT8250_DEV_PLATFORM,
857 .platform_data = dm646x_serial0_platform_data,
861 .name = "serial8250",
862 .id = PLAT8250_DEV_PLATFORM1,
864 .platform_data = dm646x_serial1_platform_data,
868 .name = "serial8250",
869 .id = PLAT8250_DEV_PLATFORM2,
871 .platform_data = dm646x_serial2_platform_data,
878 static const struct davinci_soc_info davinci_soc_info_dm646x = {
879 .io_desc = dm646x_io_desc,
880 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
881 .jtag_id_reg = 0x01c40028,
883 .ids_num = ARRAY_SIZE(dm646x_ids),
884 .psc_bases = dm646x_psc_bases,
885 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
886 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
887 .pinmux_pins = dm646x_pins,
888 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
889 .intc_base = DAVINCI_ARM_INTC_BASE,
890 .intc_type = DAVINCI_INTC_TYPE_AINTC,
891 .intc_irq_prios = dm646x_default_priorities,
892 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
893 .timer_info = &dm646x_timer_info,
894 .emac_pdata = &dm646x_emac_pdata,
895 .sram_dma = 0x10010000,
899 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
901 dm646x_mcasp0_device.dev.platform_data = pdata;
902 platform_device_register(&dm646x_mcasp0_device);
905 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
907 dm646x_mcasp1_device.dev.platform_data = pdata;
908 platform_device_register(&dm646x_mcasp1_device);
909 platform_device_register(&dm646x_dit_device);
912 void dm646x_setup_vpif(struct vpif_display_config *display_config,
913 struct vpif_capture_config *capture_config)
917 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
918 value &= ~VSCLKDIS_MASK;
919 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
921 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
922 value &= ~VDD3P3V_VID_MASK;
923 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
925 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
926 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
927 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
928 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
930 vpif_display_dev.dev.platform_data = display_config;
931 vpif_capture_dev.dev.platform_data = capture_config;
932 platform_device_register(&vpif_dev);
933 platform_device_register(&vpif_display_dev);
934 platform_device_register(&vpif_capture_dev);
937 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
939 struct platform_device *edma_pdev;
941 dm646x_edma_pdata.rsv = rsv;
943 edma_pdev = platform_device_register_full(&dm646x_edma_device);
944 return PTR_ERR_OR_ZERO(edma_pdev);
947 void __init dm646x_init(void)
949 davinci_common_init(&davinci_soc_info_dm646x);
950 davinci_map_sysmod();
953 void __init dm646x_init_time(unsigned long ref_clk_rate,
954 unsigned long aux_clkin_rate)
956 ref_clk.rate = ref_clk_rate;
957 aux_clkin.rate = aux_clkin_rate;
958 davinci_clk_init(dm646x_clks);
959 davinci_timer_init();
962 static int __init dm646x_init_devices(void)
966 if (!cpu_is_davinci_dm646x())
969 platform_device_register(&dm646x_mdio_device);
970 platform_device_register(&dm646x_emac_device);
972 ret = davinci_init_wdt();
974 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
978 postcore_initcall(dm646x_init_devices);