arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/clk/davinci.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/irqchip/irq-davinci-aintc.h>
  20 #include <linux/platform_data/edma.h>
  21 #include <linux/platform_data/gpio-davinci.h>
  22 #include <linux/platform_data/spi-davinci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/serial_8250.h>
  25 #include <linux/spi/spi.h>
  26
  27 #include <asm/mach/map.h>
  28
  29 #include <mach/common.h>
  30 #include <mach/cputype.h>
  31 #include <mach/mux.h>
  32 #include <mach/serial.h>
  33 #include <mach/time.h>
  34
  35 #include "asp.h"
  36 #include "davinci.h"
  37 #include "irqs.h"
  38 #include "mux.h"
  39
  40 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
  41 #define DM355_OSD_BASE          (IO_PHYS + 0x70200)
  42 #define DM355_VENC_BASE         (IO_PHYS + 0x70400)
  43
  44 /*
  45  * Device specific clocks
  46  */
  47 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  48
  49 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
  50
  51 static struct resource dm355_spi0_resources[] = {
  52         {
  53                 .start = 0x01c66000,
  54                 .end   = 0x01c667ff,
  55                 .flags = IORESOURCE_MEM,
  56         },
  57         {
  58                 .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
  59                 .flags = IORESOURCE_IRQ,
  60         },
  61 };
  62
  63 static struct davinci_spi_platform_data dm355_spi0_pdata = {
  64         .version        = SPI_VERSION_1,
  65         .num_chipselect = 2,
  66         .cshold_bug     = true,
  67         .dma_event_q    = EVENTQ_1,
  68         .prescaler_limit = 1,
  69 };
  70 static struct platform_device dm355_spi0_device = {
  71         .name = "spi_davinci",
  72         .id = 0,
  73         .dev = {
  74                 .dma_mask = &dm355_spi0_dma_mask,
  75                 .coherent_dma_mask = DMA_BIT_MASK(32),
  76                 .platform_data = &dm355_spi0_pdata,
  77         },
  78         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
  79         .resource = dm355_spi0_resources,
  80 };
  81
  82 void __init dm355_init_spi0(unsigned chipselect_mask,
  83                 const struct spi_board_info *info, unsigned len)
  84 {
  85         /* for now, assume we need MISO */
  86         davinci_cfg_reg(DM355_SPI0_SDI);
  87
  88         /* not all slaves will be wired up */
  89         if (chipselect_mask & BIT(0))
  90                 davinci_cfg_reg(DM355_SPI0_SDENA0);
  91         if (chipselect_mask & BIT(1))
  92                 davinci_cfg_reg(DM355_SPI0_SDENA1);
  93
  94         spi_register_board_info(info, len);
  95
  96         platform_device_register(&dm355_spi0_device);
  97 }
  98
  99 /*----------------------------------------------------------------------*/
 100
 101 #define INTMUX          0x18
 102 #define EVTMUX          0x1c
 103
 104 /*
 105  * Device specific mux setup
 106  *
 107  *      soc     description     mux  mode   mode  mux    dbg
 108  *                              reg  offset mask  mode
 109  */
 110 static const struct mux_config dm355_pins[] = {
 111 #ifdef CONFIG_DAVINCI_MUX
 112 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 113
 114 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 115 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 116 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 117 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 118 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 119 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 120
 121 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 122 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 123
 124 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 125 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 126 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 127 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 128 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 129 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 130
 131 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 132 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 133 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 134
 135 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 136 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 137 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 138
 139 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 140 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 141 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 142
 143 MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
 144 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
 145 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 146 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 147 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 148
 149 MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
 150 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
 151 MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
 152 MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
 153 MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
 154 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
 155 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 156 #endif
 157 };
 158
 159 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 160         [IRQ_DM355_CCDC_VDINT0]         = 2,
 161         [IRQ_DM355_CCDC_VDINT1]         = 6,
 162         [IRQ_DM355_CCDC_VDINT2]         = 6,
 163         [IRQ_DM355_IPIPE_HST]           = 6,
 164         [IRQ_DM355_H3AINT]              = 6,
 165         [IRQ_DM355_IPIPE_SDR]           = 6,
 166         [IRQ_DM355_IPIPEIFINT]          = 6,
 167         [IRQ_DM355_OSDINT]              = 7,
 168         [IRQ_DM355_VENCINT]             = 6,
 169         [IRQ_ASQINT]                    = 6,
 170         [IRQ_IMXINT]                    = 6,
 171         [IRQ_USBINT]                    = 4,
 172         [IRQ_DM355_RTOINT]              = 4,
 173         [IRQ_DM355_UARTINT2]            = 7,
 174         [IRQ_DM355_TINT6]               = 7,
 175         [IRQ_CCINT0]                    = 5,    /* dma */
 176         [IRQ_CCERRINT]                  = 5,    /* dma */
 177         [IRQ_TCERRINT0]                 = 5,    /* dma */
 178         [IRQ_TCERRINT]                  = 5,    /* dma */
 179         [IRQ_DM355_SPINT2_1]            = 7,
 180         [IRQ_DM355_TINT7]               = 4,
 181         [IRQ_DM355_SDIOINT0]            = 7,
 182         [IRQ_MBXINT]                    = 7,
 183         [IRQ_MBRINT]                    = 7,
 184         [IRQ_MMCINT]                    = 7,
 185         [IRQ_DM355_MMCINT1]             = 7,
 186         [IRQ_DM355_PWMINT3]             = 7,
 187         [IRQ_DDRINT]                    = 7,
 188         [IRQ_AEMIFINT]                  = 7,
 189         [IRQ_DM355_SDIOINT1]            = 4,
 190         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 191         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 192         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 193         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 194         [IRQ_PWMINT0]                   = 7,
 195         [IRQ_PWMINT1]                   = 7,
 196         [IRQ_PWMINT2]                   = 7,
 197         [IRQ_I2C]                       = 3,
 198         [IRQ_UARTINT0]                  = 3,
 199         [IRQ_UARTINT1]                  = 3,
 200         [IRQ_DM355_SPINT0_0]            = 3,
 201         [IRQ_DM355_SPINT0_1]            = 3,
 202         [IRQ_DM355_GPIO0]               = 3,
 203         [IRQ_DM355_GPIO1]               = 7,
 204         [IRQ_DM355_GPIO2]               = 4,
 205         [IRQ_DM355_GPIO3]               = 4,
 206         [IRQ_DM355_GPIO4]               = 7,
 207         [IRQ_DM355_GPIO5]               = 7,
 208         [IRQ_DM355_GPIO6]               = 7,
 209         [IRQ_DM355_GPIO7]               = 7,
 210         [IRQ_DM355_GPIO8]               = 7,
 211         [IRQ_DM355_GPIO9]               = 7,
 212         [IRQ_DM355_GPIOBNK0]            = 7,
 213         [IRQ_DM355_GPIOBNK1]            = 7,
 214         [IRQ_DM355_GPIOBNK2]            = 7,
 215         [IRQ_DM355_GPIOBNK3]            = 7,
 216         [IRQ_DM355_GPIOBNK4]            = 7,
 217         [IRQ_DM355_GPIOBNK5]            = 7,
 218         [IRQ_DM355_GPIOBNK6]            = 7,
 219         [IRQ_COMMTX]                    = 7,
 220         [IRQ_COMMRX]                    = 7,
 221         [IRQ_EMUINT]                    = 7,
 222 };
 223
 224 /*----------------------------------------------------------------------*/
 225
 226 static s8 queue_priority_mapping[][2] = {
 227         /* {event queue no, Priority} */
 228         {0, 3},
 229         {1, 7},
 230         {-1, -1},
 231 };
 232
 233 static const struct dma_slave_map dm355_edma_map[] = {
 234         { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
 235         { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
 236         { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
 237         { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
 238         { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
 239         { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
 240         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
 241         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
 242         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
 243         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
 244         { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
 245         { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
 246         { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
 247         { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
 248 };
 249
 250 static struct edma_soc_info dm355_edma_pdata = {
 251         .queue_priority_mapping = queue_priority_mapping,
 252         .default_queue          = EVENTQ_1,
 253         .slave_map              = dm355_edma_map,
 254         .slavecnt               = ARRAY_SIZE(dm355_edma_map),
 255 };
 256
 257 static struct resource edma_resources[] = {
 258         {
 259                 .name   = "edma3_cc",
 260                 .start  = 0x01c00000,
 261                 .end    = 0x01c00000 + SZ_64K - 1,
 262                 .flags  = IORESOURCE_MEM,
 263         },
 264         {
 265                 .name   = "edma3_tc0",
 266                 .start  = 0x01c10000,
 267                 .end    = 0x01c10000 + SZ_1K - 1,
 268                 .flags  = IORESOURCE_MEM,
 269         },
 270         {
 271                 .name   = "edma3_tc1",
 272                 .start  = 0x01c10400,
 273                 .end    = 0x01c10400 + SZ_1K - 1,
 274                 .flags  = IORESOURCE_MEM,
 275         },
 276         {
 277                 .name   = "edma3_ccint",
 278                 .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
 279                 .flags  = IORESOURCE_IRQ,
 280         },
 281         {
 282                 .name   = "edma3_ccerrint",
 283                 .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
 284                 .flags  = IORESOURCE_IRQ,
 285         },
 286         /* not using (or muxing) TC*_ERR */
 287 };
 288
 289 static const struct platform_device_info dm355_edma_device __initconst = {
 290         .name           = "edma",
 291         .id             = 0,
 292         .dma_mask       = DMA_BIT_MASK(32),
 293         .res            = edma_resources,
 294         .num_res        = ARRAY_SIZE(edma_resources),
 295         .data           = &dm355_edma_pdata,
 296         .size_data      = sizeof(dm355_edma_pdata),
 297 };
 298
 299 static struct resource dm355_asp1_resources[] = {
 300         {
 301                 .name   = "mpu",
 302                 .start  = DAVINCI_ASP1_BASE,
 303                 .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
 304                 .flags  = IORESOURCE_MEM,
 305         },
 306         {
 307                 .start  = DAVINCI_DMA_ASP1_TX,
 308                 .end    = DAVINCI_DMA_ASP1_TX,
 309                 .flags  = IORESOURCE_DMA,
 310         },
 311         {
 312                 .start  = DAVINCI_DMA_ASP1_RX,
 313                 .end    = DAVINCI_DMA_ASP1_RX,
 314                 .flags  = IORESOURCE_DMA,
 315         },
 316 };
 317
 318 static struct platform_device dm355_asp1_device = {
 319         .name           = "davinci-mcbsp",
 320         .id             = 1,
 321         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
 322         .resource       = dm355_asp1_resources,
 323 };
 324
 325 static void dm355_ccdc_setup_pinmux(void)
 326 {
 327         davinci_cfg_reg(DM355_VIN_PCLK);
 328         davinci_cfg_reg(DM355_VIN_CAM_WEN);
 329         davinci_cfg_reg(DM355_VIN_CAM_VD);
 330         davinci_cfg_reg(DM355_VIN_CAM_HD);
 331         davinci_cfg_reg(DM355_VIN_YIN_EN);
 332         davinci_cfg_reg(DM355_VIN_CINL_EN);
 333         davinci_cfg_reg(DM355_VIN_CINH_EN);
 334 }
 335
 336 static struct resource dm355_vpss_resources[] = {
 337         {
 338                 /* VPSS BL Base address */
 339                 .name           = "vpss",
 340                 .start          = 0x01c70800,
 341                 .end            = 0x01c70800 + 0xff,
 342                 .flags          = IORESOURCE_MEM,
 343         },
 344         {
 345                 /* VPSS CLK Base address */
 346                 .name           = "vpss",
 347                 .start          = 0x01c70000,
 348                 .end            = 0x01c70000 + 0xf,
 349                 .flags          = IORESOURCE_MEM,
 350         },
 351 };
 352
 353 static struct platform_device dm355_vpss_device = {
 354         .name                   = "vpss",
 355         .id                     = -1,
 356         .dev.platform_data      = "dm355_vpss",
 357         .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
 358         .resource               = dm355_vpss_resources,
 359 };
 360
 361 static struct resource vpfe_resources[] = {
 362         {
 363                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 364                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 365                 .flags          = IORESOURCE_IRQ,
 366         },
 367         {
 368                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 369                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 370                 .flags          = IORESOURCE_IRQ,
 371         },
 372 };
 373
 374 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 375 static struct resource dm355_ccdc_resource[] = {
 376         /* CCDC Base address */
 377         {
 378                 .flags          = IORESOURCE_MEM,
 379                 .start          = 0x01c70600,
 380                 .end            = 0x01c70600 + 0x1ff,
 381         },
 382 };
 383 static struct platform_device dm355_ccdc_dev = {
 384         .name           = "dm355_ccdc",
 385         .id             = -1,
 386         .num_resources  = ARRAY_SIZE(dm355_ccdc_resource),
 387         .resource       = dm355_ccdc_resource,
 388         .dev = {
 389                 .dma_mask               = &vpfe_capture_dma_mask,
 390                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 391                 .platform_data          = dm355_ccdc_setup_pinmux,
 392         },
 393 };
 394
 395 static struct platform_device vpfe_capture_dev = {
 396         .name           = CAPTURE_DRV_NAME,
 397         .id             = -1,
 398         .num_resources  = ARRAY_SIZE(vpfe_resources),
 399         .resource       = vpfe_resources,
 400         .dev = {
 401                 .dma_mask               = &vpfe_capture_dma_mask,
 402                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 403         },
 404 };
 405
 406 static struct resource dm355_osd_resources[] = {
 407         {
 408                 .start  = DM355_OSD_BASE,
 409                 .end    = DM355_OSD_BASE + 0x17f,
 410                 .flags  = IORESOURCE_MEM,
 411         },
 412 };
 413
 414 static struct platform_device dm355_osd_dev = {
 415         .name           = DM355_VPBE_OSD_SUBDEV_NAME,
 416         .id             = -1,
 417         .num_resources  = ARRAY_SIZE(dm355_osd_resources),
 418         .resource       = dm355_osd_resources,
 419         .dev            = {
 420                 .dma_mask               = &vpfe_capture_dma_mask,
 421                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 422         },
 423 };
 424
 425 static struct resource dm355_venc_resources[] = {
 426         {
 427                 .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 428                 .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 429                 .flags  = IORESOURCE_IRQ,
 430         },
 431         /* venc registers io space */
 432         {
 433                 .start  = DM355_VENC_BASE,
 434                 .end    = DM355_VENC_BASE + 0x17f,
 435                 .flags  = IORESOURCE_MEM,
 436         },
 437         /* VDAC config register io space */
 438         {
 439                 .start  = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
 440                 .end    = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
 441                 .flags  = IORESOURCE_MEM,
 442         },
 443 };
 444
 445 static struct resource dm355_v4l2_disp_resources[] = {
 446         {
 447                 .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 448                 .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 449                 .flags  = IORESOURCE_IRQ,
 450         },
 451         /* venc registers io space */
 452         {
 453                 .start  = DM355_VENC_BASE,
 454                 .end    = DM355_VENC_BASE + 0x17f,
 455                 .flags  = IORESOURCE_MEM,
 456         },
 457 };
 458
 459 static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
 460 {
 461         switch (if_type) {
 462         case MEDIA_BUS_FMT_SGRBG8_1X8:
 463                 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
 464                 break;
 465         case MEDIA_BUS_FMT_YUYV10_1X20:
 466                 if (field)
 467                         davinci_cfg_reg(DM355_VOUT_FIELD);
 468                 else
 469                         davinci_cfg_reg(DM355_VOUT_FIELD_G70);
 470                 break;
 471         default:
 472                 return -EINVAL;
 473         }
 474
 475         davinci_cfg_reg(DM355_VOUT_COUTL_EN);
 476         davinci_cfg_reg(DM355_VOUT_COUTH_EN);
 477
 478         return 0;
 479 }
 480
 481 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
 482                                    unsigned int pclock)
 483 {
 484         void __iomem *vpss_clk_ctrl_reg;
 485
 486         vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
 487
 488         switch (type) {
 489         case VPBE_ENC_STD:
 490                 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
 491                        vpss_clk_ctrl_reg);
 492                 break;
 493         case VPBE_ENC_DV_TIMINGS:
 494                 if (pclock > 27000000)
 495                         /*
 496                          * For HD, use external clock source since we cannot
 497                          * support HD mode with internal clocks.
 498                          */
 499                         writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
 500                 break;
 501         default:
 502                 return -EINVAL;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static struct platform_device dm355_vpbe_display = {
 509         .name           = "vpbe-v4l2",
 510         .id             = -1,
 511         .num_resources  = ARRAY_SIZE(dm355_v4l2_disp_resources),
 512         .resource       = dm355_v4l2_disp_resources,
 513         .dev            = {
 514                 .dma_mask               = &vpfe_capture_dma_mask,
 515                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 516         },
 517 };
 518
 519 static struct venc_platform_data dm355_venc_pdata = {
 520         .setup_pinmux   = dm355_vpbe_setup_pinmux,
 521         .setup_clock    = dm355_venc_setup_clock,
 522 };
 523
 524 static struct platform_device dm355_venc_dev = {
 525         .name           = DM355_VPBE_VENC_SUBDEV_NAME,
 526         .id             = -1,
 527         .num_resources  = ARRAY_SIZE(dm355_venc_resources),
 528         .resource       = dm355_venc_resources,
 529         .dev            = {
 530                 .dma_mask               = &vpfe_capture_dma_mask,
 531                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 532                 .platform_data          = (void *)&dm355_venc_pdata,
 533         },
 534 };
 535
 536 static struct platform_device dm355_vpbe_dev = {
 537         .name           = "vpbe_controller",
 538         .id             = -1,
 539         .dev            = {
 540                 .dma_mask               = &vpfe_capture_dma_mask,
 541                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 542         },
 543 };
 544
 545 static struct resource dm355_gpio_resources[] = {
 546         {       /* registers */
 547                 .start  = DAVINCI_GPIO_BASE,
 548                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 549                 .flags  = IORESOURCE_MEM,
 550         },
 551         {       /* interrupt */
 552                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
 553                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
 554                 .flags  = IORESOURCE_IRQ,
 555         },
 556         {
 557                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
 558                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
 559                 .flags  = IORESOURCE_IRQ,
 560         },
 561         {
 562                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
 563                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
 564                 .flags  = IORESOURCE_IRQ,
 565         },
 566         {
 567                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
 568                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
 569                 .flags  = IORESOURCE_IRQ,
 570         },
 571         {
 572                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
 573                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
 574                 .flags  = IORESOURCE_IRQ,
 575         },
 576         {
 577                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
 578                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
 579                 .flags  = IORESOURCE_IRQ,
 580         },
 581         {
 582                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
 583                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
 584                 .flags  = IORESOURCE_IRQ,
 585         },
 586 };
 587
 588 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
 589         .no_auto_base   = true,
 590         .base           = 0,
 591         .ngpio          = 104,
 592 };
 593
 594 int __init dm355_gpio_register(void)
 595 {
 596         return davinci_gpio_register(dm355_gpio_resources,
 597                                      ARRAY_SIZE(dm355_gpio_resources),
 598                                      &dm355_gpio_platform_data);
 599 }
 600 /*----------------------------------------------------------------------*/
 601
 602 static struct map_desc dm355_io_desc[] = {
 603         {
 604                 .virtual        = IO_VIRT,
 605                 .pfn            = __phys_to_pfn(IO_PHYS),
 606                 .length         = IO_SIZE,
 607                 .type           = MT_DEVICE
 608         },
 609 };
 610
 611 /* Contents of JTAG ID register used to identify exact cpu type */
 612 static struct davinci_id dm355_ids[] = {
 613         {
 614                 .variant        = 0x0,
 615                 .part_no        = 0xb73b,
 616                 .manufacturer   = 0x00f,
 617                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 618                 .name           = "dm355",
 619         },
 620 };
 621
 622 /*
 623  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 624  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 625  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 626  * T1_TOP: Timer 1, top   :  <unused>
 627  */
 628 static struct davinci_timer_info dm355_timer_info = {
 629         .timers         = davinci_timer_instance,
 630         .clockevent_id  = T0_BOT,
 631         .clocksource_id = T0_TOP,
 632 };
 633
 634 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
 635         {
 636                 .mapbase        = DAVINCI_UART0_BASE,
 637                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
 638                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 639                                   UPF_IOREMAP,
 640                 .iotype         = UPIO_MEM,
 641                 .regshift       = 2,
 642         },
 643         {
 644                 .flags  = 0,
 645         }
 646 };
 647 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
 648         {
 649                 .mapbase        = DAVINCI_UART1_BASE,
 650                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
 651                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 652                                   UPF_IOREMAP,
 653                 .iotype         = UPIO_MEM,
 654                 .regshift       = 2,
 655         },
 656         {
 657                 .flags  = 0,
 658         }
 659 };
 660 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
 661         {
 662                 .mapbase        = DM355_UART2_BASE,
 663                 .irq            = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
 664                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 665                                   UPF_IOREMAP,
 666                 .iotype         = UPIO_MEM,
 667                 .regshift       = 2,
 668         },
 669         {
 670                 .flags  = 0,
 671         }
 672 };
 673
 674 struct platform_device dm355_serial_device[] = {
 675         {
 676                 .name                   = "serial8250",
 677                 .id                     = PLAT8250_DEV_PLATFORM,
 678                 .dev                    = {
 679                         .platform_data  = dm355_serial0_platform_data,
 680                 }
 681         },
 682         {
 683                 .name                   = "serial8250",
 684                 .id                     = PLAT8250_DEV_PLATFORM1,
 685                 .dev                    = {
 686                         .platform_data  = dm355_serial1_platform_data,
 687                 }
 688         },
 689         {
 690                 .name                   = "serial8250",
 691                 .id                     = PLAT8250_DEV_PLATFORM2,
 692                 .dev                    = {
 693                         .platform_data  = dm355_serial2_platform_data,
 694                 }
 695         },
 696         {
 697         }
 698 };
 699
 700 static const struct davinci_soc_info davinci_soc_info_dm355 = {
 701         .io_desc                = dm355_io_desc,
 702         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 703         .jtag_id_reg            = 0x01c40028,
 704         .ids                    = dm355_ids,
 705         .ids_num                = ARRAY_SIZE(dm355_ids),
 706         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 707         .pinmux_pins            = dm355_pins,
 708         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 709         .timer_info             = &dm355_timer_info,
 710         .sram_dma               = 0x00010000,
 711         .sram_len               = SZ_32K,
 712 };
 713
 714 void __init dm355_init_asp1(u32 evt_enable)
 715 {
 716         /* we don't use ASP1 IRQs, or we'd need to mux them ... */
 717         if (evt_enable & ASP1_TX_EVT_EN)
 718                 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
 719
 720         if (evt_enable & ASP1_RX_EVT_EN)
 721                 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
 722
 723         platform_device_register(&dm355_asp1_device);
 724 }
 725
 726 void __init dm355_init(void)
 727 {
 728         davinci_common_init(&davinci_soc_info_dm355);
 729         davinci_map_sysmod();
 730 }
 731
 732 void __init dm355_init_time(void)
 733 {
 734         void __iomem *pll1, *psc;
 735         struct clk *clk;
 736
 737         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
 738
 739         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
 740         dm355_pll1_init(NULL, pll1, NULL);
 741
 742         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
 743         dm355_psc_init(NULL, psc);
 744
 745         clk = clk_get(NULL, "timer0");
 746
 747         davinci_timer_init(clk);
 748 }
 749
 750 static struct resource dm355_pll2_resources[] = {
 751         {
 752                 .start  = DAVINCI_PLL2_BASE,
 753                 .end    = DAVINCI_PLL2_BASE + SZ_1K - 1,
 754                 .flags  = IORESOURCE_MEM,
 755         },
 756 };
 757
 758 static struct platform_device dm355_pll2_device = {
 759         .name           = "dm355-pll2",
 760         .id             = -1,
 761         .resource       = dm355_pll2_resources,
 762         .num_resources  = ARRAY_SIZE(dm355_pll2_resources),
 763 };
 764
 765 void __init dm355_register_clocks(void)
 766 {
 767         /* PLL1 and PSC are registered in dm355_init_time() */
 768         platform_device_register(&dm355_pll2_device);
 769 }
 770
 771 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
 772                                 struct vpbe_config *vpbe_cfg)
 773 {
 774         if (vpfe_cfg || vpbe_cfg)
 775                 platform_device_register(&dm355_vpss_device);
 776
 777         if (vpfe_cfg) {
 778                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
 779                 platform_device_register(&dm355_ccdc_dev);
 780                 platform_device_register(&vpfe_capture_dev);
 781         }
 782
 783         if (vpbe_cfg) {
 784                 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
 785                 platform_device_register(&dm355_osd_dev);
 786                 platform_device_register(&dm355_venc_dev);
 787                 platform_device_register(&dm355_vpbe_dev);
 788                 platform_device_register(&dm355_vpbe_display);
 789         }
 790
 791         return 0;
 792 }
 793
 794 static const struct davinci_aintc_config dm355_aintc_config = {
 795         .reg = {
 796                 .start          = DAVINCI_ARM_INTC_BASE,
 797                 .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
 798                 .flags          = IORESOURCE_MEM,
 799         },
 800         .num_irqs               = 64,
 801         .prios                  = dm355_default_priorities,
 802 };
 803
 804 void __init dm355_init_irq(void)
 805 {
 806         davinci_aintc_init(&dm355_aintc_config);
 807 }
 808
 809 static int __init dm355_init_devices(void)
 810 {
 811         struct platform_device *edma_pdev;
 812         int ret = 0;
 813
 814         if (!cpu_is_davinci_dm355())
 815                 return 0;
 816
 817         davinci_cfg_reg(DM355_INT_EDMA_CC);
 818         edma_pdev = platform_device_register_full(&dm355_edma_device);
 819         if (IS_ERR(edma_pdev)) {
 820                 pr_warn("%s: Failed to register eDMA\n", __func__);
 821                 return PTR_ERR(edma_pdev);
 822         }
 823
 824         ret = davinci_init_wdt();
 825         if (ret)
 826                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
 827
 828         return ret;
 829 }
 830 postcore_initcall(dm355_init_devices);