2 * TI Common Platform Interrupt Controller (cp_intc) driver
4 * Author: Steve Chen <schen@mvista.com>
5 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/irq.h>
16 #include <mach/cp_intc.h>
18 static void __iomem *cp_intc_base;
20 static inline unsigned int cp_intc_read(unsigned offset)
22 return __raw_readl(cp_intc_base + offset);
25 static inline void cp_intc_write(unsigned long value, unsigned offset)
27 __raw_writel(value, cp_intc_base + offset);
30 static void cp_intc_ack_irq(unsigned int irq)
32 cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR);
35 /* Disable interrupt */
36 static void cp_intc_mask_irq(unsigned int irq)
38 /* XXX don't know why we need to disable nIRQ here... */
39 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
40 cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR);
41 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
44 /* Enable interrupt */
45 static void cp_intc_unmask_irq(unsigned int irq)
47 cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET);
50 static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
52 unsigned reg = BIT_WORD(irq);
53 unsigned mask = BIT_MASK(irq);
54 unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
55 unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
58 case IRQ_TYPE_EDGE_RISING:
62 case IRQ_TYPE_EDGE_FALLING:
66 case IRQ_TYPE_LEVEL_HIGH:
70 case IRQ_TYPE_LEVEL_LOW:
78 cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
79 cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
84 static struct irq_chip cp_intc_irq_chip = {
86 .ack = cp_intc_ack_irq,
87 .mask = cp_intc_mask_irq,
88 .unmask = cp_intc_unmask_irq,
89 .set_type = cp_intc_set_irq_type,
92 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
95 unsigned num_reg = BITS_TO_LONGS(num_irq);
100 cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
102 /* Disable all host interrupts */
103 cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
105 /* Disable system interrupts */
106 for (i = 0; i < num_reg; i++)
107 cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
109 /* Set to normal mode, no nesting, no priority hold */
110 cp_intc_write(0, CP_INTC_CTRL);
111 cp_intc_write(0, CP_INTC_HOST_CTRL);
113 /* Clear system interrupt status */
114 for (i = 0; i < num_reg; i++)
115 cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
117 /* Enable nIRQ (what about nFIQ?) */
118 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
121 * Priority is determined by host channel: lower channel number has
122 * higher priority i.e. channel 0 has highest priority and channel 31
123 * had the lowest priority.
125 num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
130 for (k = i = 0; i < num_reg; i++) {
131 for (val = j = 0; j < 4; j++, k++) {
134 val |= irq_prio[k] << 24;
137 cp_intc_write(val, CP_INTC_CHAN_MAP(i));
141 * Default everything to channel 15 if priority not specified.
142 * Note that channel 0-1 are mapped to nFIQ and channels 2-31
143 * are mapped to nIRQ.
145 for (i = 0; i < num_reg; i++)
146 cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
149 /* Set up genirq dispatching for cp_intc */
150 for (i = 0; i < num_irq; i++) {
151 set_irq_chip(i, &cp_intc_irq_chip);
152 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
153 set_irq_handler(i, handle_edge_irq);
156 /* Enable global interrupt */
157 cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);