2 * Clock and PLL control for DaVinci devices
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/mutex.h>
21 #include <linux/delay.h>
23 #include <mach/hardware.h>
25 #include <mach/clock.h>
27 #include <mach/cputype.h>
30 static LIST_HEAD(clocks);
31 static DEFINE_MUTEX(clocks_mutex);
32 static DEFINE_SPINLOCK(clockfw_lock);
34 static void __clk_enable(struct clk *clk)
37 __clk_enable(clk->parent);
38 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
39 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
43 static void __clk_disable(struct clk *clk)
45 if (WARN_ON(clk->usecount == 0))
47 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
48 (clk->flags & CLK_PSC))
49 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
52 __clk_disable(clk->parent);
55 int davinci_clk_reset(struct clk *clk, bool reset)
59 if (clk == NULL || IS_ERR(clk))
62 spin_lock_irqsave(&clockfw_lock, flags);
63 if (clk->flags & CLK_PSC)
64 davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
65 spin_unlock_irqrestore(&clockfw_lock, flags);
69 EXPORT_SYMBOL(davinci_clk_reset);
71 int davinci_clk_reset_assert(struct clk *clk)
73 if (clk == NULL || IS_ERR(clk) || !clk->reset)
76 return clk->reset(clk, true);
78 EXPORT_SYMBOL(davinci_clk_reset_assert);
80 int davinci_clk_reset_deassert(struct clk *clk)
82 if (clk == NULL || IS_ERR(clk) || !clk->reset)
85 return clk->reset(clk, false);
87 EXPORT_SYMBOL(davinci_clk_reset_deassert);
89 int clk_enable(struct clk *clk)
93 if (clk == NULL || IS_ERR(clk))
96 spin_lock_irqsave(&clockfw_lock, flags);
98 spin_unlock_irqrestore(&clockfw_lock, flags);
102 EXPORT_SYMBOL(clk_enable);
104 void clk_disable(struct clk *clk)
108 if (clk == NULL || IS_ERR(clk))
111 spin_lock_irqsave(&clockfw_lock, flags);
113 spin_unlock_irqrestore(&clockfw_lock, flags);
115 EXPORT_SYMBOL(clk_disable);
117 unsigned long clk_get_rate(struct clk *clk)
119 if (clk == NULL || IS_ERR(clk))
124 EXPORT_SYMBOL(clk_get_rate);
126 long clk_round_rate(struct clk *clk, unsigned long rate)
128 if (clk == NULL || IS_ERR(clk))
132 return clk->round_rate(clk, rate);
136 EXPORT_SYMBOL(clk_round_rate);
138 /* Propagate rate to children */
139 static void propagate_rate(struct clk *root)
143 list_for_each_entry(clk, &root->children, childnode) {
145 clk->rate = clk->recalc(clk);
150 int clk_set_rate(struct clk *clk, unsigned long rate)
155 if (clk == NULL || IS_ERR(clk))
159 ret = clk->set_rate(clk, rate);
161 spin_lock_irqsave(&clockfw_lock, flags);
164 clk->rate = clk->recalc(clk);
167 spin_unlock_irqrestore(&clockfw_lock, flags);
171 EXPORT_SYMBOL(clk_set_rate);
173 int clk_set_parent(struct clk *clk, struct clk *parent)
177 if (clk == NULL || IS_ERR(clk))
180 /* Cannot change parent on enabled clock */
181 if (WARN_ON(clk->usecount))
184 mutex_lock(&clocks_mutex);
185 clk->parent = parent;
186 list_del_init(&clk->childnode);
187 list_add(&clk->childnode, &clk->parent->children);
188 mutex_unlock(&clocks_mutex);
190 spin_lock_irqsave(&clockfw_lock, flags);
192 clk->rate = clk->recalc(clk);
194 spin_unlock_irqrestore(&clockfw_lock, flags);
198 EXPORT_SYMBOL(clk_set_parent);
200 int clk_register(struct clk *clk)
202 if (clk == NULL || IS_ERR(clk))
205 if (WARN(clk->parent && !clk->parent->rate,
206 "CLK: %s parent %s has no rate!\n",
207 clk->name, clk->parent->name))
210 INIT_LIST_HEAD(&clk->children);
212 mutex_lock(&clocks_mutex);
213 list_add_tail(&clk->node, &clocks);
215 list_add_tail(&clk->childnode, &clk->parent->children);
216 mutex_unlock(&clocks_mutex);
218 /* If rate is already set, use it */
222 /* Else, see if there is a way to calculate it */
224 clk->rate = clk->recalc(clk);
226 /* Otherwise, default to parent rate */
227 else if (clk->parent)
228 clk->rate = clk->parent->rate;
232 EXPORT_SYMBOL(clk_register);
234 void clk_unregister(struct clk *clk)
236 if (clk == NULL || IS_ERR(clk))
239 mutex_lock(&clocks_mutex);
240 list_del(&clk->node);
241 list_del(&clk->childnode);
242 mutex_unlock(&clocks_mutex);
244 EXPORT_SYMBOL(clk_unregister);
246 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
248 * Disable any unused clocks left on by the bootloader
250 int __init davinci_clk_disable_unused(void)
254 spin_lock_irq(&clockfw_lock);
255 list_for_each_entry(ck, &clocks, node) {
256 if (ck->usecount > 0)
258 if (!(ck->flags & CLK_PSC))
261 /* ignore if in Disabled or SwRstDisable states */
262 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
265 pr_debug("Clocks: disable unused %s\n", ck->name);
267 davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
270 spin_unlock_irq(&clockfw_lock);
276 static unsigned long clk_sysclk_recalc(struct clk *clk)
279 struct pll_data *pll;
280 unsigned long rate = clk->rate;
282 /* If this is the PLL base clock, no more calculations needed */
286 if (WARN_ON(!clk->parent))
289 rate = clk->parent->rate;
291 /* Otherwise, the parent must be a PLL */
292 if (WARN_ON(!clk->parent->pll_data))
295 pll = clk->parent->pll_data;
297 /* If pre-PLL, source clock is before the multiplier and divider(s) */
298 if (clk->flags & PRE_PLL)
299 rate = pll->input_rate;
304 v = __raw_readl(pll->base + clk->div_reg);
306 plldiv = (v & pll->div_ratio_mask) + 1;
314 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
317 struct pll_data *pll;
321 /* If this is the PLL base clock, wrong function to call */
325 /* There must be a parent... */
326 if (WARN_ON(!clk->parent))
329 /* ... the parent must be a PLL... */
330 if (WARN_ON(!clk->parent->pll_data))
333 /* ... and this clock must have a divider. */
334 if (WARN_ON(!clk->div_reg))
337 pll = clk->parent->pll_data;
339 input = clk->parent->rate;
341 /* If pre-PLL, source clock is before the multiplier and divider(s) */
342 if (clk->flags & PRE_PLL)
343 input = pll->input_rate;
347 * Can afford to provide an output little higher than requested
348 * only if maximum rate supported by hardware on this sysclk
352 ratio = DIV_ROUND_CLOSEST(input, rate);
353 if (input / ratio > clk->maxrate)
358 ratio = DIV_ROUND_UP(input, rate);
363 if (ratio > pll->div_ratio_mask)
367 v = __raw_readl(pll->base + PLLSTAT);
368 } while (v & PLLSTAT_GOSTAT);
370 v = __raw_readl(pll->base + clk->div_reg);
371 v &= ~pll->div_ratio_mask;
372 v |= ratio | PLLDIV_EN;
373 __raw_writel(v, pll->base + clk->div_reg);
375 v = __raw_readl(pll->base + PLLCMD);
377 __raw_writel(v, pll->base + PLLCMD);
380 v = __raw_readl(pll->base + PLLSTAT);
381 } while (v & PLLSTAT_GOSTAT);
385 EXPORT_SYMBOL(davinci_set_sysclk_rate);
387 static unsigned long clk_leafclk_recalc(struct clk *clk)
389 if (WARN_ON(!clk->parent))
392 return clk->parent->rate;
395 int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
401 static unsigned long clk_pllclk_recalc(struct clk *clk)
403 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
405 struct pll_data *pll = clk->pll_data;
406 unsigned long rate = clk->rate;
408 ctrl = __raw_readl(pll->base + PLLCTL);
409 rate = pll->input_rate = clk->parent->rate;
411 if (ctrl & PLLCTL_PLLEN) {
413 mult = __raw_readl(pll->base + PLLM);
414 if (cpu_is_davinci_dm365())
415 mult = 2 * (mult & PLLM_PLLM_MASK);
417 mult = (mult & PLLM_PLLM_MASK) + 1;
421 if (pll->flags & PLL_HAS_PREDIV) {
422 prediv = __raw_readl(pll->base + PREDIV);
423 if (prediv & PLLDIV_EN)
424 prediv = (prediv & pll->div_ratio_mask) + 1;
429 /* pre-divider is fixed, but (some?) chips won't report that */
430 if (cpu_is_davinci_dm355() && pll->num == 1)
433 if (pll->flags & PLL_HAS_POSTDIV) {
434 postdiv = __raw_readl(pll->base + POSTDIV);
435 if (postdiv & PLLDIV_EN)
436 postdiv = (postdiv & pll->div_ratio_mask) + 1;
447 pr_debug("PLL%d: input = %lu MHz [ ",
448 pll->num, clk->parent->rate / 1000000);
452 pr_debug("/ %d ", prediv);
454 pr_debug("* %d ", mult);
456 pr_debug("/ %d ", postdiv);
457 pr_debug("] --> %lu MHz output.\n", rate / 1000000);
463 * davinci_set_pllrate - set the output rate of a given PLL.
465 * Note: Currently tested to work with OMAP-L138 only.
467 * @pll: pll whose rate needs to be changed.
468 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
469 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
470 * @postdiv: The post divider value. Passing 0 disables the post-divider.
472 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
473 unsigned int mult, unsigned int postdiv)
476 unsigned int locktime;
479 if (pll->base == NULL)
483 * PLL lock time required per OMAP-L138 datasheet is
484 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
485 * as 4 and OSCIN cycle as 25 MHz.
488 locktime = ((2000 * prediv) / 100);
489 prediv = (prediv - 1) | PLLDIV_EN;
491 locktime = PLL_LOCK_TIME;
494 postdiv = (postdiv - 1) | PLLDIV_EN;
498 /* Protect against simultaneous calls to PLL setting seqeunce */
499 spin_lock_irqsave(&clockfw_lock, flags);
501 ctrl = __raw_readl(pll->base + PLLCTL);
503 /* Switch the PLL to bypass mode */
504 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
505 __raw_writel(ctrl, pll->base + PLLCTL);
507 udelay(PLL_BYPASS_TIME);
509 /* Reset and enable PLL */
510 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
511 __raw_writel(ctrl, pll->base + PLLCTL);
513 if (pll->flags & PLL_HAS_PREDIV)
514 __raw_writel(prediv, pll->base + PREDIV);
516 __raw_writel(mult, pll->base + PLLM);
518 if (pll->flags & PLL_HAS_POSTDIV)
519 __raw_writel(postdiv, pll->base + POSTDIV);
521 udelay(PLL_RESET_TIME);
523 /* Bring PLL out of reset */
524 ctrl |= PLLCTL_PLLRST;
525 __raw_writel(ctrl, pll->base + PLLCTL);
529 /* Remove PLL from bypass mode */
530 ctrl |= PLLCTL_PLLEN;
531 __raw_writel(ctrl, pll->base + PLLCTL);
533 spin_unlock_irqrestore(&clockfw_lock, flags);
537 EXPORT_SYMBOL(davinci_set_pllrate);
540 * davinci_set_refclk_rate() - Set the reference clock rate
541 * @rate: The new rate.
543 * Sets the reference clock rate to a given value. This will most likely
544 * result in the entire clock tree getting updated.
546 * This is used to support boards which use a reference clock different
547 * than that used by default in <soc>.c file. The reference clock rate
548 * should be updated early in the boot process; ideally soon after the
549 * clock tree has been initialized once with the default reference clock
550 * rate (davinci_common_init()).
552 * Returns 0 on success, error otherwise.
554 int davinci_set_refclk_rate(unsigned long rate)
558 refclk = clk_get(NULL, "ref");
559 if (IS_ERR(refclk)) {
560 pr_err("%s: failed to get reference clock.\n", __func__);
561 return PTR_ERR(refclk);
564 clk_set_rate(refclk, rate);
571 int __init davinci_clk_init(struct clk_lookup *clocks)
573 struct clk_lookup *c;
575 size_t num_clocks = 0;
577 for (c = clocks; c->clk; c++) {
582 /* Check if clock is a PLL */
584 clk->recalc = clk_pllclk_recalc;
586 /* Else, if it is a PLL-derived clock */
587 else if (clk->flags & CLK_PLL)
588 clk->recalc = clk_sysclk_recalc;
590 /* Otherwise, it is a leaf clock (PSC clock) */
591 else if (clk->parent)
592 clk->recalc = clk_leafclk_recalc;
596 struct pll_data *pll = clk->pll_data;
598 if (!pll->div_ratio_mask)
599 pll->div_ratio_mask = PLLDIV_RATIO_MASK;
601 if (pll->phys_base && !pll->base) {
602 pll->base = ioremap(pll->phys_base, SZ_4K);
608 clk->rate = clk->recalc(clk);
611 clk->flags |= CLK_PSC;
613 if (clk->flags & PSC_LRST)
614 clk->reset = davinci_clk_reset;
619 /* Turn on clocks that Linux doesn't otherwise manage */
620 if (clk->flags & ALWAYS_ENABLED)
624 clkdev_add_table(clocks, num_clocks);
629 #ifdef CONFIG_DEBUG_FS
631 #include <linux/debugfs.h>
632 #include <linux/seq_file.h>
634 #define CLKNAME_MAX 10 /* longest clock name */
639 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
642 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
646 if (parent->flags & CLK_PLL)
648 else if (parent->flags & CLK_PSC)
653 /* <nest spaces> name <pad to end> */
654 memset(buf, ' ', sizeof(buf) - 1);
655 buf[sizeof(buf) - 1] = 0;
656 i = strlen(parent->name);
657 memcpy(buf + nest, parent->name,
658 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
660 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
661 buf, parent->usecount, state, clk_get_rate(parent));
662 /* REVISIT show device associations too */
664 /* cost is now small, but not linear... */
665 list_for_each_entry(clk, &parent->children, childnode) {
666 dump_clock(s, nest + NEST_DELTA, clk);
670 static int davinci_ck_show(struct seq_file *m, void *v)
675 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
677 mutex_lock(&clocks_mutex);
678 list_for_each_entry(clk, &clocks, node)
680 dump_clock(m, 0, clk);
681 mutex_unlock(&clocks_mutex);
686 static int davinci_ck_open(struct inode *inode, struct file *file)
688 return single_open(file, davinci_ck_show, NULL);
691 static const struct file_operations davinci_ck_operations = {
692 .open = davinci_ck_open,
695 .release = single_release,
698 static int __init davinci_clk_debugfs_init(void)
700 debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
701 &davinci_ck_operations);
705 device_initcall(davinci_clk_debugfs_init);
706 #endif /* CONFIG_DEBUG_FS */