arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #define pr_fmt(fmt)     "AT91: " fmt
   9
  10 #include <linux/module.h>
  11 #include <linux/io.h>
  12 #include <linux/mm.h>
  13 #include <linux/pm.h>
  14 #include <linux/of_address.h>
  15 #include <linux/pinctrl/machine.h>
  16 #include <linux/clk/at91_pmc.h>
  17
  18 #include <asm/system_misc.h>
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/cpu.h>
  23 #include <mach/at91_dbgu.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "pm.h"
  28
  29 struct at91_init_soc __initdata at91_boot_soc;
  30
  31 struct at91_socinfo at91_soc_initdata;
  32 EXPORT_SYMBOL(at91_soc_initdata);
  33
  34 void __init at91rm9200_set_type(int type)
  35 {
  36         if (type == ARCH_REVISON_9200_PQFP)
  37                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  38         else
  39                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  40
  41         pr_info("filled in soc subtype: %s\n",
  42                 at91_get_soc_subtype(&at91_soc_initdata));
  43 }
  44
  45 void __init at91_init_irq_default(void)
  46 {
  47         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  48 }
  49
  50 void __init at91_init_interrupts(unsigned int *priority)
  51 {
  52         /* Initialize the AIC interrupt controller */
  53         if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
  54                 at91_aic_init(priority, at91_boot_soc.extern_irq);
  55
  56         /* Enable GPIO interrupts */
  57         at91_gpio_irq_setup();
  58 }
  59
  60 void __iomem *at91_ramc_base[2];
  61 EXPORT_SYMBOL_GPL(at91_ramc_base);
  62
  63 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  64 {
  65         if (id < 0 || id > 1) {
  66                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  67                 BUG();
  68         }
  69         at91_ramc_base[id] = ioremap(addr, size);
  70         if (!at91_ramc_base[id])
  71                 panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
  72 }
  73
  74 static struct map_desc sram_desc[2] __initdata;
  75
  76 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  77 {
  78         struct map_desc *desc = &sram_desc[bank];
  79
  80         desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
  81         if (bank > 0)
  82                 desc->virtual -= sram_desc[bank - 1].length;
  83
  84         desc->pfn = __phys_to_pfn(base);
  85         desc->length = length;
  86         desc->type = MT_MEMORY_RWX_NONCACHED;
  87
  88         pr_info("sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  89                 base, length, desc->virtual);
  90
  91         iotable_init(desc, 1);
  92 }
  93
  94 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  95         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  96         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  97         .length         = SZ_16K,
  98         .type           = MT_DEVICE,
  99 };
 100
 101 static void __init soc_detect(u32 dbgu_base)
 102 {
 103         u32 cidr, socid;
 104
 105         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 106         socid = cidr & ~AT91_CIDR_VERSION;
 107
 108         switch (socid) {
 109         case ARCH_ID_AT91RM9200:
 110                 at91_soc_initdata.type = AT91_SOC_RM9200;
 111                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
 112                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
 113                 at91_boot_soc = at91rm9200_soc;
 114                 break;
 115
 116         case ARCH_ID_AT91SAM9260:
 117                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 118                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 119                 at91_boot_soc = at91sam9260_soc;
 120                 break;
 121
 122         case ARCH_ID_AT91SAM9261:
 123                 at91_soc_initdata.type = AT91_SOC_SAM9261;
 124                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 125                 at91_boot_soc = at91sam9261_soc;
 126                 break;
 127
 128         case ARCH_ID_AT91SAM9263:
 129                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 130                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 131                 at91_boot_soc = at91sam9263_soc;
 132                 break;
 133
 134         case ARCH_ID_AT91SAM9G20:
 135                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 136                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 137                 at91_boot_soc = at91sam9260_soc;
 138                 break;
 139
 140         case ARCH_ID_AT91SAM9G45:
 141                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 142                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 143                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 144                 at91_boot_soc = at91sam9g45_soc;
 145                 break;
 146
 147         case ARCH_ID_AT91SAM9RL64:
 148                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 149                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 150                 at91_boot_soc = at91sam9rl_soc;
 151                 break;
 152
 153         case ARCH_ID_AT91SAM9X5:
 154                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 155                 at91_boot_soc = at91sam9x5_soc;
 156                 break;
 157
 158         case ARCH_ID_AT91SAM9N12:
 159                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 160                 at91_boot_soc = at91sam9n12_soc;
 161                 break;
 162
 163         case ARCH_ID_SAMA5D3:
 164                 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 165                 at91_boot_soc = sama5d3_soc;
 166                 break;
 167         }
 168
 169         /* at91sam9g10 */
 170         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 171                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 172                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 173                 at91_boot_soc = at91sam9261_soc;
 174         }
 175         /* at91sam9xe */
 176         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 177                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 178                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 179                 at91_boot_soc = at91sam9260_soc;
 180         }
 181
 182         if (!at91_soc_is_detected())
 183                 return;
 184
 185         at91_soc_initdata.cidr = cidr;
 186
 187         /* sub version of soc */
 188         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 189
 190         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 191                 switch (at91_soc_initdata.exid) {
 192                 case ARCH_EXID_AT91SAM9M10:
 193                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 194                         break;
 195                 case ARCH_EXID_AT91SAM9G46:
 196                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 197                         break;
 198                 case ARCH_EXID_AT91SAM9M11:
 199                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 200                         break;
 201                 }
 202         }
 203
 204         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 205                 switch (at91_soc_initdata.exid) {
 206                 case ARCH_EXID_AT91SAM9G15:
 207                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 208                         break;
 209                 case ARCH_EXID_AT91SAM9G35:
 210                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 211                         break;
 212                 case ARCH_EXID_AT91SAM9X35:
 213                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 214                         break;
 215                 case ARCH_EXID_AT91SAM9G25:
 216                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 217                         break;
 218                 case ARCH_EXID_AT91SAM9X25:
 219                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 220                         break;
 221                 }
 222         }
 223
 224         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
 225                 switch (at91_soc_initdata.exid) {
 226                 case ARCH_EXID_SAMA5D31:
 227                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
 228                         break;
 229                 case ARCH_EXID_SAMA5D33:
 230                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
 231                         break;
 232                 case ARCH_EXID_SAMA5D34:
 233                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
 234                         break;
 235                 case ARCH_EXID_SAMA5D35:
 236                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
 237                         break;
 238                 case ARCH_EXID_SAMA5D36:
 239                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 240                         break;
 241                 }
 242         }
 243 }
 244
 245 static const char *soc_name[] = {
 246         [AT91_SOC_RM9200]       = "at91rm9200",
 247         [AT91_SOC_SAM9260]      = "at91sam9260",
 248         [AT91_SOC_SAM9261]      = "at91sam9261",
 249         [AT91_SOC_SAM9263]      = "at91sam9263",
 250         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 251         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 252         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 253         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 254         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 255         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 256         [AT91_SOC_SAMA5D3]      = "sama5d3",
 257         [AT91_SOC_UNKNOWN]      = "Unknown",
 258 };
 259
 260 const char *at91_get_soc_type(struct at91_socinfo *c)
 261 {
 262         return soc_name[c->type];
 263 }
 264 EXPORT_SYMBOL(at91_get_soc_type);
 265
 266 static const char *soc_subtype_name[] = {
 267         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 268         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 269         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 270         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 271         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 272         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 273         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 274         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 275         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 276         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 277         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 278         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 279         [AT91_SOC_SAMA5D31]     = "sama5d31",
 280         [AT91_SOC_SAMA5D33]     = "sama5d33",
 281         [AT91_SOC_SAMA5D34]     = "sama5d34",
 282         [AT91_SOC_SAMA5D35]     = "sama5d35",
 283         [AT91_SOC_SAMA5D36]     = "sama5d36",
 284         [AT91_SOC_SUBTYPE_NONE] = "None",
 285         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 286 };
 287
 288 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 289 {
 290         return soc_subtype_name[c->subtype];
 291 }
 292 EXPORT_SYMBOL(at91_get_soc_subtype);
 293
 294 void __init at91_map_io(void)
 295 {
 296         /* Map peripherals */
 297         iotable_init(&at91_io_desc, 1);
 298
 299         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 300         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 301
 302         soc_detect(AT91_BASE_DBGU0);
 303         if (!at91_soc_is_detected())
 304                 soc_detect(AT91_BASE_DBGU1);
 305
 306         if (!at91_soc_is_detected())
 307                 panic(pr_fmt("Impossible to detect the SOC type"));
 308
 309         pr_info("Detected soc type: %s\n",
 310                 at91_get_soc_type(&at91_soc_initdata));
 311         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 312                 pr_info("Detected soc subtype: %s\n",
 313                         at91_get_soc_subtype(&at91_soc_initdata));
 314
 315         if (!at91_soc_is_enabled())
 316                 panic(pr_fmt("Soc not enabled"));
 317
 318         if (at91_boot_soc.map_io)
 319                 at91_boot_soc.map_io();
 320 }
 321
 322 void __iomem *at91_matrix_base;
 323 EXPORT_SYMBOL_GPL(at91_matrix_base);
 324
 325 void __init at91_ioremap_matrix(u32 base_addr)
 326 {
 327         at91_matrix_base = ioremap(base_addr, 512);
 328         if (!at91_matrix_base)
 329                 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
 330 }
 331
 332 #if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
 333 static struct of_device_id ramc_ids[] = {
 334         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
 335         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
 336         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
 337         { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
 338         { /*sentinel*/ }
 339 };
 340
 341 static void at91_dt_ramc(void)
 342 {
 343         struct device_node *np;
 344         const struct of_device_id *of_id;
 345         int idx = 0;
 346
 347         for_each_matching_node(np, ramc_ids) {
 348                 at91_ramc_base[idx] = of_iomap(np, 0);
 349                 if (!at91_ramc_base[idx])
 350                         panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
 351
 352                 idx++;
 353         }
 354
 355         if (!idx)
 356                 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
 357
 358         of_id = of_match_node(ramc_ids, np);
 359         if (!of_id) {
 360                 pr_warn("ramc no standby function available\n");
 361                 return;
 362         }
 363
 364         at91_pm_set_standby(of_id->data);
 365 }
 366
 367 void __init at91rm9200_dt_initialize(void)
 368 {
 369         at91_dt_ramc();
 370
 371         /* Init clock subsystem */
 372         at91_dt_clock_init();
 373
 374         /* Register the processor-specific clocks */
 375         if (at91_boot_soc.register_clocks)
 376                 at91_boot_soc.register_clocks();
 377
 378         at91_boot_soc.init();
 379 }
 380
 381 void __init at91_dt_initialize(void)
 382 {
 383         at91_dt_ramc();
 384
 385         /* Init clock subsystem */
 386         at91_dt_clock_init();
 387
 388         /* Register the processor-specific clocks */
 389         if (at91_boot_soc.register_clocks)
 390                 at91_boot_soc.register_clocks();
 391
 392         if (at91_boot_soc.init)
 393                 at91_boot_soc.init();
 394 }
 395 #endif
 396
 397 void __init at91_initialize(unsigned long main_clock)
 398 {
 399         at91_boot_soc.ioremap_registers();
 400
 401         /* Init clock subsystem */
 402         at91_clock_init(main_clock);
 403
 404         /* Register the processor-specific clocks */
 405         at91_boot_soc.register_clocks();
 406
 407         at91_boot_soc.init();
 408
 409         pinctrl_provide_dummies();
 410 }
 411
 412 void __init at91_register_devices(void)
 413 {
 414         at91_boot_soc.register_devices();
 415 }