4 * This file is based on arm realview smp platform.
6 * Copyright 2012 Actions Semi Inc.
7 * Author: Actions Semi, Inc.
9 * Copyright (c) 2017 Andreas Färber
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/delay.h>
20 #include <linux/of_address.h>
21 #include <linux/smp.h>
22 #include <linux/soc/actions/owl-sps.h>
23 #include <asm/cacheflush.h>
24 #include <asm/smp_plat.h>
25 #include <asm/smp_scu.h>
27 #define OWL_CPU1_ADDR 0x50
28 #define OWL_CPU1_FLAG 0x5c
30 #define OWL_CPUx_FLAG_BOOT 0x55aa
32 #define OWL_SPS_PG_CTL_PWR_CPU2 BIT(5)
33 #define OWL_SPS_PG_CTL_PWR_CPU3 BIT(6)
34 #define OWL_SPS_PG_CTL_ACK_CPU2 BIT(21)
35 #define OWL_SPS_PG_CTL_ACK_CPU3 BIT(22)
37 static void __iomem *scu_base_addr;
38 static void __iomem *sps_base_addr;
39 static void __iomem *timer_base_addr;
42 static int s500_wakeup_secondary(unsigned int cpu)
49 /* The generic PM domain driver is not available this early. */
52 ret = owl_sps_set_pg(sps_base_addr,
53 OWL_SPS_PG_CTL_PWR_CPU2,
54 OWL_SPS_PG_CTL_ACK_CPU2, true);
59 ret = owl_sps_set_pg(sps_base_addr,
60 OWL_SPS_PG_CTL_PWR_CPU3,
61 OWL_SPS_PG_CTL_ACK_CPU3, true);
67 /* wait for CPUx to run to WFE instruction */
70 writel(__pa_symbol(secondary_startup),
71 timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
72 writel(OWL_CPUx_FLAG_BOOT,
73 timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
81 static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
85 ret = s500_wakeup_secondary(cpu);
91 smp_send_reschedule(cpu);
93 writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
94 writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
99 static void __init s500_smp_prepare_cpus(unsigned int max_cpus)
101 struct device_node *node;
103 node = of_find_compatible_node(NULL, NULL, "actions,s500-timer");
105 pr_err("%s: missing timer\n", __func__);
109 timer_base_addr = of_iomap(node, 0);
110 if (!timer_base_addr) {
111 pr_err("%s: could not map timer registers\n", __func__);
115 node = of_find_compatible_node(NULL, NULL, "actions,s500-sps");
117 pr_err("%s: missing sps\n", __func__);
121 sps_base_addr = of_iomap(node, 0);
122 if (!sps_base_addr) {
123 pr_err("%s: could not map sps registers\n", __func__);
127 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
128 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
130 pr_err("%s: missing scu\n", __func__);
134 scu_base_addr = of_iomap(node, 0);
135 if (!scu_base_addr) {
136 pr_err("%s: could not map scu registers\n", __func__);
141 * While the number of cpus is gathered from dt, also get the
142 * number of cores from the scu to verify this value when
145 ncores = scu_get_core_count(scu_base_addr);
146 pr_debug("%s: ncores %d\n", __func__, ncores);
148 scu_enable(scu_base_addr);
152 static const struct smp_operations s500_smp_ops __initconst = {
153 .smp_prepare_cpus = s500_smp_prepare_cpus,
154 .smp_boot_secondary = s500_smp_boot_secondary,
156 CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops);