2 * Copyright (c) 2012 Linaro Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/init.h>
20 #include <linux/irqchip/arm-gic-v3.h>
21 #include <linux/linkage.h>
22 #include <asm/assembler.h>
25 #define HVC_GET_VECTORS 0
26 #define HVC_SET_VECTORS 1
30 * For the kernel proper, we need to find out the CPU boot mode long after
31 * boot, so we need to store it in a writable variable.
33 * This is not in .bss, because we set it sufficiently early that the boot-time
34 * zeroing of .bss would clobber it.
37 ENTRY(__boot_cpu_mode)
42 * Save the primary CPU boot mode. Requires 3 scratch registers.
44 .macro store_primary_cpu_mode reg1, reg2, reg3
46 and \reg1, \reg1, #MODE_MASK
47 adr \reg2, .L__boot_cpu_mode_offset
49 str \reg1, [\reg2, \reg3]
53 * Compare the current mode with the one saved on the primary CPU.
54 * If they don't match, record that fact. The Z bit indicates
55 * if there's a match or not.
56 * Requires 3 additionnal scratch registers.
58 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
59 adr \reg2, .L__boot_cpu_mode_offset
61 ldr \reg1, [\reg2, \reg3]
62 cmp \mode, \reg1 @ matches primary CPU boot mode?
63 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
64 strne \reg1, [\reg2, \reg3] @ record what happened and give up
69 .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req
73 * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
74 * consistency checking:
76 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
83 * Hypervisor stub installation functions.
85 * These must be called with the MMU and D-cache off.
86 * They are not ABI compliant and are only intended to be called from the kernel
87 * entry points in head.S.
89 @ Call this from the primary CPU
90 ENTRY(__hyp_stub_install)
91 store_primary_cpu_mode r4, r5, r6
92 ENDPROC(__hyp_stub_install)
96 @ Secondary CPUs should call here
97 ENTRY(__hyp_stub_install_secondary)
99 and r4, r4, #MODE_MASK
102 * If the secondary has booted with a different mode, give up
105 compare_cpu_mode_with_primary r4, r5, r6, r7
109 * Once we have given up on one CPU, we do not try to install the
110 * stub hypervisor on the remaining ones: because the saved boot mode
111 * is modified, it can't compare equal to the CPSR mode field any
118 retne lr @ give up if the CPU is not in HYP mode
121 * Configure HSCTLR to set correct exception endianness/instruction set
124 * Eventually, CPU-specific code might be needed -- assume not for now
126 * This code relies on the "eret" instruction to synchronize the
127 * various coprocessor accesses. This is done when we switch to SVC
128 * (see safe_svcmode_maskall).
130 @ Now install the hypervisor stub:
131 adr r7, __hyp_stub_vectors
132 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
134 @ Disable all traps, so we don't get any nasty surprise
136 mcr p15, 4, r7, c1, c1, 0 @ HCR
137 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
138 mcr p15, 4, r7, c1, c1, 3 @ HSTR
140 THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
141 ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
142 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
144 mrc p15, 4, r7, c1, c1, 1 @ HDCR
145 and r7, #0x1f @ Preserve HPMN
146 mcr p15, 4, r7, c1, c1, 1 @ HDCR
148 @ Make sure NS-SVC is initialised appropriately
149 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
150 orr r7, #(1 << 5) @ CP15 barriers enabled
151 bic r7, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7)
152 bic r7, #(3 << 19) @ WXN and UWXN disabled
153 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
155 mrc p15, 0, r7, c0, c0, 0 @ MIDR
156 mcr p15, 4, r7, c0, c0, 0 @ VPIDR
158 mrc p15, 0, r7, c0, c0, 5 @ MPIDR
159 mcr p15, 4, r7, c0, c0, 5 @ VMPIDR
161 #if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
162 @ make CNTP_* and CNTPCT accessible from PL1
163 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
168 mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
169 orr r7, r7, #3 @ PL1PCEN | PL1PCTEN
170 mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL
172 mcrr p15, 4, r7, r7, c14 @ CNTVOFF
174 @ Disable virtual timer in case it was counting
175 mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
176 bic r7, #1 @ Clear ENABLE
177 mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL
181 #ifdef CONFIG_ARM_GIC_V3
182 @ Check whether GICv3 system registers are available
183 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
188 @ Enable system register accesses
189 mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
190 orr r7, r7, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
191 mcr p15, 4, r7, c12, c9, 5 @ ICC_HSRE
194 @ SRE bit could be forced to 0 by firmware.
195 @ Check whether it sticks before accessing any other sysreg
196 mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
197 tst r7, #ICC_SRE_EL2_SRE
200 mcr p15, 4, r7, c12, c11, 0 @ ICH_HCR
204 bx lr @ The boot CPU mode is left in r4.
205 ENDPROC(__hyp_stub_install_secondary)
208 teq r0, #HVC_GET_VECTORS
210 mrc p15, 4, r0, c12, c0, 0 @ get HVBAR
213 1: teq r0, #HVC_SET_VECTORS
215 mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
222 ENDPROC(__hyp_stub_do_trap)
225 * __hyp_set_vectors: Call this after boot to set the initial hypervisor
226 * vectors as part of hypervisor installation. On an SMP system, this should
227 * be called on each CPU.
229 * r0 must be the physical address of the new vector table (which must lie in
230 * the bottom 4GB of physical address space.
232 * r0 must be 32-byte aligned.
234 * Before calling this, you must check that the stub hypervisor is installed
235 * everywhere, by waiting for any secondary CPUs to be brought up and then
236 * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
238 * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
239 * something else went wrong... in such cases, trying to install a new
240 * hypervisor is unlikely to work as desired.
242 * When you call into your shiny new hypervisor, sp_hyp will contain junk,
243 * so you will need to set that to something sensible at the new hypervisor's
244 * initialisation entry point.
246 ENTRY(__hyp_get_vectors)
247 mov r0, #HVC_GET_VECTORS
250 ENDPROC(__hyp_get_vectors)
252 ENTRY(__hyp_set_vectors)
254 mov r0, #HVC_SET_VECTORS
257 ENDPROC(__hyp_set_vectors)
261 .L__boot_cpu_mode_offset:
262 .long __boot_cpu_mode - .
267 __hyp_stub_reset: W(b) .
268 __hyp_stub_und: W(b) .
269 __hyp_stub_svc: W(b) .
270 __hyp_stub_pabort: W(b) .
271 __hyp_stub_dabort: W(b) .
272 __hyp_stub_trap: W(b) __hyp_stub_do_trap
273 __hyp_stub_irq: W(b) .
274 __hyp_stub_fiq: W(b) .
275 ENDPROC(__hyp_stub_vectors)