1 #ifndef __ASM_SPINLOCK_H
2 #define __ASM_SPINLOCK_H
4 #if __LINUX_ARM_ARCH__ < 6
5 #error SMP not supported on pre-ARMv6 CPUs
8 #include <linux/prefetch.h>
9 #include <asm/barrier.h>
10 #include <asm/processor.h>
13 * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K
14 * extensions, so when running on UP, we have to patch these instructions away.
16 #ifdef CONFIG_THUMB2_KERNEL
18 * For Thumb-2, special care is needed to ensure that the conditional WFE
19 * instruction really does assemble to exactly 4 bytes (as required by
20 * the SMP_ON_UP fixup code). By itself "wfene" might cause the
21 * assembler to insert a extra (16-bit) IT instruction, depending on the
22 * presence or absence of neighbouring conditional instructions.
24 * To avoid this unpredictableness, an approprite IT is inserted explicitly:
25 * the assembler won't change IT instructions which are explicitly present
28 #define WFE(cond) __ALT_SMP_ASM( \
35 #define WFE(cond) __ALT_SMP_ASM("wfe" cond, "nop")
38 #define SEV __ALT_SMP_ASM(WASM(sev), WASM(nop))
40 static inline void dsb_sev(void)
48 * ARMv6 ticket-based spin-locking.
50 * A memory barrier is required after we get a lock, and before we
51 * release it, because V6 CPUs are assumed to have weakly ordered
55 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
57 u16 owner = READ_ONCE(lock->tickets.owner);
60 arch_spinlock_t tmp = READ_ONCE(*lock);
62 if (tmp.tickets.owner == tmp.tickets.next ||
63 tmp.tickets.owner != owner)
68 smp_acquire__after_ctrl_dep();
71 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
73 static inline void arch_spin_lock(arch_spinlock_t *lock)
77 arch_spinlock_t lockval;
79 prefetchw(&lock->slock);
83 " strex %2, %1, [%3]\n"
86 : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
87 : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
90 while (lockval.tickets.next != lockval.tickets.owner) {
92 lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
98 static inline int arch_spin_trylock(arch_spinlock_t *lock)
100 unsigned long contended, res;
103 prefetchw(&lock->slock);
105 __asm__ __volatile__(
108 " subs %1, %0, %0, ror #16\n"
109 " addeq %0, %0, %4\n"
110 " strexeq %2, %0, [%3]"
111 : "=&r" (slock), "=&r" (contended), "=&r" (res)
112 : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
124 static inline void arch_spin_unlock(arch_spinlock_t *lock)
127 lock->tickets.owner++;
131 static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
133 return lock.tickets.owner == lock.tickets.next;
136 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
138 return !arch_spin_value_unlocked(READ_ONCE(*lock));
141 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
143 struct __raw_tickets tickets = READ_ONCE(lock->tickets);
144 return (tickets.next - tickets.owner) > 1;
146 #define arch_spin_is_contended arch_spin_is_contended
152 * Write locks are easy - we just set bit 31. When unlocking, we can
153 * just write zero since the lock is exclusively held.
156 static inline void arch_write_lock(arch_rwlock_t *rw)
160 prefetchw(&rw->lock);
161 __asm__ __volatile__(
162 "1: ldrex %0, [%1]\n"
165 " strexeq %0, %2, [%1]\n"
169 : "r" (&rw->lock), "r" (0x80000000)
175 static inline int arch_write_trylock(arch_rwlock_t *rw)
177 unsigned long contended, res;
179 prefetchw(&rw->lock);
181 __asm__ __volatile__(
185 " strexeq %1, %3, [%2]"
186 : "=&r" (contended), "=&r" (res)
187 : "r" (&rw->lock), "r" (0x80000000)
199 static inline void arch_write_unlock(arch_rwlock_t *rw)
203 __asm__ __volatile__(
206 : "r" (&rw->lock), "r" (0)
212 /* write_can_lock - would write_trylock() succeed? */
213 #define arch_write_can_lock(x) (ACCESS_ONCE((x)->lock) == 0)
216 * Read locks are a bit more hairy:
217 * - Exclusively load the lock value.
219 * - Store new lock value if positive, and we still own this location.
220 * If the value is negative, we've already failed.
221 * - If we failed to store the value, we want a negative result.
222 * - If we failed, try again.
223 * Unlocking is similarly hairy. We may have multiple read locks
224 * currently active. However, we know we won't have any write
227 static inline void arch_read_lock(arch_rwlock_t *rw)
229 unsigned long tmp, tmp2;
231 prefetchw(&rw->lock);
232 __asm__ __volatile__(
233 "1: ldrex %0, [%2]\n"
235 " strexpl %1, %0, [%2]\n"
237 " rsbpls %0, %1, #0\n"
239 : "=&r" (tmp), "=&r" (tmp2)
246 static inline void arch_read_unlock(arch_rwlock_t *rw)
248 unsigned long tmp, tmp2;
252 prefetchw(&rw->lock);
253 __asm__ __volatile__(
254 "1: ldrex %0, [%2]\n"
256 " strex %1, %0, [%2]\n"
259 : "=&r" (tmp), "=&r" (tmp2)
267 static inline int arch_read_trylock(arch_rwlock_t *rw)
269 unsigned long contended, res;
271 prefetchw(&rw->lock);
273 __asm__ __volatile__(
277 " strexpl %1, %0, [%2]"
278 : "=&r" (contended), "=&r" (res)
283 /* If the lock is negative, then it is already held for write. */
284 if (contended < 0x80000000) {
292 /* read_can_lock - would read_trylock() succeed? */
293 #define arch_read_can_lock(x) (ACCESS_ONCE((x)->lock) < 0x80000000)
295 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
296 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
298 #define arch_spin_relax(lock) cpu_relax()
299 #define arch_read_relax(lock) cpu_relax()
300 #define arch_write_relax(lock) cpu_relax()
302 #endif /* __ASM_SPINLOCK_H */