1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/assembler.h
5 * Copyright (C) 1996-2000 Russell King
7 * This file contains arm architecture specific defines
8 * for the different processors.
10 * Do not include any C declarations in this file - it is included by
13 #ifndef __ASM_ASSEMBLER_H__
14 #define __ASM_ASSEMBLER_H__
17 #error "Only include this from assembly code"
20 #include <asm/ptrace.h>
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
24 #include <asm/pgtable.h>
25 #include <asm/thread_info.h>
26 #include <asm/uaccess-asm.h>
31 * Endian independent macros for shifting bytes within registers.
36 #define get_byte_0 lsl #0
37 #define get_byte_1 lsr #8
38 #define get_byte_2 lsr #16
39 #define get_byte_3 lsr #24
40 #define put_byte_0 lsl #0
41 #define put_byte_1 lsl #8
42 #define put_byte_2 lsl #16
43 #define put_byte_3 lsl #24
47 #define get_byte_0 lsr #24
48 #define get_byte_1 lsr #16
49 #define get_byte_2 lsr #8
50 #define get_byte_3 lsl #0
51 #define put_byte_0 lsl #24
52 #define put_byte_1 lsl #16
53 #define put_byte_2 lsl #8
54 #define put_byte_3 lsl #0
57 /* Select code for any configuration running in BE8 mode */
58 #ifdef CONFIG_CPU_ENDIAN_BE8
59 #define ARM_BE8(code...) code
61 #define ARM_BE8(code...)
65 * Data preload for architectures that support it
67 #if __LINUX_ARM_ARCH__ >= 5
68 #define PLD(code...) code
74 * This can be used to enable code to cacheline align the destination
75 * pointer when bulk writing to memory. Experiments on StrongARM and
76 * XScale didn't show this a worthwhile thing to do when the cache is not
77 * set to write-allocate (this would need further testing on XScale when WA
80 * On Feroceon there is much to gain however, regardless of cache mode.
82 #ifdef CONFIG_CPU_FEROCEON
83 #define CALGN(code...) code
85 #define CALGN(code...)
88 #define IMM12_MASK 0xfff
90 /* the frame pointer used for stack unwinding */
92 THUMB( fpreg .req r7 )
95 * Enable and disable interrupts
97 #if __LINUX_ARM_ARCH__ >= 6
98 .macro disable_irq_notrace
102 .macro enable_irq_notrace
106 .macro disable_irq_notrace
107 msr cpsr_c, #PSR_I_BIT | SVC_MODE
110 .macro enable_irq_notrace
111 msr cpsr_c, #SVC_MODE
115 #if __LINUX_ARM_ARCH__ < 7
117 mcr p15, 0, r0, c7, c10, 4
121 mcr p15, 0, r0, c7, c5, 4
125 .macro asm_trace_hardirqs_off, save=1
126 #if defined(CONFIG_TRACE_IRQFLAGS)
128 stmdb sp!, {r0-r3, ip, lr}
130 bl trace_hardirqs_off
132 ldmia sp!, {r0-r3, ip, lr}
137 .macro asm_trace_hardirqs_on, cond=al, save=1
138 #if defined(CONFIG_TRACE_IRQFLAGS)
140 * actually the registers should be pushed and pop'd conditionally, but
141 * after bl the flags are certainly clobbered
144 stmdb sp!, {r0-r3, ip, lr}
146 bl\cond trace_hardirqs_on
148 ldmia sp!, {r0-r3, ip, lr}
153 .macro disable_irq, save=1
155 asm_trace_hardirqs_off \save
159 asm_trace_hardirqs_on
163 * Save the current IRQ state and disable IRQs. Note that this macro
164 * assumes FIQs are enabled, and that the processor is in SVC mode.
166 .macro save_and_disable_irqs, oldcpsr
167 #ifdef CONFIG_CPU_V7M
168 mrs \oldcpsr, primask
175 .macro save_and_disable_irqs_notrace, oldcpsr
176 #ifdef CONFIG_CPU_V7M
177 mrs \oldcpsr, primask
185 * Restore interrupt state previously stored in a register. We don't
186 * guarantee that this will preserve the flags.
188 .macro restore_irqs_notrace, oldcpsr
189 #ifdef CONFIG_CPU_V7M
190 msr primask, \oldcpsr
196 .macro restore_irqs, oldcpsr
197 tst \oldcpsr, #PSR_I_BIT
198 asm_trace_hardirqs_on cond=eq
199 restore_irqs_notrace \oldcpsr
203 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
204 * reference local symbols in the same assembly file which are to be
205 * resolved by the assembler. Other usage is undefined.
207 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
208 .macro badr\c, rd, sym
209 #ifdef CONFIG_THUMB2_KERNEL
218 * Get current thread_info.
220 .macro get_thread_info, rd
221 /* thread_info is the first member of struct task_struct */
226 * Increment/decrement the preempt count.
228 #ifdef CONFIG_PREEMPT_COUNT
229 .macro inc_preempt_count, ti, tmp
230 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
231 add \tmp, \tmp, #1 @ increment it
232 str \tmp, [\ti, #TI_PREEMPT]
235 .macro dec_preempt_count, ti, tmp
236 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
237 sub \tmp, \tmp, #1 @ decrement it
238 str \tmp, [\ti, #TI_PREEMPT]
241 .macro inc_preempt_count, ti, tmp
244 .macro dec_preempt_count, ti, tmp
248 #define USERL(l, x...) \
250 .pushsection __ex_table,"a"; \
255 #define USER(x...) USERL(9001f, x)
258 #define ALT_SMP(instr...) \
261 * Note: if you get assembler errors from ALT_UP() when building with
262 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
263 * ALT_SMP( W(instr) ... )
265 #define ALT_UP(instr...) \
266 .pushsection ".alt.smp.init", "a" ;\
270 .if . - 9997b == 2 ;\
273 .if . - 9997b != 4 ;\
274 .error "ALT_UP() content must assemble to exactly 4 bytes";\
277 #define ALT_UP_B(label) \
278 .pushsection ".alt.smp.init", "a" ;\
281 W(b) . + (label - 9998b) ;\
284 #define ALT_SMP(instr...)
285 #define ALT_UP(instr...) instr
286 #define ALT_UP_B(label) b label
290 * this_cpu_offset - load the per-CPU offset of this CPU into
293 .macro this_cpu_offset, rd:req
295 ALT_SMP(mrc p15, 0, \rd, c13, c0, 4)
300 .L1_\@: ldr_va \rd, __per_cpu_offset
310 * set_current - store the task pointer of this CPU's current task
312 .macro set_current, rn:req, tmp:req
313 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
314 9998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register
318 .L0_\@: str_va \rn, __current, \tmp
324 str_va \rn, __current, \tmp
329 * get_current - load the task pointer of this CPU's current task
331 .macro get_current, rd:req
332 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
333 9998: mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register
337 .L0_\@: ldr_va \rd, __current
343 ldr_va \rd, __current
348 * reload_current - reload the task pointer of this CPU's current task
349 * into the TLS register
351 .macro reload_current, t1:req, t2:req
352 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
357 ldr_this_cpu \t1, __entry_task, \t1, \t2
358 mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO
364 * Instruction barrier
367 #if __LINUX_ARM_ARCH__ >= 7
369 #elif __LINUX_ARM_ARCH__ == 6
370 mcr p15, 0, r0, c7, c5, 4
375 * SMP data memory barrier
379 #if __LINUX_ARM_ARCH__ >= 7
385 #elif __LINUX_ARM_ARCH__ == 6
386 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
388 #error Incompatible SMP platform
399 * Raw SMP data memory barrier
401 .macro __smp_dmb mode
402 #if __LINUX_ARM_ARCH__ >= 7
408 #elif __LINUX_ARM_ARCH__ == 6
409 mcr p15, 0, r0, c7, c10, 5 @ dmb
411 .error "Incompatible SMP platform"
415 #if defined(CONFIG_CPU_V7M)
417 * setmode is used to assert to be in svc mode during boot. For v7-M
418 * this is done in __v7m_setup, so setmode can be empty here.
420 .macro setmode, mode, reg
422 #elif defined(CONFIG_THUMB2_KERNEL)
423 .macro setmode, mode, reg
428 .macro setmode, mode, reg
434 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
435 * a scratch register for the macro to overwrite.
437 * This macro is intended for forcing the CPU into SVC mode at boot time.
438 * you cannot return to the original mode.
440 .macro safe_svcmode_maskall reg:req
441 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
443 eor \reg, \reg, #HYP_MODE
445 bic \reg , \reg , #MODE_MASK
446 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
447 THUMB( orr \reg , \reg , #PSR_T_BIT )
449 orr \reg, \reg, #PSR_A_BIT
458 * workaround for possibly broken pre-v6 hardware
459 * (akita, Sharp Zaurus C-1000, PXA270-based)
461 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
466 * STRT/LDRT access macros with ARM and Thumb-2 variants
468 #ifdef CONFIG_THUMB2_KERNEL
470 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
473 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
475 \instr\t\cond\().w \reg, [\ptr, #\off]
477 .error "Unsupported inc macro argument"
480 .pushsection __ex_table,"a"
486 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
487 @ explicit IT instruction needed because of the label
488 @ introduced by the USER macro
495 .error "Unsupported rept macro argument"
499 @ Slightly optimised to avoid incrementing the pointer twice
500 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
502 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
505 add\cond \ptr, #\rept * \inc
508 #else /* !CONFIG_THUMB2_KERNEL */
510 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
514 \instr\()b\t\cond \reg, [\ptr], #\inc
516 \instr\t\cond \reg, [\ptr], #\inc
518 .error "Unsupported inc macro argument"
521 .pushsection __ex_table,"a"
528 #endif /* CONFIG_THUMB2_KERNEL */
530 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
531 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
534 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
535 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
538 /* Utility macro for declaring string literals */
539 .macro string name:req, string
540 .type \name , #object
543 .size \name , . - \name
546 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
548 #if __LINUX_ARM_ARCH__ < 6
562 #ifdef CONFIG_THUMB2_KERNEL
567 .macro bug, msg, line
568 #ifdef CONFIG_THUMB2_KERNEL
573 #ifdef CONFIG_DEBUG_BUGVERBOSE
574 .pushsection .rodata.str, "aMS", %progbits, 1
577 .pushsection __bug_table, "aw"
585 #ifdef CONFIG_KPROBES
586 #define _ASM_NOKPROBE(entry) \
587 .pushsection "_kprobe_blacklist", "aw" ; \
592 #define _ASM_NOKPROBE(entry)
595 .macro __adldst_l, op, reg, sym, tmp, c
596 .if __LINUX_ARM_ARCH__ < 7
600 .La\@: .long \sym - .Lpc\@
606 movw\c \tmp, #:lower16:\sym - .Lpc\@
607 movt\c \tmp, #:upper16:\sym - .Lpc\@
610 #ifndef CONFIG_THUMB2_KERNEL
611 .set .Lpc\@, . + 8 // PC bias
615 \op\c \reg, [pc, \tmp]
618 .Lb\@: add\c \tmp, \tmp, pc
620 * In Thumb-2 builds, the PC bias depends on whether we are currently
621 * emitting into a .arm or a .thumb section. The size of the add opcode
622 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
623 * emitting in ARM mode, so let's use this to account for the bias.
625 .set .Lpc\@, . + (. - .Lb\@)
634 * mov_l - move a constant value or [relocated] address into a register
636 .macro mov_l, dst:req, imm:req, cond
637 .if __LINUX_ARM_ARCH__ < 7
640 movw\cond \dst, #:lower16:\imm
641 movt\cond \dst, #:upper16:\imm
646 * adr_l - adr pseudo-op with unlimited range
648 * @dst: destination register
649 * @sym: name of the symbol
650 * @cond: conditional opcode suffix
652 .macro adr_l, dst:req, sym:req, cond
653 __adldst_l add, \dst, \sym, \dst, \cond
657 * ldr_l - ldr <literal> pseudo-op with unlimited range
659 * @dst: destination register
660 * @sym: name of the symbol
661 * @cond: conditional opcode suffix
663 .macro ldr_l, dst:req, sym:req, cond
664 __adldst_l ldr, \dst, \sym, \dst, \cond
668 * str_l - str <literal> pseudo-op with unlimited range
670 * @src: source register
671 * @sym: name of the symbol
672 * @tmp: mandatory scratch register
673 * @cond: conditional opcode suffix
675 .macro str_l, src:req, sym:req, tmp:req, cond
676 __adldst_l str, \src, \sym, \tmp, \cond
679 .macro __ldst_va, op, reg, tmp, sym, cond, offset
680 #if __LINUX_ARM_ARCH__ >= 7 || \
681 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
682 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
683 mov_l \tmp, \sym, \cond
686 * Avoid a literal load, by emitting a sequence of ADD/LDR instructions
687 * with the appropriate relocations. The combined sequence has a range
688 * of -/+ 256 MiB, which should be sufficient for the core kernel and
689 * for modules loaded into the module region.
692 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
693 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
694 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
695 .L0_\@: sub\cond \tmp, pc, #8 - \offset
696 .L1_\@: sub\cond \tmp, \tmp, #4 - \offset
699 \op\cond \reg, [\tmp, #\offset]
703 * ldr_va - load a 32-bit word from the virtual address of \sym
705 .macro ldr_va, rd:req, sym:req, cond, tmp, offset=0
707 __ldst_va ldr, \rd, \tmp, \sym, \cond, \offset
709 __ldst_va ldr, \rd, \rd, \sym, \cond, \offset
714 * str_va - store a 32-bit word to the virtual address of \sym
716 .macro str_va, rn:req, sym:req, tmp:req, cond
717 __ldst_va str, \rn, \tmp, \sym, \cond, 0
721 * ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym',
722 * without using a temp register. Supported in ARM mode
725 .macro ldr_this_cpu_armv6, rd:req, sym:req
728 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
729 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
730 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
732 .L0_\@: sub \rd, \rd, #4
733 .L1_\@: sub \rd, \rd, #0
734 .L2_\@: ldr \rd, [\rd, #4]
738 * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym'
739 * into register 'rd', which may be the stack pointer,
740 * using 't1' and 't2' as general temp registers. These
741 * are permitted to overlap with 'rd' if != sp
743 .macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req
745 ldr_va \rd, \sym, tmp=\t1
746 #elif __LINUX_ARM_ARCH__ >= 7 || \
747 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
748 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
753 ldr_this_cpu_armv6 \rd, \sym
758 * rev_l - byte-swap a 32-bit value
760 * @val: source/destination register
761 * @tmp: scratch register
763 .macro rev_l, val:req, tmp:req
764 .if __LINUX_ARM_ARCH__ < 6
765 eor \tmp, \val, \val, ror #16
766 bic \tmp, \tmp, #0x00ff0000
767 mov \val, \val, ror #8
768 eor \val, \val, \tmp, lsr #8
774 .if __LINUX_ARM_ARCH__ < 6
775 .set .Lrev_l_uses_tmp, 1
777 .set .Lrev_l_uses_tmp, 0
781 * bl_r - branch and link to register
783 * @dst: target to branch to
784 * @c: conditional opcode suffix
786 .macro bl_r, dst:req, c
787 .if __LINUX_ARM_ARCH__ < 6
795 #endif /* __ASM_ASSEMBLER_H__ */