1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/assembler.h
5 * Copyright (C) 1996-2000 Russell King
7 * This file contains arm architecture specific defines
8 * for the different processors.
10 * Do not include any C declarations in this file - it is included by
13 #ifndef __ASM_ASSEMBLER_H__
14 #define __ASM_ASSEMBLER_H__
17 #error "Only include this from assembly code"
20 #include <asm/ptrace.h>
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
24 #include <asm/thread_info.h>
25 #include <asm/uaccess-asm.h>
30 * Endian independent macros for shifting bytes within registers.
35 #define get_byte_0 lsl #0
36 #define get_byte_1 lsr #8
37 #define get_byte_2 lsr #16
38 #define get_byte_3 lsr #24
39 #define put_byte_0 lsl #0
40 #define put_byte_1 lsl #8
41 #define put_byte_2 lsl #16
42 #define put_byte_3 lsl #24
46 #define get_byte_0 lsr #24
47 #define get_byte_1 lsr #16
48 #define get_byte_2 lsr #8
49 #define get_byte_3 lsl #0
50 #define put_byte_0 lsl #24
51 #define put_byte_1 lsl #16
52 #define put_byte_2 lsl #8
53 #define put_byte_3 lsl #0
56 /* Select code for any configuration running in BE8 mode */
57 #ifdef CONFIG_CPU_ENDIAN_BE8
58 #define ARM_BE8(code...) code
60 #define ARM_BE8(code...)
64 * Data preload for architectures that support it
66 #if __LINUX_ARM_ARCH__ >= 5
67 #define PLD(code...) code
73 * This can be used to enable code to cacheline align the destination
74 * pointer when bulk writing to memory. Experiments on StrongARM and
75 * XScale didn't show this a worthwhile thing to do when the cache is not
76 * set to write-allocate (this would need further testing on XScale when WA
79 * On Feroceon there is much to gain however, regardless of cache mode.
81 #ifdef CONFIG_CPU_FEROCEON
82 #define CALGN(code...) code
84 #define CALGN(code...)
87 #define IMM12_MASK 0xfff
89 /* the frame pointer used for stack unwinding */
91 THUMB( fpreg .req r7 )
94 * Enable and disable interrupts
96 #if __LINUX_ARM_ARCH__ >= 6
97 .macro disable_irq_notrace
101 .macro enable_irq_notrace
105 .macro disable_irq_notrace
106 msr cpsr_c, #PSR_I_BIT | SVC_MODE
109 .macro enable_irq_notrace
110 msr cpsr_c, #SVC_MODE
114 #if __LINUX_ARM_ARCH__ < 7
116 mcr p15, 0, r0, c7, c10, 4
120 mcr p15, 0, r0, c7, c5, 4
124 .macro asm_trace_hardirqs_off, save=1
125 #if defined(CONFIG_TRACE_IRQFLAGS)
127 stmdb sp!, {r0-r3, ip, lr}
129 bl trace_hardirqs_off
131 ldmia sp!, {r0-r3, ip, lr}
136 .macro asm_trace_hardirqs_on, cond=al, save=1
137 #if defined(CONFIG_TRACE_IRQFLAGS)
139 * actually the registers should be pushed and pop'd conditionally, but
140 * after bl the flags are certainly clobbered
143 stmdb sp!, {r0-r3, ip, lr}
145 bl\cond trace_hardirqs_on
147 ldmia sp!, {r0-r3, ip, lr}
152 .macro disable_irq, save=1
154 asm_trace_hardirqs_off \save
158 asm_trace_hardirqs_on
162 * Save the current IRQ state and disable IRQs. Note that this macro
163 * assumes FIQs are enabled, and that the processor is in SVC mode.
165 .macro save_and_disable_irqs, oldcpsr
166 #ifdef CONFIG_CPU_V7M
167 mrs \oldcpsr, primask
174 .macro save_and_disable_irqs_notrace, oldcpsr
175 #ifdef CONFIG_CPU_V7M
176 mrs \oldcpsr, primask
184 * Restore interrupt state previously stored in a register. We don't
185 * guarantee that this will preserve the flags.
187 .macro restore_irqs_notrace, oldcpsr
188 #ifdef CONFIG_CPU_V7M
189 msr primask, \oldcpsr
195 .macro restore_irqs, oldcpsr
196 tst \oldcpsr, #PSR_I_BIT
197 asm_trace_hardirqs_on cond=eq
198 restore_irqs_notrace \oldcpsr
202 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
203 * reference local symbols in the same assembly file which are to be
204 * resolved by the assembler. Other usage is undefined.
206 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
207 .macro badr\c, rd, sym
208 #ifdef CONFIG_THUMB2_KERNEL
217 * Get current thread_info.
219 .macro get_thread_info, rd
220 /* thread_info is the first member of struct task_struct */
225 * Increment/decrement the preempt count.
227 #ifdef CONFIG_PREEMPT_COUNT
228 .macro inc_preempt_count, ti, tmp
229 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
230 add \tmp, \tmp, #1 @ increment it
231 str \tmp, [\ti, #TI_PREEMPT]
234 .macro dec_preempt_count, ti, tmp
235 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
236 sub \tmp, \tmp, #1 @ decrement it
237 str \tmp, [\ti, #TI_PREEMPT]
240 .macro dec_preempt_count_ti, ti, tmp
242 dec_preempt_count \ti, \tmp
245 .macro inc_preempt_count, ti, tmp
248 .macro dec_preempt_count, ti, tmp
251 .macro dec_preempt_count_ti, ti, tmp
255 #define USERL(l, x...) \
257 .pushsection __ex_table,"a"; \
262 #define USER(x...) USERL(9001f, x)
265 #define ALT_SMP(instr...) \
268 * Note: if you get assembler errors from ALT_UP() when building with
269 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
270 * ALT_SMP( W(instr) ... )
272 #define ALT_UP(instr...) \
273 .pushsection ".alt.smp.init", "a" ;\
277 .if . - 9997b == 2 ;\
280 .if . - 9997b != 4 ;\
281 .error "ALT_UP() content must assemble to exactly 4 bytes";\
284 #define ALT_UP_B(label) \
285 .pushsection ".alt.smp.init", "a" ;\
288 W(b) . + (label - 9998b) ;\
291 #define ALT_SMP(instr...)
292 #define ALT_UP(instr...) instr
293 #define ALT_UP_B(label) b label
297 * this_cpu_offset - load the per-CPU offset of this CPU into
300 .macro this_cpu_offset, rd:req
302 ALT_SMP(mrc p15, 0, \rd, c13, c0, 4)
307 .L1_\@: ldr_va \rd, __per_cpu_offset
317 * set_current - store the task pointer of this CPU's current task
319 .macro set_current, rn:req, tmp:req
320 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
321 9998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register
325 .L0_\@: str_va \rn, __current, \tmp
331 str_va \rn, __current, \tmp
336 * get_current - load the task pointer of this CPU's current task
338 .macro get_current, rd:req
339 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
340 9998: mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register
344 .L0_\@: ldr_va \rd, __current
350 ldr_va \rd, __current
355 * reload_current - reload the task pointer of this CPU's current task
356 * into the TLS register
358 .macro reload_current, t1:req, t2:req
359 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
364 ldr_this_cpu \t1, __entry_task, \t1, \t2
365 mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO
371 * Instruction barrier
374 #if __LINUX_ARM_ARCH__ >= 7
376 #elif __LINUX_ARM_ARCH__ == 6
377 mcr p15, 0, r0, c7, c5, 4
382 * SMP data memory barrier
386 #if __LINUX_ARM_ARCH__ >= 7
392 #elif __LINUX_ARM_ARCH__ == 6
393 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
395 #error Incompatible SMP platform
405 #if defined(CONFIG_CPU_V7M)
407 * setmode is used to assert to be in svc mode during boot. For v7-M
408 * this is done in __v7m_setup, so setmode can be empty here.
410 .macro setmode, mode, reg
412 #elif defined(CONFIG_THUMB2_KERNEL)
413 .macro setmode, mode, reg
418 .macro setmode, mode, reg
424 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
425 * a scratch register for the macro to overwrite.
427 * This macro is intended for forcing the CPU into SVC mode at boot time.
428 * you cannot return to the original mode.
430 .macro safe_svcmode_maskall reg:req
431 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
433 eor \reg, \reg, #HYP_MODE
435 bic \reg , \reg , #MODE_MASK
436 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
437 THUMB( orr \reg , \reg , #PSR_T_BIT )
439 orr \reg, \reg, #PSR_A_BIT
448 * workaround for possibly broken pre-v6 hardware
449 * (akita, Sharp Zaurus C-1000, PXA270-based)
451 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
456 * STRT/LDRT access macros with ARM and Thumb-2 variants
458 #ifdef CONFIG_THUMB2_KERNEL
460 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
463 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
465 \instr\t\cond\().w \reg, [\ptr, #\off]
467 .error "Unsupported inc macro argument"
470 .pushsection __ex_table,"a"
476 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
477 @ explicit IT instruction needed because of the label
478 @ introduced by the USER macro
485 .error "Unsupported rept macro argument"
489 @ Slightly optimised to avoid incrementing the pointer twice
490 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
492 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
495 add\cond \ptr, #\rept * \inc
498 #else /* !CONFIG_THUMB2_KERNEL */
500 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
504 \instr\()b\t\cond \reg, [\ptr], #\inc
506 \instr\t\cond \reg, [\ptr], #\inc
508 .error "Unsupported inc macro argument"
511 .pushsection __ex_table,"a"
518 #endif /* CONFIG_THUMB2_KERNEL */
520 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
521 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
524 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
525 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
528 /* Utility macro for declaring string literals */
529 .macro string name:req, string
530 .type \name , #object
533 .size \name , . - \name
536 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
538 #if __LINUX_ARM_ARCH__ < 6
552 #ifdef CONFIG_THUMB2_KERNEL
557 .macro bug, msg, line
558 #ifdef CONFIG_THUMB2_KERNEL
563 #ifdef CONFIG_DEBUG_BUGVERBOSE
564 .pushsection .rodata.str, "aMS", %progbits, 1
567 .pushsection __bug_table, "aw"
575 #ifdef CONFIG_KPROBES
576 #define _ASM_NOKPROBE(entry) \
577 .pushsection "_kprobe_blacklist", "aw" ; \
582 #define _ASM_NOKPROBE(entry)
585 .macro __adldst_l, op, reg, sym, tmp, c
586 .if __LINUX_ARM_ARCH__ < 7
590 .La\@: .long \sym - .Lpc\@
596 movw\c \tmp, #:lower16:\sym - .Lpc\@
597 movt\c \tmp, #:upper16:\sym - .Lpc\@
600 #ifndef CONFIG_THUMB2_KERNEL
601 .set .Lpc\@, . + 8 // PC bias
605 \op\c \reg, [pc, \tmp]
608 .Lb\@: add\c \tmp, \tmp, pc
610 * In Thumb-2 builds, the PC bias depends on whether we are currently
611 * emitting into a .arm or a .thumb section. The size of the add opcode
612 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
613 * emitting in ARM mode, so let's use this to account for the bias.
615 .set .Lpc\@, . + (. - .Lb\@)
624 * mov_l - move a constant value or [relocated] address into a register
626 .macro mov_l, dst:req, imm:req, cond
627 .if __LINUX_ARM_ARCH__ < 7
630 movw\cond \dst, #:lower16:\imm
631 movt\cond \dst, #:upper16:\imm
636 * adr_l - adr pseudo-op with unlimited range
638 * @dst: destination register
639 * @sym: name of the symbol
640 * @cond: conditional opcode suffix
642 .macro adr_l, dst:req, sym:req, cond
643 __adldst_l add, \dst, \sym, \dst, \cond
647 * ldr_l - ldr <literal> pseudo-op with unlimited range
649 * @dst: destination register
650 * @sym: name of the symbol
651 * @cond: conditional opcode suffix
653 .macro ldr_l, dst:req, sym:req, cond
654 __adldst_l ldr, \dst, \sym, \dst, \cond
658 * str_l - str <literal> pseudo-op with unlimited range
660 * @src: source register
661 * @sym: name of the symbol
662 * @tmp: mandatory scratch register
663 * @cond: conditional opcode suffix
665 .macro str_l, src:req, sym:req, tmp:req, cond
666 __adldst_l str, \src, \sym, \tmp, \cond
669 .macro __ldst_va, op, reg, tmp, sym, cond
670 #if __LINUX_ARM_ARCH__ >= 7 || \
671 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
672 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
673 mov_l \tmp, \sym, \cond
674 \op\cond \reg, [\tmp]
677 * Avoid a literal load, by emitting a sequence of ADD/LDR instructions
678 * with the appropriate relocations. The combined sequence has a range
679 * of -/+ 256 MiB, which should be sufficient for the core kernel and
680 * for modules loaded into the module region.
683 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
684 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
685 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
686 .L0_\@: sub\cond \tmp, pc, #8
687 .L1_\@: sub\cond \tmp, \tmp, #4
688 .L2_\@: \op\cond \reg, [\tmp, #0]
693 * ldr_va - load a 32-bit word from the virtual address of \sym
695 .macro ldr_va, rd:req, sym:req, cond
696 __ldst_va ldr, \rd, \rd, \sym, \cond
700 * str_va - store a 32-bit word to the virtual address of \sym
702 .macro str_va, rn:req, sym:req, tmp:req, cond
703 __ldst_va str, \rn, \tmp, \sym, \cond
707 * ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym',
708 * without using a temp register. Supported in ARM mode
711 .macro ldr_this_cpu_armv6, rd:req, sym:req
714 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
715 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
716 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
718 .L0_\@: sub \rd, \rd, #4
719 .L1_\@: sub \rd, \rd, #0
720 .L2_\@: ldr \rd, [\rd, #4]
724 * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym'
725 * into register 'rd', which may be the stack pointer,
726 * using 't1' and 't2' as general temp registers. These
727 * are permitted to overlap with 'rd' if != sp
729 .macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req
730 #if __LINUX_ARM_ARCH__ >= 7 || \
731 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
732 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
737 ldr_this_cpu_armv6 \rd, \sym
742 * rev_l - byte-swap a 32-bit value
744 * @val: source/destination register
745 * @tmp: scratch register
747 .macro rev_l, val:req, tmp:req
748 .if __LINUX_ARM_ARCH__ < 6
749 eor \tmp, \val, \val, ror #16
750 bic \tmp, \tmp, #0x00ff0000
751 mov \val, \val, ror #8
752 eor \val, \val, \tmp, lsr #8
759 * bl_r - branch and link to register
761 * @dst: target to branch to
762 * @c: conditional opcode suffix
764 .macro bl_r, dst:req, c
765 .if __LINUX_ARM_ARCH__ < 6
773 #endif /* __ASM_ASSEMBLER_H__ */