2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
29 * Endian independent macros for shifting bytes within registers.
34 #define get_byte_0 lsl #0
35 #define get_byte_1 lsr #8
36 #define get_byte_2 lsr #16
37 #define get_byte_3 lsr #24
38 #define put_byte_0 lsl #0
39 #define put_byte_1 lsl #8
40 #define put_byte_2 lsl #16
41 #define put_byte_3 lsl #24
45 #define get_byte_0 lsr #24
46 #define get_byte_1 lsr #16
47 #define get_byte_2 lsr #8
48 #define get_byte_3 lsl #0
49 #define put_byte_0 lsl #24
50 #define put_byte_1 lsl #16
51 #define put_byte_2 lsl #8
52 #define put_byte_3 lsl #0
56 * Data preload for architectures that support it
58 #if __LINUX_ARM_ARCH__ >= 5
59 #define PLD(code...) code
65 * This can be used to enable code to cacheline align the destination
66 * pointer when bulk writing to memory. Experiments on StrongARM and
67 * XScale didn't show this a worthwhile thing to do when the cache is not
68 * set to write-allocate (this would need further testing on XScale when WA
71 * On Feroceon there is much to gain however, regardless of cache mode.
73 #ifdef CONFIG_CPU_FEROCEON
74 #define CALGN(code...) code
76 #define CALGN(code...)
80 * Enable and disable interrupts
82 #if __LINUX_ARM_ARCH__ >= 6
83 .macro disable_irq_notrace
87 .macro enable_irq_notrace
91 .macro disable_irq_notrace
92 msr cpsr_c, #PSR_I_BIT | SVC_MODE
95 .macro enable_irq_notrace
100 .macro asm_trace_hardirqs_off
101 #if defined(CONFIG_TRACE_IRQFLAGS)
102 stmdb sp!, {r0-r3, ip, lr}
103 bl trace_hardirqs_off
104 ldmia sp!, {r0-r3, ip, lr}
108 .macro asm_trace_hardirqs_on_cond, cond
109 #if defined(CONFIG_TRACE_IRQFLAGS)
111 * actually the registers should be pushed and pop'd conditionally, but
112 * after bl the flags are certainly clobbered
114 stmdb sp!, {r0-r3, ip, lr}
115 bl\cond trace_hardirqs_on
116 ldmia sp!, {r0-r3, ip, lr}
120 .macro asm_trace_hardirqs_on
121 asm_trace_hardirqs_on_cond al
126 asm_trace_hardirqs_off
130 asm_trace_hardirqs_on
134 * Save the current IRQ state and disable IRQs. Note that this macro
135 * assumes FIQs are enabled, and that the processor is in SVC mode.
137 .macro save_and_disable_irqs, oldcpsr
142 .macro save_and_disable_irqs_notrace, oldcpsr
148 * Restore interrupt state previously stored in a register. We don't
149 * guarantee that this will preserve the flags.
151 .macro restore_irqs_notrace, oldcpsr
155 .macro restore_irqs, oldcpsr
156 tst \oldcpsr, #PSR_I_BIT
157 asm_trace_hardirqs_on_cond eq
158 restore_irqs_notrace \oldcpsr
163 .pushsection __ex_table,"a"; \
169 #define ALT_SMP(instr...) \
172 * Note: if you get assembler errors from ALT_UP() when building with
173 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
174 * ALT_SMP( W(instr) ... )
176 #define ALT_UP(instr...) \
177 .pushsection ".alt.smp.init", "a" ;\
180 .if . - 9997b != 4 ;\
181 .error "ALT_UP() content must assemble to exactly 4 bytes";\
184 #define ALT_UP_B(label) \
185 .equ up_b_offset, label - 9998b ;\
186 .pushsection ".alt.smp.init", "a" ;\
188 W(b) . + up_b_offset ;\
191 #define ALT_SMP(instr...)
192 #define ALT_UP(instr...) instr
193 #define ALT_UP_B(label) b label
197 * Instruction barrier
200 #if __LINUX_ARM_ARCH__ >= 7
202 #elif __LINUX_ARM_ARCH__ == 6
203 mcr p15, 0, r0, c7, c5, 4
208 * SMP data memory barrier
212 #if __LINUX_ARM_ARCH__ >= 7
218 #elif __LINUX_ARM_ARCH__ == 6
219 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
221 #error Incompatible SMP platform
231 #ifdef CONFIG_THUMB2_KERNEL
232 .macro setmode, mode, reg
237 .macro setmode, mode, reg
243 * STRT/LDRT access macros with ARM and Thumb-2 variants
245 #ifdef CONFIG_THUMB2_KERNEL
247 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
250 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
252 \instr\cond\()\t\().w \reg, [\ptr, #\off]
254 .error "Unsupported inc macro argument"
257 .pushsection __ex_table,"a"
263 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
264 @ explicit IT instruction needed because of the label
265 @ introduced by the USER macro
272 .error "Unsupported rept macro argument"
276 @ Slightly optimised to avoid incrementing the pointer twice
277 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
279 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
282 add\cond \ptr, #\rept * \inc
285 #else /* !CONFIG_THUMB2_KERNEL */
287 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
291 \instr\cond\()b\()\t \reg, [\ptr], #\inc
293 \instr\cond\()\t \reg, [\ptr], #\inc
295 .error "Unsupported inc macro argument"
298 .pushsection __ex_table,"a"
305 #endif /* CONFIG_THUMB2_KERNEL */
307 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
308 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
311 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
312 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
315 /* Utility macro for declaring string literals */
316 .macro string name:req, string
317 .type \name , #object
320 .size \name , . - \name
323 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
324 #ifndef CONFIG_CPU_USE_DOMAINS
325 adds \tmp, \addr, #\size - 1
326 sbcccs \tmp, \tmp, \limit
331 #endif /* __ASM_ASSEMBLER_H__ */