2 * Device Tree Source for UniPhier PXs2 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
23 compatible = "arm,cortex-a9";
25 clocks = <&sys_clk 32>;
26 enable-method = "psci";
27 next-level-cache = <&l2>;
28 operating-points-v2 = <&cpu_opp>;
34 compatible = "arm,cortex-a9";
36 clocks = <&sys_clk 32>;
37 enable-method = "psci";
38 next-level-cache = <&l2>;
39 operating-points-v2 = <&cpu_opp>;
44 compatible = "arm,cortex-a9";
46 clocks = <&sys_clk 32>;
47 enable-method = "psci";
48 next-level-cache = <&l2>;
49 operating-points-v2 = <&cpu_opp>;
54 compatible = "arm,cortex-a9";
56 clocks = <&sys_clk 32>;
57 enable-method = "psci";
58 next-level-cache = <&l2>;
59 operating-points-v2 = <&cpu_opp>;
64 compatible = "operating-points-v2";
68 opp-hz = /bits/ 64 <100000000>;
69 clock-latency-ns = <300>;
72 opp-hz = /bits/ 64 <150000000>;
73 clock-latency-ns = <300>;
76 opp-hz = /bits/ 64 <200000000>;
77 clock-latency-ns = <300>;
80 opp-hz = /bits/ 64 <300000000>;
81 clock-latency-ns = <300>;
84 opp-hz = /bits/ 64 <400000000>;
85 clock-latency-ns = <300>;
88 opp-hz = /bits/ 64 <600000000>;
89 clock-latency-ns = <300>;
92 opp-hz = /bits/ 64 <800000000>;
93 clock-latency-ns = <300>;
96 opp-hz = /bits/ 64 <1200000000>;
97 clock-latency-ns = <300>;
102 compatible = "arm,psci-0.2";
108 compatible = "fixed-clock";
110 clock-frequency = <25000000>;
113 arm_timer_clk: arm-timer {
115 compatible = "fixed-clock";
116 clock-frequency = <50000000>;
122 polling-delay-passive = <250>; /* 250ms */
123 polling-delay = <1000>; /* 1000ms */
124 thermal-sensors = <&pvtctl>;
128 temperature = <95000>; /* 95C */
132 cpu_alert: cpu-alert {
133 temperature = <85000>; /* 85C */
142 cooling-device = <&cpu0
143 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
150 compatible = "simple-bus";
151 #address-cells = <1>;
154 interrupt-parent = <&intc>;
156 l2: l2-cache@500c0000 {
157 compatible = "socionext,uniphier-system-cache";
158 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
160 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
162 cache-size = <(1280 * 1024)>;
164 cache-line-size = <128>;
168 serial0: serial@54006800 {
169 compatible = "socionext,uniphier-uart";
171 reg = <0x54006800 0x40>;
172 interrupts = <0 33 4>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_uart0>;
175 clocks = <&peri_clk 0>;
176 resets = <&peri_rst 0>;
179 serial1: serial@54006900 {
180 compatible = "socionext,uniphier-uart";
182 reg = <0x54006900 0x40>;
183 interrupts = <0 35 4>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_uart1>;
186 clocks = <&peri_clk 1>;
187 resets = <&peri_rst 1>;
190 serial2: serial@54006a00 {
191 compatible = "socionext,uniphier-uart";
193 reg = <0x54006a00 0x40>;
194 interrupts = <0 37 4>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_uart2>;
197 clocks = <&peri_clk 2>;
198 resets = <&peri_rst 2>;
201 serial3: serial@54006b00 {
202 compatible = "socionext,uniphier-uart";
204 reg = <0x54006b00 0x40>;
205 interrupts = <0 177 4>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_uart3>;
208 clocks = <&peri_clk 3>;
209 resets = <&peri_rst 3>;
212 gpio: gpio@55000000 {
213 compatible = "socionext,uniphier-gpio";
214 reg = <0x55000000 0x200>;
215 interrupt-parent = <&aidet>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
220 gpio-ranges = <&pinctrl 0 0 0>,
222 gpio-ranges-group-names = "gpio_range0",
225 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
230 compatible = "socionext,uniphier-fi2c";
232 reg = <0x58780000 0x80>;
233 #address-cells = <1>;
235 interrupts = <0 41 4>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_i2c0>;
238 clocks = <&peri_clk 4>;
239 resets = <&peri_rst 4>;
240 clock-frequency = <100000>;
244 compatible = "socionext,uniphier-fi2c";
246 reg = <0x58781000 0x80>;
247 #address-cells = <1>;
249 interrupts = <0 42 4>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_i2c1>;
252 clocks = <&peri_clk 5>;
253 resets = <&peri_rst 5>;
254 clock-frequency = <100000>;
258 compatible = "socionext,uniphier-fi2c";
260 reg = <0x58782000 0x80>;
261 #address-cells = <1>;
263 interrupts = <0 43 4>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_i2c2>;
266 clocks = <&peri_clk 6>;
267 resets = <&peri_rst 6>;
268 clock-frequency = <100000>;
272 compatible = "socionext,uniphier-fi2c";
274 reg = <0x58783000 0x80>;
275 #address-cells = <1>;
277 interrupts = <0 44 4>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_i2c3>;
280 clocks = <&peri_clk 7>;
281 resets = <&peri_rst 7>;
282 clock-frequency = <100000>;
285 /* chip-internal connection for DMD */
287 compatible = "socionext,uniphier-fi2c";
288 reg = <0x58784000 0x80>;
289 #address-cells = <1>;
291 interrupts = <0 45 4>;
292 clocks = <&peri_clk 8>;
293 resets = <&peri_rst 8>;
294 clock-frequency = <400000>;
297 /* chip-internal connection for STM */
299 compatible = "socionext,uniphier-fi2c";
300 reg = <0x58785000 0x80>;
301 #address-cells = <1>;
303 interrupts = <0 25 4>;
304 clocks = <&peri_clk 9>;
305 resets = <&peri_rst 9>;
306 clock-frequency = <400000>;
309 /* chip-internal connection for HDMI */
311 compatible = "socionext,uniphier-fi2c";
312 reg = <0x58786000 0x80>;
313 #address-cells = <1>;
315 interrupts = <0 26 4>;
316 clocks = <&peri_clk 10>;
317 resets = <&peri_rst 10>;
318 clock-frequency = <400000>;
321 system_bus: system-bus@58c00000 {
322 compatible = "socionext,uniphier-system-bus";
324 reg = <0x58c00000 0x400>;
325 #address-cells = <2>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_system_bus>;
332 compatible = "socionext,uniphier-smpctrl";
333 reg = <0x59801000 0x400>;
337 compatible = "socionext,uniphier-pxs2-sdctrl",
338 "simple-mfd", "syscon";
339 reg = <0x59810000 0x400>;
342 compatible = "socionext,uniphier-pxs2-sd-clock";
347 compatible = "socionext,uniphier-pxs2-sd-reset";
353 compatible = "socionext,uniphier-pxs2-perictrl",
354 "simple-mfd", "syscon";
355 reg = <0x59820000 0x200>;
358 compatible = "socionext,uniphier-pxs2-peri-clock";
363 compatible = "socionext,uniphier-pxs2-peri-reset";
369 compatible = "socionext,uniphier-pxs2-soc-glue",
370 "simple-mfd", "syscon";
371 reg = <0x5f800000 0x2000>;
374 compatible = "socionext,uniphier-pxs2-pinctrl";
378 aidet: aidet@5fc20000 {
379 compatible = "socionext,uniphier-pxs2-aidet";
380 reg = <0x5fc20000 0x200>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
386 compatible = "arm,cortex-a9-global-timer";
387 reg = <0x60000200 0x20>;
388 interrupts = <1 11 0xf04>;
389 clocks = <&arm_timer_clk>;
393 compatible = "arm,cortex-a9-twd-timer";
394 reg = <0x60000600 0x20>;
395 interrupts = <1 13 0xf04>;
396 clocks = <&arm_timer_clk>;
399 intc: interrupt-controller@60001000 {
400 compatible = "arm,cortex-a9-gic";
401 reg = <0x60001000 0x1000>,
403 #interrupt-cells = <3>;
404 interrupt-controller;
408 compatible = "socionext,uniphier-pxs2-sysctrl",
409 "simple-mfd", "syscon";
410 reg = <0x61840000 0x10000>;
413 compatible = "socionext,uniphier-pxs2-clock";
418 compatible = "socionext,uniphier-pxs2-reset";
423 compatible = "socionext,uniphier-pxs2-thermal";
424 interrupts = <0 3 4>;
425 #thermal-sensor-cells = <0>;
426 socionext,tmod-calibration = <0x0f86 0x6844>;
430 nand: nand@68000000 {
431 compatible = "socionext,uniphier-denali-nand-v5b";
433 reg-names = "nand_data", "denali_reg";
434 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
435 interrupts = <0 65 4>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_nand2cs>;
438 clocks = <&sys_clk 2>;
439 resets = <&sys_rst 2>;
444 #include "uniphier-pinctrl.dtsi"