arch/arm/boot/dts/tegra30-ouya.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/input/gpio-keys.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/thermal/thermal.h>
   7
   8 #include "tegra30.dtsi"
   9 #include "tegra30-cpu-opp.dtsi"
  10 #include "tegra30-cpu-opp-microvolt.dtsi"
  11
  12 / {
  13         model = "Ouya Game Console";
  14         compatible = "ouya,ouya", "nvidia,tegra30";
  15
  16         aliases {
  17                 mmc0 = &sdmmc4; /* eMMC */
  18                 mmc1 = &sdmmc3; /* WiFi */
  19                 rtc0 = &pmic;
  20                 rtc1 = "/rtc@7000e000";
  21                 serial0 = &uartd; /* Debug Port */
  22                 serial1 = &uartc; /* Bluetooth */
  23         };
  24
  25         chosen {
  26                 stdout-path = "serial0:115200n8";
  27         };
  28
  29         firmware {
  30                 trusted-foundations {
  31                         compatible = "tlm,trusted-foundations";
  32                         tlm,version-major = <0x0>;
  33                         tlm,version-minor = <0x0>;
  34                 };
  35         };
  36
  37         memory@80000000 {
  38                 reg = <0x80000000 0x40000000>;
  39         };
  40
  41         reserved-memory {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 ranges;
  45
  46                 linux,cma@80000000 {
  47                         compatible = "shared-dma-pool";
  48                         alloc-ranges = <0x80000000 0x30000000>;
  49                         size = <0x10000000>; /* 256MiB */
  50                         linux,cma-default;
  51                         reusable;
  52                 };
  53
  54                 ramoops@bfdf0000 {
  55                         compatible = "ramoops";
  56                         reg = <0xbfdf0000 0x10000>;     /* 64kB */
  57                         console-size = <0x8000>;        /* 32kB */
  58                         record-size = <0x400>;          /*  1kB */
  59                         ecc-size = <16>;
  60                 };
  61
  62                 trustzone@bfe00000 {
  63                         reg = <0xbfe00000 0x200000>;
  64                         no-map;
  65                 };
  66         };
  67
  68         host1x@50000000 {
  69                 hdmi@54280000 {
  70                         status = "okay";
  71                         vdd-supply = <&vdd_vid_reg>;
  72                         pll-supply = <&ldo7_reg>;
  73                         hdmi-supply = <&sys_3v3_reg>;
  74                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  75                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  76                 };
  77         };
  78
  79         pinmux@70000868 {
  80                 pinctrl-names = "default";
  81                 pinctrl-0 = <&state_default>;
  82
  83                 state_default: pinmux {
  84                         clk_32k_out_pa0 {
  85                                 nvidia,pins = "clk_32k_out_pa0";
  86                                 nvidia,function = "blink";
  87                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  89                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  90                         };
  91
  92                         uart3_cts_n_pa1 {
  93                                 nvidia,pins = "uart3_cts_n_pa1";
  94                                 nvidia,function = "uartc";
  95                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  96                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  97                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  98                         };
  99
 100                         dap2_fs_pa2 {
 101                                 nvidia,pins = "dap2_fs_pa2";
 102                                 nvidia,function = "i2s1";
 103                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 104                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 105                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 106                         };
 107
 108                         dap2_sclk_pa3 {
 109                                 nvidia,pins = "dap2_sclk_pa3";
 110                                 nvidia,function = "i2s1";
 111                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 112                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 113                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 114                         };
 115
 116                         dap2_din_pa4 {
 117                                 nvidia,pins = "dap2_din_pa4";
 118                                 nvidia,function = "i2s1";
 119                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 120                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 121                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 122                         };
 123
 124                         dap2_dout_pa5 {
 125                                 nvidia,pins = "dap2_dout_pa5";
 126                                 nvidia,function = "i2s1";
 127                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 128                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 129                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 130                         };
 131
 132                         sdmmc3_clk_pa6 {
 133                                 nvidia,pins = "sdmmc3_clk_pa6";
 134                                 nvidia,function = "sdmmc3";
 135                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 136                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 137                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 138                         };
 139
 140                         sdmmc3_cmd_pa7 {
 141                                 nvidia,pins = "sdmmc3_cmd_pa7";
 142                                 nvidia,function = "sdmmc3";
 143                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 144                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 145                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 146                         };
 147
 148                         gmi_a17_pb0 {
 149                                 nvidia,pins = "gmi_a17_pb0";
 150                                 nvidia,function = "spi4";
 151                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 152                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 153                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 154                         };
 155
 156                         gmi_a18_pb1 {
 157                                 nvidia,pins = "gmi_a18_pb1";
 158                                 nvidia,function = "spi4";
 159                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 160                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 161                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 162                         };
 163
 164                         lcd_pwr0_pb2 {
 165                                 nvidia,pins = "lcd_pwr0_pb2";
 166                                 nvidia,function = "displaya";
 167                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 168                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 169                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 170                         };
 171
 172                         lcd_pclk_pb3 {
 173                                 nvidia,pins = "lcd_pclk_pb3";
 174                                 nvidia,function = "displaya";
 175                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 176                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 177                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 178                         };
 179
 180                         sdmmc3_dat3_pb4 {
 181                                 nvidia,pins = "sdmmc3_dat3_pb4";
 182                                 nvidia,function = "sdmmc3";
 183                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 184                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 185                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 186                         };
 187
 188                         sdmmc3_dat2_pb5 {
 189                                 nvidia,pins = "sdmmc3_dat2_pb5";
 190                                 nvidia,function = "sdmmc3";
 191                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 192                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 193                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 194                         };
 195
 196                         sdmmc3_dat1_pb6 {
 197                                 nvidia,pins = "sdmmc3_dat1_pb6";
 198                                 nvidia,function = "sdmmc3";
 199                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 200                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 201                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 202                         };
 203
 204                         sdmmc3_dat0_pb7 {
 205                                 nvidia,pins = "sdmmc3_dat0_pb7";
 206                                 nvidia,function = "sdmmc3";
 207                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 208                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 209                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 210                         };
 211
 212                         uart3_rts_n_pc0 {
 213                                 nvidia,pins = "uart3_rts_n_pc0";
 214                                 nvidia,function = "uartc";
 215                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 216                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 217                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 218                         };
 219
 220                         lcd_pwr1_pc1 {
 221                                 nvidia,pins = "lcd_pwr1_pc1";
 222                                 nvidia,function = "displaya";
 223                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 224                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 225                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 226                         };
 227
 228                         uart2_txd_pc2 {
 229                                 nvidia,pins = "uart2_txd_pc2";
 230                                 nvidia,function = "uartb";
 231                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 232                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 233                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 234                         };
 235
 236                         uart2_rxd_pc3 {
 237                                 nvidia,pins = "uart2_rxd_pc3";
 238                                 nvidia,function = "uartb";
 239                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 240                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 241                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 242                         };
 243
 244                         gen1_i2c_scl_pc4 {
 245                                 nvidia,pins = "gen1_i2c_scl_pc4";
 246                                 nvidia,function = "i2c1";
 247                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 248                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 249                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 250                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 251                         };
 252
 253                         gen1_i2c_sda_pc5 {
 254                                 nvidia,pins = "gen1_i2c_sda_pc5";
 255                                 nvidia,function = "i2c1";
 256                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 257                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 258                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 259                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 260                         };
 261
 262                         lcd_pwr2_pc6 {
 263                                 nvidia,pins = "lcd_pwr2_pc6";
 264                                 nvidia,function = "displaya";
 265                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 266                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 267                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 268                         };
 269
 270                         gmi_wp_n_pc7 {
 271                                 nvidia,pins = "gmi_wp_n_pc7";
 272                                 nvidia,function = "gmi";
 273                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 274                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 275                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 276                         };
 277
 278                         sdmmc3_dat5_pd0 {
 279                                 nvidia,pins = "sdmmc3_dat5_pd0";
 280                                 nvidia,function = "sdmmc3";
 281                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 282                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 283                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 284                         };
 285
 286                         sdmmc3_dat4_pd1 {
 287                                 nvidia,pins = "sdmmc3_dat4_pd1";
 288                                 nvidia,function = "sdmmc3";
 289                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 290                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 291                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 292                         };
 293
 294                         lcd_dc1_pd2 {
 295                                 nvidia,pins = "lcd_dc1_pd2";
 296                                 nvidia,function = "displaya";
 297                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 298                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 299                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 300                         };
 301
 302                         sdmmc3_dat6_pd3 {
 303                                 nvidia,pins = "sdmmc3_dat6_pd3";
 304                                 nvidia,function = "spi4";
 305                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 306                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 307                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 308                         };
 309
 310                         sdmmc3_dat7_pd4 {
 311                                 nvidia,pins = "sdmmc3_dat7_pd4";
 312                                 nvidia,function = "spi4";
 313                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 314                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 315                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 316                         };
 317
 318                         vi_d1_pd5 {
 319                                 nvidia,pins = "vi_d1_pd5";
 320                                 nvidia,function = "sdmmc2";
 321                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 322                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 323                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 324                         };
 325
 326                         vi_vsync_pd6 {
 327                                 nvidia,pins = "vi_vsync_pd6";
 328                                 nvidia,function = "ddr";
 329                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 330                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 331                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 332                         };
 333
 334                         vi_hsync_pd7 {
 335                                 nvidia,pins = "vi_hsync_pd7";
 336                                 nvidia,function = "ddr";
 337                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 338                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 339                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 340                         };
 341
 342                         lcd_d0_pe0 {
 343                                 nvidia,pins = "lcd_d0_pe0";
 344                                 nvidia,function = "displaya";
 345                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 346                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 347                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 348                         };
 349
 350                         lcd_d1_pe1 {
 351                                 nvidia,pins = "lcd_d1_pe1";
 352                                 nvidia,function = "displaya";
 353                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 354                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 355                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 356                         };
 357
 358                         lcd_d2_pe2 {
 359                                 nvidia,pins = "lcd_d2_pe2";
 360                                 nvidia,function = "displaya";
 361                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 362                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 363                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 364                         };
 365
 366                         lcd_d3_pe3 {
 367                                 nvidia,pins = "lcd_d3_pe3";
 368                                 nvidia,function = "displaya";
 369                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 370                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 371                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 372                         };
 373
 374                         lcd_d4_pe4 {
 375                                 nvidia,pins = "lcd_d4_pe4";
 376                                 nvidia,function = "displaya";
 377                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 378                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 379                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 380                         };
 381
 382                         lcd_d5_pe5 {
 383                                 nvidia,pins = "lcd_d5_pe5";
 384                                 nvidia,function = "displaya";
 385                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 386                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 387                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 388                         };
 389
 390                         lcd_d6_pe6 {
 391                                 nvidia,pins = "lcd_d6_pe6";
 392                                 nvidia,function = "displaya";
 393                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 394                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 395                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 396                         };
 397
 398                         lcd_d7_pe7 {
 399                                 nvidia,pins = "lcd_d7_pe7";
 400                                 nvidia,function = "displaya";
 401                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 402                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 403                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 404                         };
 405
 406                         lcd_d8_pf0 {
 407                                 nvidia,pins = "lcd_d8_pf0";
 408                                 nvidia,function = "displaya";
 409                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 410                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 411                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 412                         };
 413
 414                         lcd_d9_pf1 {
 415                                 nvidia,pins = "lcd_d9_pf1";
 416                                 nvidia,function = "displaya";
 417                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 418                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 419                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 420                         };
 421
 422                         lcd_d10_pf2 {
 423                                 nvidia,pins = "lcd_d10_pf2";
 424                                 nvidia,function = "displaya";
 425                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 426                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 427                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 428                         };
 429
 430                         lcd_d11_pf3 {
 431                                 nvidia,pins = "lcd_d11_pf3";
 432                                 nvidia,function = "displaya";
 433                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 434                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 435                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 436                         };
 437
 438                         lcd_d12_pf4 {
 439                                 nvidia,pins = "lcd_d12_pf4";
 440                                 nvidia,function = "displaya";
 441                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 442                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 443                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 444                         };
 445
 446                         lcd_d13_pf5 {
 447                                 nvidia,pins = "lcd_d13_pf5";
 448                                 nvidia,function = "displaya";
 449                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 450                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 451                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 452                         };
 453
 454                         lcd_d14_pf6 {
 455                                 nvidia,pins = "lcd_d14_pf6";
 456                                 nvidia,function = "displaya";
 457                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 458                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 459                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 460                         };
 461
 462                         lcd_d15_pf7 {
 463                                 nvidia,pins = "lcd_d15_pf7";
 464                                 nvidia,function = "displaya";
 465                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 466                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 467                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 468                         };
 469
 470                         gmi_ad0_pg0 {
 471                                 nvidia,pins = "gmi_ad0_pg0";
 472                                 nvidia,function = "nand";
 473                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 474                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 475                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 476                         };
 477
 478                         gmi_ad1_pg1 {
 479                                 nvidia,pins = "gmi_ad1_pg1";
 480                                 nvidia,function = "nand";
 481                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 482                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 483                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 484                         };
 485
 486                         gmi_ad2_pg2 {
 487                                 nvidia,pins = "gmi_ad2_pg2";
 488                                 nvidia,function = "nand";
 489                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 490                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 491                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 492                         };
 493
 494                         gmi_ad3_pg3 {
 495                                 nvidia,pins = "gmi_ad3_pg3";
 496                                 nvidia,function = "nand";
 497                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 498                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 499                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 500                         };
 501
 502                         gmi_ad4_pg4 {
 503                                 nvidia,pins = "gmi_ad4_pg4";
 504                                 nvidia,function = "nand";
 505                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 506                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 507                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 508                         };
 509
 510                         gmi_ad5_pg5 {
 511                                 nvidia,pins = "gmi_ad5_pg5";
 512                                 nvidia,function = "nand";
 513                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 514                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 515                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 516                         };
 517
 518                         gmi_ad6_pg6 {
 519                                 nvidia,pins = "gmi_ad6_pg6";
 520                                 nvidia,function = "nand";
 521                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 522                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 523                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 524                         };
 525
 526                         gmi_ad7_pg7 {
 527                                 nvidia,pins = "gmi_ad7_pg7";
 528                                 nvidia,function = "nand";
 529                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 530                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 531                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 532                         };
 533
 534                         gmi_ad8_ph0 {
 535                                 nvidia,pins = "gmi_ad8_ph0";
 536                                 nvidia,function = "pwm0";
 537                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 538                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 539                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 540                         };
 541
 542                         gmi_ad9_ph1 {
 543                                 nvidia,pins = "gmi_ad9_ph1";
 544                                 nvidia,function = "pwm1";
 545                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 546                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 547                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 548                         };
 549
 550                         gmi_ad10_ph2 {
 551                                 nvidia,pins = "gmi_ad10_ph2";
 552                                 nvidia,function = "pwm2";
 553                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 554                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 555                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 556                         };
 557
 558                         gmi_ad11_ph3 {
 559                                 nvidia,pins = "gmi_ad11_ph3";
 560                                 nvidia,function = "nand";
 561                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 562                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 563                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 564                         };
 565
 566                         gmi_ad12_ph4 {
 567                                 nvidia,pins = "gmi_ad12_ph4";
 568                                 nvidia,function = "nand";
 569                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 570                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 571                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 572                         };
 573
 574                         gmi_ad13_ph5 {
 575                                 nvidia,pins = "gmi_ad13_ph5";
 576                                 nvidia,function = "nand";
 577                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 578                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 579                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 580                         };
 581
 582                         gmi_ad14_ph6 {
 583                                 nvidia,pins = "gmi_ad14_ph6";
 584                                 nvidia,function = "nand";
 585                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 586                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 587                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 588                         };
 589
 590                         gmi_wr_n_pi0 {
 591                                 nvidia,pins = "gmi_wr_n_pi0";
 592                                 nvidia,function = "nand";
 593                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 594                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 595                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 596                         };
 597
 598                         gmi_oe_n_pi1 {
 599                                 nvidia,pins = "gmi_oe_n_pi1";
 600                                 nvidia,function = "nand";
 601                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 602                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 603                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 604                         };
 605
 606                         gmi_dqs_pi2 {
 607                                 nvidia,pins = "gmi_dqs_pi2";
 608                                 nvidia,function = "nand";
 609                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 610                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 611                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 612                         };
 613
 614                         gmi_iordy_pi5 {
 615                                 nvidia,pins = "gmi_iordy_pi5";
 616                                 nvidia,function = "rsvd1";
 617                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 618                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 619                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 620                         };
 621
 622                         gmi_cs7_n_pi6 {
 623                                 nvidia,pins = "gmi_cs7_n_pi6";
 624                                 nvidia,function = "nand";
 625                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 626                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 627                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 628                         };
 629
 630                         gmi_wait_pi7 {
 631                                 nvidia,pins = "gmi_wait_pi7";
 632                                 nvidia,function = "nand";
 633                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 634                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 635                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 636                         };
 637
 638                         lcd_de_pj1 {
 639                                 nvidia,pins = "lcd_de_pj1";
 640                                 nvidia,function = "displaya";
 641                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 642                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 643                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 644                         };
 645
 646                         gmi_cs1_n_pj2 {
 647                                 nvidia,pins = "gmi_cs1_n_pj2";
 648                                 nvidia,function = "rsvd1";
 649                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 650                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 651                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 652                         };
 653
 654                         lcd_hsync_pj3 {
 655                                 nvidia,pins = "lcd_hsync_pj3";
 656                                 nvidia,function = "displaya";
 657                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 658                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 659                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 660                         };
 661
 662                         lcd_vsync_pj4 {
 663                                 nvidia,pins = "lcd_vsync_pj4";
 664                                 nvidia,function = "displaya";
 665                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 666                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 667                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 668                         };
 669
 670                         uart2_cts_n_pj5 {
 671                                 nvidia,pins = "uart2_cts_n_pj5";
 672                                 nvidia,function = "uartb";
 673                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 674                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 675                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 676                         };
 677
 678                         uart2_rts_n_pj6 {
 679                                 nvidia,pins = "uart2_rts_n_pj6";
 680                                 nvidia,function = "uartb";
 681                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 682                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 683                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 684                         };
 685
 686                         gmi_a16_pj7 {
 687                                 nvidia,pins = "gmi_a16_pj7";
 688                                 nvidia,function = "spi4";
 689                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 690                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 691                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 692                         };
 693
 694                         gmi_adv_n_pk0 {
 695                                 nvidia,pins = "gmi_adv_n_pk0";
 696                                 nvidia,function = "nand";
 697                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 698                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 699                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 700                         };
 701
 702                         gmi_clk_pk1 {
 703                                 nvidia,pins = "gmi_clk_pk1";
 704                                 nvidia,function = "nand";
 705                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 706                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 707                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 708                         };
 709
 710                         gmi_cs2_n_pk3 {
 711                                 nvidia,pins = "gmi_cs2_n_pk3";
 712                                 nvidia,function = "rsvd1";
 713                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 714                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 715                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 716                         };
 717
 718                         gmi_cs3_n_pk4 {
 719                                 nvidia,pins = "gmi_cs3_n_pk4";
 720                                 nvidia,function = "nand";
 721                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 722                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 723                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 724                         };
 725
 726                         spdif_out_pk5 {
 727                                 nvidia,pins = "spdif_out_pk5";
 728                                 nvidia,function = "spdif";
 729                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 730                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 731                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 732                         };
 733
 734                         spdif_in_pk6 {
 735                                 nvidia,pins = "spdif_in_pk6";
 736                                 nvidia,function = "spdif";
 737                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 738                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 739                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 740                         };
 741
 742                         gmi_a19_pk7 {
 743                                 nvidia,pins = "gmi_a19_pk7";
 744                                 nvidia,function = "spi4";
 745                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 746                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 747                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 748                         };
 749
 750                         vi_d2_pl0 {
 751                                 nvidia,pins = "vi_d2_pl0";
 752                                 nvidia,function = "sdmmc2";
 753                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 754                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 755                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 756                         };
 757
 758                         vi_d3_pl1 {
 759                                 nvidia,pins = "vi_d3_pl1";
 760                                 nvidia,function = "sdmmc2";
 761                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 762                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 763                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 764                         };
 765
 766                         vi_d4_pl2 {
 767                                 nvidia,pins = "vi_d4_pl2";
 768                                 nvidia,function = "vi";
 769                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 770                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 771                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 772                         };
 773
 774                         vi_d5_pl3 {
 775                                 nvidia,pins = "vi_d5_pl3";
 776                                 nvidia,function = "sdmmc2";
 777                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 778                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 779                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 780                         };
 781
 782                         vi_d6_pl4 {
 783                                 nvidia,pins = "vi_d6_pl4";
 784                                 nvidia,function = "vi";
 785                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 786                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 787                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 788                         };
 789
 790                         vi_d7_pl5 {
 791                                 nvidia,pins = "vi_d7_pl5";
 792                                 nvidia,function = "sdmmc2";
 793                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 794                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 795                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 796                         };
 797
 798                         vi_d8_pl6 {
 799                                 nvidia,pins = "vi_d8_pl6";
 800                                 nvidia,function = "sdmmc2";
 801                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 802                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 803                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 804                         };
 805
 806                         vi_d9_pl7 {
 807                                 nvidia,pins = "vi_d9_pl7";
 808                                 nvidia,function = "sdmmc2";
 809                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 810                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 811                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 812                         };
 813
 814                         lcd_d16_pm0 {
 815                                 nvidia,pins = "lcd_d16_pm0";
 816                                 nvidia,function = "displaya";
 817                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 818                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 819                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 820                         };
 821
 822                         lcd_d17_pm1 {
 823                                 nvidia,pins = "lcd_d17_pm1";
 824                                 nvidia,function = "displaya";
 825                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 826                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 827                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 828                         };
 829
 830                         lcd_d18_pm2 {
 831                                 nvidia,pins = "lcd_d18_pm2";
 832                                 nvidia,function = "displaya";
 833                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 834                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 835                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 836                         };
 837
 838                         lcd_d19_pm3 {
 839                                 nvidia,pins = "lcd_d19_pm3";
 840                                 nvidia,function = "displaya";
 841                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 842                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 843                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 844                         };
 845
 846                         lcd_d20_pm4 {
 847                                 nvidia,pins = "lcd_d20_pm4";
 848                                 nvidia,function = "displaya";
 849                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 850                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 851                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 852                         };
 853
 854                         lcd_d21_pm5 {
 855                                 nvidia,pins = "lcd_d21_pm5";
 856                                 nvidia,function = "displaya";
 857                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 858                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 859                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 860                         };
 861
 862                         lcd_d22_pm6 {
 863                                 nvidia,pins = "lcd_d22_pm6";
 864                                 nvidia,function = "displaya";
 865                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 866                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 867                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 868                         };
 869
 870                         lcd_d23_pm7 {
 871                                 nvidia,pins = "lcd_d23_pm7";
 872                                 nvidia,function = "displaya";
 873                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 874                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 875                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 876                         };
 877
 878                         dap1_fs_pn0 {
 879                                 nvidia,pins = "dap1_fs_pn0";
 880                                 nvidia,function = "i2s0";
 881                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 882                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 883                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 884                         };
 885
 886                         dap1_din_pn1 {
 887                                 nvidia,pins = "dap1_din_pn1";
 888                                 nvidia,function = "i2s0";
 889                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 890                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 891                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 892                         };
 893
 894                         dap1_dout_pn2 {
 895                                 nvidia,pins = "dap1_dout_pn2";
 896                                 nvidia,function = "i2s0";
 897                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 898                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 899                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 900                         };
 901
 902                         dap1_sclk_pn3 {
 903                                 nvidia,pins = "dap1_sclk_pn3";
 904                                 nvidia,function = "i2s0";
 905                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 906                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 907                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 908                         };
 909
 910                         lcd_cs0_n_pn4 {
 911                                 nvidia,pins = "lcd_cs0_n_pn4";
 912                                 nvidia,function = "displaya";
 913                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 914                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 915                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 916                         };
 917
 918                         lcd_sdout_pn5 {
 919                                 nvidia,pins = "lcd_sdout_pn5";
 920                                 nvidia,function = "displaya";
 921                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 922                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 923                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 924                         };
 925
 926                         lcd_dc0_pn6 {
 927                                 nvidia,pins = "lcd_dc0_pn6";
 928                                 nvidia,function = "displaya";
 929                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 930                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 931                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 932                         };
 933
 934                         hdmi_int_pn7 {
 935                                 nvidia,pins = "hdmi_int_pn7";
 936                                 nvidia,function = "hdmi";
 937                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 938                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 939                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 940                         };
 941
 942                         ulpi_data7_po0 {
 943                                 nvidia,pins = "ulpi_data7_po0";
 944                                 nvidia,function = "uarta";
 945                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 946                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 947                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 948                         };
 949
 950                         ulpi_data0_po1 {
 951                                 nvidia,pins = "ulpi_data0_po1";
 952                                 nvidia,function = "uarta";
 953                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 954                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 955                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 956                         };
 957
 958                         ulpi_data1_po2 {
 959                                 nvidia,pins = "ulpi_data1_po2";
 960                                 nvidia,function = "uarta";
 961                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 962                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 963                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 964                         };
 965
 966                         ulpi_data2_po3 {
 967                                 nvidia,pins = "ulpi_data2_po3";
 968                                 nvidia,function = "uarta";
 969                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 970                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 971                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 972                         };
 973
 974                         ulpi_data3_po4 {
 975                                 nvidia,pins = "ulpi_data3_po4";
 976                                 nvidia,function = "uarta";
 977                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 978                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 979                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 980                         };
 981
 982                         ulpi_data4_po5 {
 983                                 nvidia,pins = "ulpi_data4_po5";
 984                                 nvidia,function = "uarta";
 985                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 986                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 987                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 988                         };
 989
 990                         ulpi_data5_po6 {
 991                                 nvidia,pins = "ulpi_data5_po6";
 992                                 nvidia,function = "uarta";
 993                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 994                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 995                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 996                         };
 997
 998                         ulpi_data6_po7 {
 999                                 nvidia,pins = "ulpi_data6_po7";
1000                                 nvidia,function = "uarta";
1001                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1002                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1003                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1004                         };
1005
1006                         dap3_fs_pp0 {
1007                                 nvidia,pins = "dap3_fs_pp0";
1008                                 nvidia,function = "i2s2";
1009                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1010                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1011                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1012                         };
1013
1014                         dap3_din_pp1 {
1015                                 nvidia,pins = "dap3_din_pp1";
1016                                 nvidia,function = "i2s2";
1017                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1018                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1019                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1020                         };
1021
1022                         dap3_dout_pp2 {
1023                                 nvidia,pins = "dap3_dout_pp2";
1024                                 nvidia,function = "i2s2";
1025                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1026                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1027                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1028                         };
1029
1030                         dap3_sclk_pp3 {
1031                                 nvidia,pins = "dap3_sclk_pp3";
1032                                 nvidia,function = "i2s2";
1033                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1034                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1035                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1036                         };
1037
1038                         dap4_fs_pp4 {
1039                                 nvidia,pins = "dap4_fs_pp4";
1040                                 nvidia,function = "i2s3";
1041                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1042                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1043                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1044                         };
1045
1046                         dap4_din_pp5 {
1047                                 nvidia,pins = "dap4_din_pp5";
1048                                 nvidia,function = "i2s3";
1049                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1050                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1051                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1052                         };
1053
1054                         dap4_dout_pp6 {
1055                                 nvidia,pins = "dap4_dout_pp6";
1056                                 nvidia,function = "i2s3";
1057                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1058                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1059                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1060                         };
1061
1062                         dap4_sclk_pp7 {
1063                                 nvidia,pins = "dap4_sclk_pp7";
1064                                 nvidia,function = "i2s3";
1065                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1066                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1067                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1068                         };
1069
1070                         kb_col0_pq0 {
1071                                 nvidia,pins = "kb_col0_pq0";
1072                                 nvidia,function = "kbc";
1073                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1074                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1075                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1076                         };
1077
1078                         kb_col1_pq1 {
1079                                 nvidia,pins = "kb_col1_pq1";
1080                                 nvidia,function = "kbc";
1081                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1082                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1083                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1084                         };
1085
1086                         kb_col2_pq2 {
1087                                 nvidia,pins = "kb_col2_pq2";
1088                                 nvidia,function = "kbc";
1089                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1090                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1091                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1092                         };
1093
1094                         kb_col3_pq3 {
1095                                 nvidia,pins = "kb_col3_pq3";
1096                                 nvidia,function = "kbc";
1097                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1098                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1099                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1100                         };
1101
1102                         kb_col4_pq4 {
1103                                 nvidia,pins = "kb_col4_pq4";
1104                                 nvidia,function = "kbc";
1105                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1106                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1107                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1108                         };
1109
1110                         kb_col5_pq5 {
1111                                 nvidia,pins = "kb_col5_pq5";
1112                                 nvidia,function = "kbc";
1113                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1114                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1115                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1116                         };
1117
1118                         kb_col6_pq6 {
1119                                 nvidia,pins = "kb_col6_pq6";
1120                                 nvidia,function = "kbc";
1121                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1122                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1123                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1124                         };
1125
1126                         kb_col7_pq7 {
1127                                 nvidia,pins = "kb_col7_pq7";
1128                                 nvidia,function = "kbc";
1129                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1130                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1131                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1132                         };
1133
1134                         kb_row0_pr0 {
1135                                 nvidia,pins = "kb_row0_pr0";
1136                                 nvidia,function = "kbc";
1137                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1138                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1139                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1140                         };
1141
1142                         kb_row1_pr1 {
1143                                 nvidia,pins = "kb_row1_pr1";
1144                                 nvidia,function = "kbc";
1145                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1146                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1147                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1148                         };
1149
1150                         kb_row2_pr2 {
1151                                 nvidia,pins = "kb_row2_pr2";
1152                                 nvidia,function = "kbc";
1153                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1154                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1155                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1156                         };
1157
1158                         kb_row3_pr3 {
1159                                 nvidia,pins = "kb_row3_pr3";
1160                                 nvidia,function = "kbc";
1161                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1162                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1163                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1164                         };
1165
1166                         kb_row4_pr4 {
1167                                 nvidia,pins = "kb_row4_pr4";
1168                                 nvidia,function = "kbc";
1169                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1170                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1171                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1172                         };
1173
1174                         kb_row5_pr5 {
1175                                 nvidia,pins = "kb_row5_pr5";
1176                                 nvidia,function = "kbc";
1177                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1178                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1179                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1180                         };
1181
1182                         kb_row6_pr6 {
1183                                 nvidia,pins = "kb_row6_pr6";
1184                                 nvidia,function = "kbc";
1185                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1186                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1187                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1188                         };
1189
1190                         kb_row7_pr7 {
1191                                 nvidia,pins = "kb_row7_pr7";
1192                                 nvidia,function = "kbc";
1193                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1194                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1195                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1196                         };
1197
1198                         kb_row8_ps0 {
1199                                 nvidia,pins = "kb_row8_ps0";
1200                                 nvidia,function = "kbc";
1201                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1202                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1203                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1204                         };
1205
1206                         kb_row9_ps1 {
1207                                 nvidia,pins = "kb_row9_ps1";
1208                                 nvidia,function = "kbc";
1209                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1210                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1211                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1212                         };
1213
1214                         kb_row10_ps2 {
1215                                 nvidia,pins = "kb_row10_ps2";
1216                                 nvidia,function = "kbc";
1217                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1218                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1219                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1220                         };
1221
1222                         kb_row11_ps3 {
1223                                 nvidia,pins = "kb_row11_ps3";
1224                                 nvidia,function = "kbc";
1225                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1226                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1227                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1228                         };
1229
1230                         kb_row12_ps4 {
1231                                 nvidia,pins = "kb_row12_ps4";
1232                                 nvidia,function = "kbc";
1233                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1234                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1235                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1236                         };
1237
1238                         kb_row13_ps5 {
1239                                 nvidia,pins = "kb_row13_ps5";
1240                                 nvidia,function = "kbc";
1241                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1242                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1243                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1244                         };
1245
1246                         kb_row14_ps6 {
1247                                 nvidia,pins = "kb_row14_ps6";
1248                                 nvidia,function = "kbc";
1249                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1250                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1251                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1252                         };
1253
1254                         kb_row15_ps7 {
1255                                 nvidia,pins = "kb_row15_ps7";
1256                                 nvidia,function = "kbc";
1257                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1258                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1259                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1260                         };
1261
1262                         vi_pclk_pt0 {
1263                                 nvidia,pins = "vi_pclk_pt0";
1264                                 nvidia,function = "rsvd1";
1265                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1266                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1267                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1268                         };
1269
1270                         vi_mclk_pt1 {
1271                                 nvidia,pins = "vi_mclk_pt1";
1272                                 nvidia,function = "vi";
1273                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1274                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1275                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1276                         };
1277
1278                         vi_d10_pt2 {
1279                                 nvidia,pins = "vi_d10_pt2";
1280                                 nvidia,function = "ddr";
1281                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1282                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1283                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1284                         };
1285
1286                         vi_d11_pt3 {
1287                                 nvidia,pins = "vi_d11_pt3";
1288                                 nvidia,function = "ddr";
1289                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1290                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1291                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1292                         };
1293
1294                         vi_d0_pt4 {
1295                                 nvidia,pins = "vi_d0_pt4";
1296                                 nvidia,function = "ddr";
1297                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1298                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1299                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1300                         };
1301
1302                         gen2_i2c_scl_pt5 {
1303                                 nvidia,pins = "gen2_i2c_scl_pt5";
1304                                 nvidia,function = "i2c2";
1305                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1306                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1307                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1308                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1309                         };
1310
1311                         gen2_i2c_sda_pt6 {
1312                                 nvidia,pins = "gen2_i2c_sda_pt6";
1313                                 nvidia,function = "i2c2";
1314                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1315                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1316                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1317                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1318                         };
1319
1320                         sdmmc4_cmd_pt7 {
1321                                 nvidia,pins = "sdmmc4_cmd_pt7";
1322                                 nvidia,function = "sdmmc4";
1323                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1324                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1325                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1326                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1327                         };
1328
1329                         pu0 {
1330                                 nvidia,pins = "pu0";
1331                                 nvidia,function = "owr";
1332                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1333                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1334                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1335                         };
1336
1337                         pu1 {
1338                                 nvidia,pins = "pu1";
1339                                 nvidia,function = "rsvd1";
1340                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1341                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1342                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1343                         };
1344
1345                         pu2 {
1346                                 nvidia,pins = "pu2";
1347                                 nvidia,function = "rsvd1";
1348                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1349                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1350                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1351                         };
1352
1353                         pu3 {
1354                                 nvidia,pins = "pu3";
1355                                 nvidia,function = "pwm0";
1356                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1357                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1358                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1359                         };
1360
1361                         pu4 {
1362                                 nvidia,pins = "pu4";
1363                                 nvidia,function = "pwm1";
1364                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1365                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1366                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1367                         };
1368
1369                         pu5 {
1370                                 nvidia,pins = "pu5";
1371                                 nvidia,function = "rsvd4";
1372                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1373                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1374                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1375                         };
1376
1377                         pu6 {
1378                                 nvidia,pins = "pu6";
1379                                 nvidia,function = "pwm3";
1380                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1381                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1382                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1383                         };
1384
1385                         jtag_rtck_pu7 {
1386                                 nvidia,pins = "jtag_rtck_pu7";
1387                                 nvidia,function = "rtck";
1388                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1389                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1390                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1391                         };
1392
1393                         pv0 {
1394                                 nvidia,pins = "pv0";
1395                                 nvidia,function = "rsvd1";
1396                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1397                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1398                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1399                         };
1400
1401                         pv1 {
1402                                 nvidia,pins = "pv1";
1403                                 nvidia,function = "rsvd1";
1404                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1405                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1406                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1407                         };
1408
1409                         pv2 {
1410                                 nvidia,pins = "pv2";
1411                                 nvidia,function = "owr";
1412                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1413                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1414                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1415                         };
1416
1417                         pv3 {
1418                                 nvidia,pins = "pv3";
1419                                 nvidia,function = "clk_12m_out";
1420                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1421                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1422                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1423                         };
1424
1425                         ddc_scl_pv4 {
1426                                 nvidia,pins = "ddc_scl_pv4";
1427                                 nvidia,function = "i2c4";
1428                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1429                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1430                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1431                         };
1432
1433                         ddc_sda_pv5 {
1434                                 nvidia,pins = "ddc_sda_pv5";
1435                                 nvidia,function = "i2c4";
1436                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1437                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1438                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1439                         };
1440
1441                         crt_hsync_pv6 {
1442                                 nvidia,pins = "crt_hsync_pv6";
1443                                 nvidia,function = "crt";
1444                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1445                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1446                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1447                         };
1448
1449                         crt_vsync_pv7 {
1450                                 nvidia,pins = "crt_vsync_pv7";
1451                                 nvidia,function = "crt";
1452                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1453                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1454                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1455                         };
1456
1457                         lcd_cs1_n_pw0 {
1458                                 nvidia,pins = "lcd_cs1_n_pw0";
1459                                 nvidia,function = "displaya";
1460                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1461                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1462                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1463                         };
1464
1465                         lcd_m1_pw1 {
1466                                 nvidia,pins = "lcd_m1_pw1";
1467                                 nvidia,function = "displaya";
1468                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1469                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1470                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1471                         };
1472
1473                         spi2_cs1_n_pw2 {
1474                                 nvidia,pins = "spi2_cs1_n_pw2";
1475                                 nvidia,function = "spi2";
1476                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1477                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1478                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1479                         };
1480
1481                         clk1_out_pw4 {
1482                                 nvidia,pins = "clk1_out_pw4";
1483                                 nvidia,function = "extperiph1";
1484                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1485                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1486                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1487                         };
1488
1489                         clk2_out_pw5 {
1490                                 nvidia,pins = "clk2_out_pw5";
1491                                 nvidia,function = "extperiph2";
1492                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1493                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1494                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1495                         };
1496
1497                         uart3_txd_pw6 {
1498                                 nvidia,pins = "uart3_txd_pw6";
1499                                 nvidia,function = "uartc";
1500                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1501                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1502                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1503                         };
1504
1505                         uart3_rxd_pw7 {
1506                                 nvidia,pins = "uart3_rxd_pw7";
1507                                 nvidia,function = "uartc";
1508                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1509                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1510                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1511                         };
1512
1513                         spi2_sck_px2 {
1514                                 nvidia,pins = "spi2_sck_px2";
1515                                 nvidia,function = "gmi";
1516                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1517                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1518                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1519                         };
1520
1521                         spi1_mosi_px4 {
1522                                 nvidia,pins = "spi1_mosi_px4";
1523                                 nvidia,function = "spi1";
1524                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1525                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1526                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1527                         };
1528
1529                         spi1_sck_px5 {
1530                                 nvidia,pins = "spi1_sck_px5";
1531                                 nvidia,function = "spi1";
1532                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1533                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1534                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1535                         };
1536
1537                         spi1_cs0_n_px6 {
1538                                 nvidia,pins = "spi1_cs0_n_px6";
1539                                 nvidia,function = "spi1";
1540                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1541                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1542                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1543                         };
1544
1545                         spi1_miso_px7 {
1546                                 nvidia,pins = "spi1_miso_px7";
1547                                 nvidia,function = "spi1";
1548                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1549                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1550                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1551                         };
1552
1553                         ulpi_clk_py0 {
1554                                 nvidia,pins = "ulpi_clk_py0";
1555                                 nvidia,function = "uartd";
1556                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1557                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1558                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1559                         };
1560
1561                         ulpi_dir_py1 {
1562                                 nvidia,pins = "ulpi_dir_py1";
1563                                 nvidia,function = "uartd";
1564                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1565                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1566                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1567                         };
1568
1569                         ulpi_nxt_py2 {
1570                                 nvidia,pins = "ulpi_nxt_py2";
1571                                 nvidia,function = "uartd";
1572                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1573                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1574                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1575                         };
1576
1577                         ulpi_stp_py3 {
1578                                 nvidia,pins = "ulpi_stp_py3";
1579                                 nvidia,function = "uartd";
1580                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1581                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1582                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1583                         };
1584
1585                         sdmmc1_dat3_py4 {
1586                                 nvidia,pins = "sdmmc1_dat3_py4";
1587                                 nvidia,function = "sdmmc1";
1588                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1589                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1590                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1591                         };
1592
1593                         sdmmc1_dat2_py5 {
1594                                 nvidia,pins = "sdmmc1_dat2_py5";
1595                                 nvidia,function = "sdmmc1";
1596                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1597                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1598                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1599                         };
1600
1601                         sdmmc1_dat1_py6 {
1602                                 nvidia,pins = "sdmmc1_dat1_py6";
1603                                 nvidia,function = "sdmmc1";
1604                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1605                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1606                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1607                         };
1608
1609                         sdmmc1_dat0_py7 {
1610                                 nvidia,pins = "sdmmc1_dat0_py7";
1611                                 nvidia,function = "sdmmc1";
1612                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1613                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1614                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1615                         };
1616
1617                         sdmmc1_clk_pz0 {
1618                                 nvidia,pins = "sdmmc1_clk_pz0";
1619                                 nvidia,function = "sdmmc1";
1620                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1621                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1622                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1623                         };
1624
1625                         sdmmc1_cmd_pz1 {
1626                                 nvidia,pins = "sdmmc1_cmd_pz1";
1627                                 nvidia,function = "sdmmc1";
1628                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1629                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1630                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1631                         };
1632
1633                         lcd_sdin_pz2 {
1634                                 nvidia,pins = "lcd_sdin_pz2";
1635                                 nvidia,function = "displaya";
1636                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1637                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1638                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1639                         };
1640
1641                         lcd_wr_n_pz3 {
1642                                 nvidia,pins = "lcd_wr_n_pz3";
1643                                 nvidia,function = "displaya";
1644                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1645                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1646                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1647                         };
1648
1649                         lcd_sck_pz4 {
1650                                 nvidia,pins = "lcd_sck_pz4";
1651                                 nvidia,function = "displaya";
1652                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1653                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1654                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1655                         };
1656
1657                         sys_clk_req_pz5 {
1658                                 nvidia,pins = "sys_clk_req_pz5";
1659                                 nvidia,function = "sysclk";
1660                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1661                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1662                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1663                         };
1664
1665                         pwr_i2c_scl_pz6 {
1666                                 nvidia,pins = "pwr_i2c_scl_pz6";
1667                                 nvidia,function = "i2cpwr";
1668                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1669                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1670                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1671                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1672                         };
1673
1674                         pwr_i2c_sda_pz7 {
1675                                 nvidia,pins = "pwr_i2c_sda_pz7";
1676                                 nvidia,function = "i2cpwr";
1677                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1678                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1679                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1680                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1681                         };
1682
1683                         sdmmc4_dat0_paa0 {
1684                                 nvidia,pins = "sdmmc4_dat0_paa0";
1685                                 nvidia,function = "sdmmc4";
1686                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1687                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1688                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1689                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1690                         };
1691
1692                         sdmmc4_dat1_paa1 {
1693                                 nvidia,pins = "sdmmc4_dat1_paa1";
1694                                 nvidia,function = "sdmmc4";
1695                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1696                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1697                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1698                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1699                         };
1700
1701                         sdmmc4_dat2_paa2 {
1702                                 nvidia,pins = "sdmmc4_dat2_paa2";
1703                                 nvidia,function = "sdmmc4";
1704                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1705                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1706                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1707                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1708                         };
1709
1710                         sdmmc4_dat3_paa3 {
1711                                 nvidia,pins = "sdmmc4_dat3_paa3";
1712                                 nvidia,function = "sdmmc4";
1713                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1714                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1715                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1716                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1717                         };
1718
1719                         sdmmc4_dat4_paa4 {
1720                                 nvidia,pins = "sdmmc4_dat4_paa4";
1721                                 nvidia,function = "sdmmc4";
1722                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1723                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1724                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1725                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1726                         };
1727
1728                         sdmmc4_dat5_paa5 {
1729                                 nvidia,pins = "sdmmc4_dat5_paa5";
1730                                 nvidia,function = "sdmmc4";
1731                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1732                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1733                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1734                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1735                         };
1736
1737                         sdmmc4_dat6_paa6 {
1738                                 nvidia,pins = "sdmmc4_dat6_paa6";
1739                                 nvidia,function = "sdmmc4";
1740                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1741                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1742                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1743                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1744                         };
1745
1746                         sdmmc4_dat7_paa7 {
1747                                 nvidia,pins = "sdmmc4_dat7_paa7";
1748                                 nvidia,function = "sdmmc4";
1749                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1750                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1751                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1752                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1753                         };
1754
1755                         pbb0 {
1756                                 nvidia,pins = "pbb0";
1757                                 nvidia,function = "i2s4";
1758                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1759                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1760                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1761                         };
1762
1763                         cam_i2c_scl_pbb1 {
1764                                 nvidia,pins = "cam_i2c_scl_pbb1";
1765                                 nvidia,function = "i2c3";
1766                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1767                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1768                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1769                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1770                         };
1771
1772                         cam_i2c_sda_pbb2 {
1773                                 nvidia,pins = "cam_i2c_sda_pbb2";
1774                                 nvidia,function = "i2c3";
1775                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1776                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1777                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1778                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1779                         };
1780
1781                         pbb3 {
1782                                 nvidia,pins = "pbb3";
1783                                 nvidia,function = "vgp3";
1784                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1785                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1786                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1787                         };
1788
1789                         pbb4 {
1790                                 nvidia,pins = "pbb4";
1791                                 nvidia,function = "vgp4";
1792                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1793                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1794                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1795                         };
1796
1797                         pbb5 {
1798                                 nvidia,pins = "pbb5";
1799                                 nvidia,function = "vgp5";
1800                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1801                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1802                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1803                         };
1804
1805                         pbb6 {
1806                                 nvidia,pins = "pbb6";
1807                                 nvidia,function = "vgp6";
1808                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1809                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1810                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1811                         };
1812
1813                         pbb7 {
1814                                 nvidia,pins = "pbb7";
1815                                 nvidia,function = "i2s4";
1816                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1817                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1818                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1819                         };
1820
1821                         cam_mclk_pcc0 {
1822                                 nvidia,pins = "cam_mclk_pcc0";
1823                                 nvidia,function = "vi_alt3";
1824                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1825                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1826                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1827                         };
1828
1829                         pcc1 {
1830                                 nvidia,pins = "pcc1";
1831                                 nvidia,function = "i2s4";
1832                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1833                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1834                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1835                         };
1836
1837                         pcc2 {
1838                                 nvidia,pins = "pcc2";
1839                                 nvidia,function = "i2s4";
1840                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1841                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1842                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1843                         };
1844
1845                         sdmmc4_rst_n_pcc3 {
1846                                 nvidia,pins = "sdmmc4_rst_n_pcc3";
1847                                 nvidia,function = "sdmmc4";
1848                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1849                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1850                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1851                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1852                         };
1853
1854                         sdmmc4_clk_pcc4 {
1855                                 nvidia,pins = "sdmmc4_clk_pcc4";
1856                                 nvidia,function = "sdmmc4";
1857                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1858                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1859                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1860                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
1861                         };
1862
1863                         clk2_req_pcc5 {
1864                                 nvidia,pins = "clk2_req_pcc5";
1865                                 nvidia,function = "dap";
1866                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1867                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1868                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1869                         };
1870
1871                         pex_l2_rst_n_pcc6 {
1872                                 nvidia,pins = "pex_l2_rst_n_pcc6";
1873                                 nvidia,function = "pcie";
1874                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1875                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1876                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1877                         };
1878
1879                         pex_l2_clkreq_n_pcc7 {
1880                                 nvidia,pins = "pex_l2_clkreq_n_pcc7";
1881                                 nvidia,function = "pcie";
1882                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1883                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1884                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1885                         };
1886
1887                         pex_l0_prsnt_n_pdd0 {
1888                                 nvidia,pins = "pex_l0_prsnt_n_pdd0";
1889                                 nvidia,function = "pcie";
1890                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1891                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1892                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1893                         };
1894
1895                         pex_l0_rst_n_pdd1 {
1896                                 nvidia,pins = "pex_l0_rst_n_pdd1";
1897                                 nvidia,function = "pcie";
1898                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1899                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1900                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1901                         };
1902
1903                         pex_l0_clkreq_n_pdd2 {
1904                                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
1905                                 nvidia,function = "pcie";
1906                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1907                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1908                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1909                         };
1910
1911                         pex_wake_n_pdd3 {
1912                                 nvidia,pins = "pex_wake_n_pdd3";
1913                                 nvidia,function = "pcie";
1914                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1915                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1916                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1917                         };
1918
1919                         pex_l1_prsnt_n_pdd4 {
1920                                 nvidia,pins = "pex_l1_prsnt_n_pdd4";
1921                                 nvidia,function = "pcie";
1922                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1923                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1924                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1925                         };
1926
1927                         pex_l1_rst_n_pdd5 {
1928                                 nvidia,pins = "pex_l1_rst_n_pdd5";
1929                                 nvidia,function = "pcie";
1930                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1931                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1932                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1933                         };
1934
1935                         pex_l1_clkreq_n_pdd6 {
1936                                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
1937                                 nvidia,function = "pcie";
1938                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1939                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1940                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1941                         };
1942
1943                         pex_l2_prsnt_n_pdd7 {
1944                                 nvidia,pins = "pex_l2_prsnt_n_pdd7";
1945                                 nvidia,function = "pcie";
1946                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1947                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1948                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1949                         };
1950
1951                         clk3_out_pee0 {
1952                                 nvidia,pins = "clk3_out_pee0";
1953                                 nvidia,function = "extperiph3";
1954                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1955                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1956                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1957                         };
1958
1959                         clk3_req_pee1 {
1960                                 nvidia,pins = "clk3_req_pee1";
1961                                 nvidia,function = "dev3";
1962                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1963                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1964                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1965                         };
1966
1967                         clk1_req_pee2 {
1968                                 nvidia,pins = "clk1_req_pee2";
1969                                 nvidia,function = "dap";
1970                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1971                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1972                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1973                         };
1974
1975                         hdmi_cec_pee3 {
1976                                 nvidia,pins = "hdmi_cec_pee3";
1977                                 nvidia,function = "cec";
1978                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1979                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1980                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1981                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1982                         };
1983
1984                         owr {
1985                                 nvidia,pins = "owr";
1986                                 nvidia,function = "owr";
1987                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1988                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1989                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1990                         };
1991
1992                         drive_groups {
1993                                 nvidia,pins = "drive_gma",
1994                                               "drive_gmb",
1995                                               "drive_gmc",
1996                                               "drive_gmd";
1997                                 nvidia,pull-down-strength = <9>;
1998                                 nvidia,pull-up-strength = <9>;
1999                                 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
2000                                 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
2001                         };
2002                 };
2003         };
2004
2005         uartc: serial@70006200 {
2006                 compatible = "nvidia,tegra30-hsuart";
2007                 /delete-property/ reg-shift;
2008                 status = "okay";
2009
2010                 nvidia,adjust-baud-rates = <0 9600 100>,
2011                                            <9600 115200 200>,
2012                                            <1000000 4000000 136>;
2013
2014                 /* Azurewave AW-NH660 BCM4330B1 */
2015                 bluetooth {
2016                         compatible = "brcm,bcm4330-bt";
2017
2018                         interrupt-parent = <&gpio>;
2019                         interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
2020                         interrupt-names = "host-wakeup";
2021
2022                         max-speed = <4000000>;
2023
2024                         clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
2025                         clock-names = "txco";
2026
2027                         vbat-supply  = <&sys_3v3_reg>;
2028                         vddio-supply = <&vdd_1v8>;
2029
2030                         shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
2031                         device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
2032                 };
2033         };
2034
2035         uartd: serial@70006300 {
2036                 status = "okay";
2037         };
2038
2039         hdmi_ddc: i2c@7000c700 {
2040                 status = "okay";
2041                 clock-frequency = <100000>;
2042         };
2043
2044         i2c@7000d000 {
2045                 status = "okay";
2046                 clock-frequency = <400000>;
2047
2048                 pmic: pmic@2d {
2049                         compatible = "ti,tps65911";
2050                         reg = <0x2d>;
2051
2052                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2053                         #interrupt-cells = <2>;
2054                         interrupt-controller;
2055                         wakeup-source;
2056
2057                         ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
2058                         ti,system-power-controller;
2059                         ti,sleep-keep-ck32k;
2060                         ti,sleep-enable;
2061
2062                         #gpio-cells = <2>;
2063                         gpio-controller;
2064
2065                         vcc1-supply = <&vdd_5v0_reg>;
2066                         vcc2-supply = <&vdd_5v0_reg>;
2067                         vcc3-supply = <&vdd_1v8>;
2068                         vcc4-supply = <&vdd_5v0_reg>;
2069                         vcc5-supply = <&vdd_5v0_reg>;
2070                         vcc6-supply = <&vdd2_reg>;
2071                         vcc7-supply = <&vdd_5v0_reg>;
2072                         vccio-supply = <&vdd_5v0_reg>;
2073
2074                         regulators {
2075                                 vdd1_reg: vdd1 {
2076                                         regulator-name = "vddio_ddr_1v2";
2077                                         regulator-min-microvolt = <1200000>;
2078                                         regulator-max-microvolt = <1200000>;
2079                                         regulator-always-on;
2080                                 };
2081
2082                                 vdd2_reg: vdd2 {
2083                                         regulator-name = "vdd_1v5_gen";
2084                                         regulator-min-microvolt = <1500000>;
2085                                         regulator-max-microvolt = <1500000>;
2086                                         regulator-always-on;
2087                                 };
2088
2089                                 vdd_cpu: vddctrl {
2090                                         regulator-name = "vdd_cpu,vdd_sys";
2091                                         regulator-min-microvolt = <800000>;
2092                                         regulator-max-microvolt = <1270000>;
2093                                         regulator-coupled-with = <&vdd_core>;
2094                                         regulator-coupled-max-spread = <300000>;
2095                                         regulator-max-step-microvolt = <100000>;
2096                                         regulator-always-on;
2097
2098                                         nvidia,tegra-cpu-regulator;
2099                                 };
2100
2101                                 vdd_1v8: vio {
2102                                         regulator-name = "vdd_1v8_gen";
2103                                         regulator-min-microvolt = <1800000>;
2104                                         regulator-max-microvolt = <1800000>;
2105                                         regulator-always-on;
2106                                 };
2107
2108                                 ldo1_reg: ldo1 {
2109                                         regulator-name = "vdd_pexa,vdd_pexb";
2110                                         regulator-min-microvolt = <1050000>;
2111                                         regulator-max-microvolt = <1050000>;
2112                                         regulator-always-on;
2113                                 };
2114
2115                                 ldo2_reg: ldo2 {
2116                                         regulator-name = "vdd_sata,avdd_plle";
2117                                         regulator-min-microvolt = <1050000>;
2118                                         regulator-max-microvolt = <1050000>;
2119                                         regulator-always-on;
2120                                 };
2121
2122                                 /* LDO3 is not connected to anything */
2123
2124                                 ldo4_reg: ldo4 {
2125                                         regulator-name = "vdd_rtc";
2126                                         regulator-min-microvolt = <1200000>;
2127                                         regulator-max-microvolt = <1200000>;
2128                                         regulator-always-on;
2129                                 };
2130
2131                                 ldo5_reg: ldo5 {
2132                                         regulator-name = "vddio_sdmmc,avdd_vdac";
2133                                         regulator-min-microvolt = <1800000>;
2134                                         regulator-max-microvolt = <3300000>;
2135                                         regulator-always-on;
2136                                 };
2137
2138                                 ldo6_reg: ldo6 {
2139                                         regulator-name = "avdd_dsi_csi,pwrdet_mipi";
2140                                         regulator-min-microvolt = <1200000>;
2141                                         regulator-max-microvolt = <1200000>;
2142                                         regulator-always-on;
2143                                 };
2144
2145                                 ldo7_reg: ldo7 {
2146                                         regulator-name = "vdd_pllm,x,u,a_p_c_s";
2147                                         regulator-min-microvolt = <1200000>;
2148                                         regulator-max-microvolt = <1200000>;
2149                                         regulator-always-on;
2150                                 };
2151
2152                                 ldo8_reg: ldo8 {
2153                                         regulator-name = "vdd_ddr_hs";
2154                                         regulator-min-microvolt = <1000000>;
2155                                         regulator-max-microvolt = <1000000>;
2156                                         regulator-always-on;
2157                                 };
2158                         };
2159                 };
2160
2161                 cpu_temp: nct1008@4c {
2162                         compatible = "onnn,nct1008";
2163                         reg = <0x4c>;
2164                         vcc-supply = <&sys_3v3_reg>;
2165
2166                         interrupt-parent = <&gpio>;
2167                         interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
2168
2169                         #thermal-sensor-cells = <1>;
2170                 };
2171
2172                 vdd_core: tps62361@60 {
2173                         compatible = "ti,tps62361";
2174                         reg = <0x60>;
2175
2176                         regulator-name = "vdd_core";
2177                         regulator-min-microvolt = <950000>;
2178                         regulator-max-microvolt = <1350000>;
2179                         regulator-coupled-with = <&vdd_cpu>;
2180                         regulator-coupled-max-spread = <300000>;
2181                         regulator-max-step-microvolt = <100000>;
2182                         regulator-boot-on;
2183                         regulator-always-on;
2184                         ti,vsel0-state-high;
2185                         ti,vsel1-state-high;
2186                         ti,enable-vout-discharge;
2187
2188                         nvidia,tegra-core-regulator;
2189                 };
2190         };
2191
2192         pmc@7000e400 {
2193                 status = "okay";
2194                 nvidia,invert-interrupt;
2195                 nvidia,suspend-mode = <1>;
2196                 nvidia,cpu-pwr-good-time = <2000>;
2197                 nvidia,cpu-pwr-off-time = <200>;
2198                 nvidia,core-pwr-good-time = <3845 3845>;
2199                 nvidia,core-pwr-off-time = <458>;
2200                 nvidia,core-power-req-active-high;
2201                 nvidia,sys-clock-req-active-high;
2202                 core-supply = <&vdd_core>;
2203         };
2204
2205         memory-controller@7000f000 {
2206                 emc-timings-0 {
2207                         nvidia,ram-code = <0>; /* Samsung RAM */
2208
2209                         timing-25500000 {
2210                                 clock-frequency = <25500000>;
2211                                 nvidia,emem-configuration = <
2212                                         0x00030003 /* MC_EMEM_ARB_CFG */
2213                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2214                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2215                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2216                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
2217                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2218                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
2219                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2220                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2221                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2222                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2223                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2224                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2225                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2226                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2227                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
2228                                         0x75830303 /* MC_EMEM_ARB_MISC0 */
2229                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2230                                 >;
2231                         };
2232
2233                         timing-51000000 {
2234                                 clock-frequency = <51000000>;
2235                                 nvidia,emem-configuration = <
2236                                         0x00010003 /* MC_EMEM_ARB_CFG */
2237                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2238                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2239                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2240                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
2241                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2242                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
2243                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2244                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2245                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2246                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2247                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2248                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2249                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2250                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2251                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
2252                                         0x74630303 /* MC_EMEM_ARB_MISC0 */
2253                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2254                                 >;
2255                         };
2256
2257                         timing-102000000 {
2258                                 clock-frequency = <102000000>;
2259                                 nvidia,emem-configuration = <
2260                                         0x00000003 /* MC_EMEM_ARB_CFG */
2261                                         0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2262                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2263                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2264                                         0x00000003 /* MC_EMEM_ARB_TIMING_RC */
2265                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2266                                         0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
2267                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2268                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2269                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2270                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2271                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2272                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2273                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2274                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2275                                         0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
2276                                         0x73c30504 /* MC_EMEM_ARB_MISC0 */
2277                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2278                                 >;
2279                         };
2280
2281                         timing-204000000 {
2282                                 clock-frequency = <204000000>;
2283                                 nvidia,emem-configuration = <
2284                                         0x00000006 /* MC_EMEM_ARB_CFG */
2285                                         0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2286                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2287                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2288                                         0x00000005 /* MC_EMEM_ARB_TIMING_RC */
2289                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
2290                                         0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
2291                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2292                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2293                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2294                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2295                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2296                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2297                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2298                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2299                                         0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
2300                                         0x73840a06 /* MC_EMEM_ARB_MISC0 */
2301                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2302                                 >;
2303                         };
2304
2305                         timing-400000000 {
2306                                 clock-frequency = <400000000>;
2307                                 nvidia,emem-configuration = <
2308                                         0x0000000c /* MC_EMEM_ARB_CFG */
2309                                         0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2310                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2311                                         0x00000002 /* MC_EMEM_ARB_TIMING_RP */
2312                                         0x00000009 /* MC_EMEM_ARB_TIMING_RC */
2313                                         0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
2314                                         0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
2315                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2316                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2317                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2318                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2319                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
2320                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
2321                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2322                                         0x06030202 /* MC_EMEM_ARB_DA_TURNS */
2323                                         0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
2324                                         0x7086120a /* MC_EMEM_ARB_MISC0 */
2325                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2326                                 >;
2327                         };
2328
2329                         timing-800000000 {
2330                                 clock-frequency = <800000000>;
2331                                 nvidia,emem-configuration = <
2332                                         0x00000018 /* MC_EMEM_ARB_CFG */
2333                                         0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2334                                         0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
2335                                         0x00000005 /* MC_EMEM_ARB_TIMING_RP */
2336                                         0x00000013 /* MC_EMEM_ARB_TIMING_RC */
2337                                         0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
2338                                         0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
2339                                         0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
2340                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2341                                         0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
2342                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2343                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
2344                                         0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
2345                                         0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
2346                                         0x08040202 /* MC_EMEM_ARB_DA_TURNS */
2347                                         0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
2348                                         0x712c2414 /* MC_EMEM_ARB_MISC0 */
2349                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2350                                 >;
2351                         };
2352                 };
2353
2354                 emc-timings-1 {
2355                         nvidia,ram-code = <1>; /* Hynix M RAM */
2356
2357                         timing-25500000 {
2358                                 clock-frequency = <25500000>;
2359                                 nvidia,emem-configuration = <
2360                                         0x00030003 /* MC_EMEM_ARB_CFG */
2361                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2362                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2363                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2364                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
2365                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2366                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
2367                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2368                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2369                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2370                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2371                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2372                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2373                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2374                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2375                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
2376                                         0x75830303 /* MC_EMEM_ARB_MISC0 */
2377                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2378                                 >;
2379                         };
2380
2381                         timing-51000000 {
2382                                 clock-frequency = <51000000>;
2383                                 nvidia,emem-configuration = <
2384                                         0x00010003 /* MC_EMEM_ARB_CFG */
2385                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2386                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2387                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2388                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
2389                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2390                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
2391                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2392                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2393                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2394                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2395                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2396                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2397                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2398                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2399                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
2400                                         0x74630303 /* MC_EMEM_ARB_MISC0 */
2401                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2402                                 >;
2403                         };
2404
2405                         timing-102000000 {
2406                                 clock-frequency = <102000000>;
2407                                 nvidia,emem-configuration = <
2408                                         0x00000003 /* MC_EMEM_ARB_CFG */
2409                                         0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2410                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2411                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2412                                         0x00000003 /* MC_EMEM_ARB_TIMING_RC */
2413                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2414                                         0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
2415                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2416                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2417                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2418                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2419                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2420                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2421                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2422                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2423                                         0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
2424                                         0x73c30504 /* MC_EMEM_ARB_MISC0 */
2425                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2426                                 >;
2427                         };
2428
2429                         timing-204000000 {
2430                                 clock-frequency = <204000000>;
2431                                 nvidia,emem-configuration = <
2432                                         0x00000006 /* MC_EMEM_ARB_CFG */
2433                                         0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2434                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2435                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2436                                         0x00000005 /* MC_EMEM_ARB_TIMING_RC */
2437                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
2438                                         0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
2439                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2440                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2441                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2442                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2443                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2444                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2445                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2446                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2447                                         0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
2448                                         0x73840a06 /* MC_EMEM_ARB_MISC0 */
2449                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2450                                 >;
2451                         };
2452
2453                         timing-400000000 {
2454                                 clock-frequency = <400000000>;
2455                                 nvidia,emem-configuration = <
2456                                         0x0000000c /* MC_EMEM_ARB_CFG */
2457                                         0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2458                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2459                                         0x00000002 /* MC_EMEM_ARB_TIMING_RP */
2460                                         0x00000009 /* MC_EMEM_ARB_TIMING_RC */
2461                                         0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
2462                                         0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
2463                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2464                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2465                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2466                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2467                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
2468                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
2469                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2470                                         0x06030202 /* MC_EMEM_ARB_DA_TURNS */
2471                                         0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
2472                                         0x7086120a /* MC_EMEM_ARB_MISC0 */
2473                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2474                                 >;
2475                         };
2476
2477                         timing-800000000 {
2478                                 clock-frequency = <800000000>;
2479                                 nvidia,emem-configuration = <
2480                                         0x00000018 /* MC_EMEM_ARB_CFG */
2481                                         0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2482                                         0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
2483                                         0x00000005 /* MC_EMEM_ARB_TIMING_RP */
2484                                         0x00000013 /* MC_EMEM_ARB_TIMING_RC */
2485                                         0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
2486                                         0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
2487                                         0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
2488                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2489                                         0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
2490                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2491                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
2492                                         0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
2493                                         0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
2494                                         0x08040202 /* MC_EMEM_ARB_DA_TURNS */
2495                                         0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
2496                                         0x712c2414 /* MC_EMEM_ARB_MISC0 */
2497                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2498                                 >;
2499                         };
2500                 };
2501
2502                 emc-timings-2 {
2503                         nvidia,ram-code = <2>; /* Hynix A RAM */
2504
2505                         timing-25500000 {
2506                                 clock-frequency = <25500000>;
2507                                 nvidia,emem-configuration = <
2508                                         0x00030003 /* MC_EMEM_ARB_CFG */
2509                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2510                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2511                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2512                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
2513                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2514                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
2515                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2516                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2517                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2518                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2519                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2520                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2521                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2522                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2523                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
2524                                         0x75e30303 /* MC_EMEM_ARB_MISC0 */
2525                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2526                                 >;
2527                         };
2528
2529                         timing-51000000 {
2530                                 clock-frequency = <51000000>;
2531                                 nvidia,emem-configuration = <
2532                                         0x00010003 /* MC_EMEM_ARB_CFG */
2533                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2534                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2535                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2536                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
2537                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2538                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
2539                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2540                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2541                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2542                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2543                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2544                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2545                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2546                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2547                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
2548                                         0x74e30303 /* MC_EMEM_ARB_MISC0 */
2549                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2550                                 >;
2551                         };
2552
2553                         timing-102000000 {
2554                                 clock-frequency = <102000000>;
2555                                 nvidia,emem-configuration = <
2556                                         0x00000003 /* MC_EMEM_ARB_CFG */
2557                                         0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2558                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2559                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2560                                         0x00000003 /* MC_EMEM_ARB_TIMING_RC */
2561                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
2562                                         0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
2563                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2564                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2565                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2566                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2567                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2568                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2569                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2570                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2571                                         0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
2572                                         0x74430504 /* MC_EMEM_ARB_MISC0 */
2573                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2574                                 >;
2575                         };
2576
2577                         timing-204000000 {
2578                                 clock-frequency = <204000000>;
2579                                 nvidia,emem-configuration = <
2580                                         0x00000006 /* MC_EMEM_ARB_CFG */
2581                                         0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2582                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2583                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
2584                                         0x00000005 /* MC_EMEM_ARB_TIMING_RC */
2585                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
2586                                         0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
2587                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2588                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2589                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2590                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2591                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
2592                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
2593                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2594                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
2595                                         0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
2596                                         0x74040a06 /* MC_EMEM_ARB_MISC0 */
2597                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2598                                 >;
2599                         };
2600
2601                         timing-400000000 {
2602                                 clock-frequency = <400000000>;
2603                                 nvidia,emem-configuration = <
2604                                         0x0000000c /* MC_EMEM_ARB_CFG */
2605                                         0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2606                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
2607                                         0x00000002 /* MC_EMEM_ARB_TIMING_RP */
2608                                         0x00000009 /* MC_EMEM_ARB_TIMING_RC */
2609                                         0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
2610                                         0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
2611                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
2612                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2613                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
2614                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2615                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
2616                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
2617                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
2618                                         0x06030202 /* MC_EMEM_ARB_DA_TURNS */
2619                                         0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
2620                                         0x7086120a /* MC_EMEM_ARB_MISC0 */
2621                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2622                                 >;
2623                         };
2624
2625                         timing-800000000 {
2626                                 clock-frequency = <800000000>;
2627                                 nvidia,emem-configuration = <
2628                                         0x00000018 /* MC_EMEM_ARB_CFG */
2629                                         0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
2630                                         0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
2631                                         0x00000005 /* MC_EMEM_ARB_TIMING_RP */
2632                                         0x00000013 /* MC_EMEM_ARB_TIMING_RC */
2633                                         0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
2634                                         0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
2635                                         0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
2636                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
2637                                         0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
2638                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
2639                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
2640                                         0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
2641                                         0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
2642                                         0x08040202 /* MC_EMEM_ARB_DA_TURNS */
2643                                         0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
2644                                         0x712c2414 /* MC_EMEM_ARB_MISC0 */
2645                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
2646                                 >;
2647                         };
2648                 };
2649         };
2650
2651         memory-controller@7000f400 {
2652                 emc-timings-0 {
2653                         nvidia,ram-code = <0>;  /* Samsung RAM */
2654
2655                         timing-25500000 {
2656                                 clock-frequency = <25500000>;
2657                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
2658                                 nvidia,emc-mode-1 = <0x80100003>;
2659                                 nvidia,emc-mode-2 = <0x80200008>;
2660                                 nvidia,emc-mode-reset = <0x80001221>;
2661                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
2662                                 nvidia,emc-cfg-periodic-qrst;
2663                                 nvidia,emc-cfg-dyn-self-ref;
2664                                 nvidia,emc-configuration = <
2665                                         0x00000001 /* EMC_RC */
2666                                         0x00000006 /* EMC_RFC */
2667                                         0x00000000 /* EMC_RAS */
2668                                         0x00000000 /* EMC_RP */
2669                                         0x00000002 /* EMC_R2W */
2670                                         0x0000000a /* EMC_W2R */
2671                                         0x00000005 /* EMC_R2P */
2672                                         0x0000000b /* EMC_W2P */
2673                                         0x00000000 /* EMC_RD_RCD */
2674                                         0x00000000 /* EMC_WR_RCD */
2675                                         0x00000003 /* EMC_RRD */
2676                                         0x00000001 /* EMC_REXT */
2677                                         0x00000000 /* EMC_WEXT */
2678                                         0x00000005 /* EMC_WDV */
2679                                         0x00000005 /* EMC_QUSE */
2680                                         0x00000004 /* EMC_QRST */
2681                                         0x0000000a /* EMC_QSAFE */
2682                                         0x0000000b /* EMC_RDV */
2683                                         0x000000c0 /* EMC_REFRESH */
2684                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
2685                                         0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
2686                                         0x00000002 /* EMC_PDEX2WR */
2687                                         0x00000002 /* EMC_PDEX2RD */
2688                                         0x00000001 /* EMC_PCHG2PDEN */
2689                                         0x00000000 /* EMC_ACT2PDEN */
2690                                         0x00000007 /* EMC_AR2PDEN */
2691                                         0x0000000f /* EMC_RW2PDEN */
2692                                         0x00000007 /* EMC_TXSR */
2693                                         0x00000007 /* EMC_TXSRDLL */
2694                                         0x00000004 /* EMC_TCKE */
2695                                         0x00000002 /* EMC_TFAW */
2696                                         0x00000000 /* EMC_TRPAB */
2697                                         0x00000004 /* EMC_TCLKSTABLE */
2698                                         0x00000005 /* EMC_TCLKSTOP */
2699                                         0x000000c7 /* EMC_TREFBW */
2700                                         0x00000006 /* EMC_QUSE_EXTRA */
2701                                         0x00000004 /* EMC_FBIO_CFG6 */
2702                                         0x00000000 /* EMC_ODT_WRITE */
2703                                         0x00000000 /* EMC_ODT_READ */
2704                                         0x00004288 /* EMC_FBIO_CFG5 */
2705                                         0x007800a4 /* EMC_CFG_DIG_DLL */
2706                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2707                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2708                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2709                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2710                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2711                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2712                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2713                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2714                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2715                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2716                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2717                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2718                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2719                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2720                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2721                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2722                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2723                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2724                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2725                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2726                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2727                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2728                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2729                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2730                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2731                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2732                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2733                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2734                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2735                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
2736                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
2737                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
2738                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
2739                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
2740                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
2741                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2742                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
2743                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
2744                                         0x00000802 /* EMC_CTT_TERM_CTRL */
2745                                         0x00000000 /* EMC_ZCAL_INTERVAL */
2746                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
2747                                         0x000c000c /* EMC_MRS_WAIT_CNT */
2748                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2749                                         0x00000000 /* EMC_CTT */
2750                                         0x00000000 /* EMC_CTT_DURATION */
2751                                         0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
2752                                         0xe8000000 /* EMC_FBIO_SPARE */
2753                                         0xff00ff00 /* EMC_CFG_RSV */
2754                                 >;
2755                         };
2756
2757                         timing-51000000 {
2758                                 clock-frequency = <51000000>;
2759                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
2760                                 nvidia,emc-mode-1 = <0x80100003>;
2761                                 nvidia,emc-mode-2 = <0x80200008>;
2762                                 nvidia,emc-mode-reset = <0x80001221>;
2763                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
2764                                 nvidia,emc-cfg-periodic-qrst;
2765                                 nvidia,emc-cfg-dyn-self-ref;
2766                                 nvidia,emc-configuration = <
2767                                         0x00000002 /* EMC_RC */
2768                                         0x0000000d /* EMC_RFC */
2769                                         0x00000001 /* EMC_RAS */
2770                                         0x00000000 /* EMC_RP */
2771                                         0x00000002 /* EMC_R2W */
2772                                         0x0000000a /* EMC_W2R */
2773                                         0x00000005 /* EMC_R2P */
2774                                         0x0000000b /* EMC_W2P */
2775                                         0x00000000 /* EMC_RD_RCD */
2776                                         0x00000000 /* EMC_WR_RCD */
2777                                         0x00000003 /* EMC_RRD */
2778                                         0x00000001 /* EMC_REXT */
2779                                         0x00000000 /* EMC_WEXT */
2780                                         0x00000005 /* EMC_WDV */
2781                                         0x00000005 /* EMC_QUSE */
2782                                         0x00000004 /* EMC_QRST */
2783                                         0x0000000a /* EMC_QSAFE */
2784                                         0x0000000b /* EMC_RDV */
2785                                         0x00000181 /* EMC_REFRESH */
2786                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
2787                                         0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
2788                                         0x00000002 /* EMC_PDEX2WR */
2789                                         0x00000002 /* EMC_PDEX2RD */
2790                                         0x00000001 /* EMC_PCHG2PDEN */
2791                                         0x00000000 /* EMC_ACT2PDEN */
2792                                         0x00000007 /* EMC_AR2PDEN */
2793                                         0x0000000f /* EMC_RW2PDEN */
2794                                         0x0000000e /* EMC_TXSR */
2795                                         0x0000000e /* EMC_TXSRDLL */
2796                                         0x00000004 /* EMC_TCKE */
2797                                         0x00000003 /* EMC_TFAW */
2798                                         0x00000000 /* EMC_TRPAB */
2799                                         0x00000004 /* EMC_TCLKSTABLE */
2800                                         0x00000005 /* EMC_TCLKSTOP */
2801                                         0x0000018e /* EMC_TREFBW */
2802                                         0x00000006 /* EMC_QUSE_EXTRA */
2803                                         0x00000004 /* EMC_FBIO_CFG6 */
2804                                         0x00000000 /* EMC_ODT_WRITE */
2805                                         0x00000000 /* EMC_ODT_READ */
2806                                         0x00004288 /* EMC_FBIO_CFG5 */
2807                                         0x007800a4 /* EMC_CFG_DIG_DLL */
2808                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2809                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2810                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2811                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2812                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2813                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2814                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2815                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2816                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2817                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2818                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2819                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2820                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2821                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2822                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2823                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2824                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2825                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2826                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2827                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2828                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2829                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2830                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2831                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2832                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2833                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2834                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2835                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2836                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2837                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
2838                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
2839                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
2840                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
2841                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
2842                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
2843                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2844                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
2845                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
2846                                         0x00000802 /* EMC_CTT_TERM_CTRL */
2847                                         0x00000000 /* EMC_ZCAL_INTERVAL */
2848                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
2849                                         0x000c000c /* EMC_MRS_WAIT_CNT */
2850                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2851                                         0x00000000 /* EMC_CTT */
2852                                         0x00000000 /* EMC_CTT_DURATION */
2853                                         0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
2854                                         0xe8000000 /* EMC_FBIO_SPARE */
2855                                         0xff00ff00 /* EMC_CFG_RSV */
2856                                 >;
2857                         };
2858
2859                         timing-102000000 {
2860                                 clock-frequency = <102000000>;
2861                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
2862                                 nvidia,emc-mode-1 = <0x80100003>;
2863                                 nvidia,emc-mode-2 = <0x80200008>;
2864                                 nvidia,emc-mode-reset = <0x80001221>;
2865                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
2866                                 nvidia,emc-cfg-periodic-qrst;
2867                                 nvidia,emc-cfg-dyn-self-ref;
2868                                 nvidia,emc-configuration = <
2869                                         0x00000004 /* EMC_RC */
2870                                         0x0000001a /* EMC_RFC */
2871                                         0x00000003 /* EMC_RAS */
2872                                         0x00000001 /* EMC_RP */
2873                                         0x00000002 /* EMC_R2W */
2874                                         0x0000000a /* EMC_W2R */
2875                                         0x00000005 /* EMC_R2P */
2876                                         0x0000000b /* EMC_W2P */
2877                                         0x00000001 /* EMC_RD_RCD */
2878                                         0x00000001 /* EMC_WR_RCD */
2879                                         0x00000003 /* EMC_RRD */
2880                                         0x00000001 /* EMC_REXT */
2881                                         0x00000000 /* EMC_WEXT */
2882                                         0x00000005 /* EMC_WDV */
2883                                         0x00000005 /* EMC_QUSE */
2884                                         0x00000004 /* EMC_QRST */
2885                                         0x0000000a /* EMC_QSAFE */
2886                                         0x0000000b /* EMC_RDV */
2887                                         0x00000303 /* EMC_REFRESH */
2888                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
2889                                         0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
2890                                         0x00000002 /* EMC_PDEX2WR */
2891                                         0x00000002 /* EMC_PDEX2RD */
2892                                         0x00000001 /* EMC_PCHG2PDEN */
2893                                         0x00000000 /* EMC_ACT2PDEN */
2894                                         0x00000007 /* EMC_AR2PDEN */
2895                                         0x0000000f /* EMC_RW2PDEN */
2896                                         0x0000001c /* EMC_TXSR */
2897                                         0x0000001c /* EMC_TXSRDLL */
2898                                         0x00000004 /* EMC_TCKE */
2899                                         0x00000005 /* EMC_TFAW */
2900                                         0x00000000 /* EMC_TRPAB */
2901                                         0x00000004 /* EMC_TCLKSTABLE */
2902                                         0x00000005 /* EMC_TCLKSTOP */
2903                                         0x0000031c /* EMC_TREFBW */
2904                                         0x00000006 /* EMC_QUSE_EXTRA */
2905                                         0x00000004 /* EMC_FBIO_CFG6 */
2906                                         0x00000000 /* EMC_ODT_WRITE */
2907                                         0x00000000 /* EMC_ODT_READ */
2908                                         0x00004288 /* EMC_FBIO_CFG5 */
2909                                         0x007800a4 /* EMC_CFG_DIG_DLL */
2910                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
2911                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
2912                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
2913                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
2914                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
2915                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
2916                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
2917                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
2918                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
2919                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
2920                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
2921                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
2922                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
2923                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
2924                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
2925                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
2926                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
2927                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
2928                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
2929                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
2930                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
2931                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
2932                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
2933                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
2934                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
2935                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
2936                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
2937                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
2938                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
2939                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
2940                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
2941                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
2942                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
2943                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
2944                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
2945                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
2946                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
2947                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
2948                                         0x00000802 /* EMC_CTT_TERM_CTRL */
2949                                         0x00000000 /* EMC_ZCAL_INTERVAL */
2950                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
2951                                         0x000c000c /* EMC_MRS_WAIT_CNT */
2952                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
2953                                         0x00000000 /* EMC_CTT */
2954                                         0x00000000 /* EMC_CTT_DURATION */
2955                                         0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
2956                                         0xe8000000 /* EMC_FBIO_SPARE */
2957                                         0xff00ff00 /* EMC_CFG_RSV */
2958                                 >;
2959                         };
2960
2961                         timing-204000000 {
2962                                 clock-frequency = <204000000>;
2963                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
2964                                 nvidia,emc-mode-1 = <0x80100003>;
2965                                 nvidia,emc-mode-2 = <0x80200008>;
2966                                 nvidia,emc-mode-reset = <0x80001221>;
2967                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
2968                                 nvidia,emc-cfg-periodic-qrst;
2969                                 nvidia,emc-cfg-dyn-self-ref;
2970                                 nvidia,emc-configuration = <
2971                                         0x00000009 /* EMC_RC */
2972                                         0x00000035 /* EMC_RFC */
2973                                         0x00000007 /* EMC_RAS */
2974                                         0x00000002 /* EMC_RP */
2975                                         0x00000002 /* EMC_R2W */
2976                                         0x0000000a /* EMC_W2R */
2977                                         0x00000005 /* EMC_R2P */
2978                                         0x0000000b /* EMC_W2P */
2979                                         0x00000002 /* EMC_RD_RCD */
2980                                         0x00000002 /* EMC_WR_RCD */
2981                                         0x00000003 /* EMC_RRD */
2982                                         0x00000001 /* EMC_REXT */
2983                                         0x00000000 /* EMC_WEXT */
2984                                         0x00000005 /* EMC_WDV */
2985                                         0x00000005 /* EMC_QUSE */
2986                                         0x00000004 /* EMC_QRST */
2987                                         0x0000000a /* EMC_QSAFE */
2988                                         0x0000000b /* EMC_RDV */
2989                                         0x00000607 /* EMC_REFRESH */
2990                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
2991                                         0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
2992                                         0x00000002 /* EMC_PDEX2WR */
2993                                         0x00000002 /* EMC_PDEX2RD */
2994                                         0x00000001 /* EMC_PCHG2PDEN */
2995                                         0x00000000 /* EMC_ACT2PDEN */
2996                                         0x00000007 /* EMC_AR2PDEN */
2997                                         0x0000000f /* EMC_RW2PDEN */
2998                                         0x00000038 /* EMC_TXSR */
2999                                         0x00000038 /* EMC_TXSRDLL */
3000                                         0x00000004 /* EMC_TCKE */
3001                                         0x00000009 /* EMC_TFAW */
3002                                         0x00000000 /* EMC_TRPAB */
3003                                         0x00000004 /* EMC_TCLKSTABLE */
3004                                         0x00000005 /* EMC_TCLKSTOP */
3005                                         0x00000638 /* EMC_TREFBW */
3006                                         0x00000006 /* EMC_QUSE_EXTRA */
3007                                         0x00000006 /* EMC_FBIO_CFG6 */
3008                                         0x00000000 /* EMC_ODT_WRITE */
3009                                         0x00000000 /* EMC_ODT_READ */
3010                                         0x00004288 /* EMC_FBIO_CFG5 */
3011                                         0x004400a4 /* EMC_CFG_DIG_DLL */
3012                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3013                                         0x00080000 /* EMC_DLL_XFORM_DQS0 */
3014                                         0x00080000 /* EMC_DLL_XFORM_DQS1 */
3015                                         0x00080000 /* EMC_DLL_XFORM_DQS2 */
3016                                         0x00080000 /* EMC_DLL_XFORM_DQS3 */
3017                                         0x00080000 /* EMC_DLL_XFORM_DQS4 */
3018                                         0x00080000 /* EMC_DLL_XFORM_DQS5 */
3019                                         0x00080000 /* EMC_DLL_XFORM_DQS6 */
3020                                         0x00080000 /* EMC_DLL_XFORM_DQS7 */
3021                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
3022                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
3023                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
3024                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
3025                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
3026                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
3027                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
3028                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
3029                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3030                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3031                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3032                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3033                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3034                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3035                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3036                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3037                                         0x00080000 /* EMC_DLL_XFORM_DQ0 */
3038                                         0x00080000 /* EMC_DLL_XFORM_DQ1 */
3039                                         0x00080000 /* EMC_DLL_XFORM_DQ2 */
3040                                         0x00080000 /* EMC_DLL_XFORM_DQ3 */
3041                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3042                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
3043                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
3044                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3045                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
3046                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
3047                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
3048                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
3049                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
3050                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3051                                         0x00020000 /* EMC_ZCAL_INTERVAL */
3052                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
3053                                         0x000c000c /* EMC_MRS_WAIT_CNT */
3054                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3055                                         0x00000000 /* EMC_CTT */
3056                                         0x00000000 /* EMC_CTT_DURATION */
3057                                         0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
3058                                         0xe8000000 /* EMC_FBIO_SPARE */
3059                                         0xff00ff00 /* EMC_CFG_RSV */
3060                                 >;
3061                         };
3062
3063                         timing-400000000 {
3064                                 clock-frequency = <400000000>;
3065                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3066                                 nvidia,emc-mode-1 = <0x80100002>;
3067                                 nvidia,emc-mode-2 = <0x80200000>;
3068                                 nvidia,emc-mode-reset = <0x80000521>;
3069                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3070                                 nvidia,emc-configuration = <
3071                                         0x00000012 /* EMC_RC */
3072                                         0x00000066 /* EMC_RFC */
3073                                         0x0000000c /* EMC_RAS */
3074                                         0x00000004 /* EMC_RP */
3075                                         0x00000003 /* EMC_R2W */
3076                                         0x00000008 /* EMC_W2R */
3077                                         0x00000002 /* EMC_R2P */
3078                                         0x0000000a /* EMC_W2P */
3079                                         0x00000004 /* EMC_RD_RCD */
3080                                         0x00000004 /* EMC_WR_RCD */
3081                                         0x00000002 /* EMC_RRD */
3082                                         0x00000001 /* EMC_REXT */
3083                                         0x00000000 /* EMC_WEXT */
3084                                         0x00000004 /* EMC_WDV */
3085                                         0x00000006 /* EMC_QUSE */
3086                                         0x00000004 /* EMC_QRST */
3087                                         0x0000000a /* EMC_QSAFE */
3088                                         0x0000000c /* EMC_RDV */
3089                                         0x00000bf0 /* EMC_REFRESH */
3090                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3091                                         0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
3092                                         0x00000001 /* EMC_PDEX2WR */
3093                                         0x00000008 /* EMC_PDEX2RD */
3094                                         0x00000001 /* EMC_PCHG2PDEN */
3095                                         0x00000000 /* EMC_ACT2PDEN */
3096                                         0x00000008 /* EMC_AR2PDEN */
3097                                         0x0000000f /* EMC_RW2PDEN */
3098                                         0x0000006c /* EMC_TXSR */
3099                                         0x00000200 /* EMC_TXSRDLL */
3100                                         0x00000004 /* EMC_TCKE */
3101                                         0x00000010 /* EMC_TFAW */
3102                                         0x00000000 /* EMC_TRPAB */
3103                                         0x00000004 /* EMC_TCLKSTABLE */
3104                                         0x00000005 /* EMC_TCLKSTOP */
3105                                         0x00000c30 /* EMC_TREFBW */
3106                                         0x00000000 /* EMC_QUSE_EXTRA */
3107                                         0x00000004 /* EMC_FBIO_CFG6 */
3108                                         0x00000000 /* EMC_ODT_WRITE */
3109                                         0x00000000 /* EMC_ODT_READ */
3110                                         0x00007088 /* EMC_FBIO_CFG5 */
3111                                         0x001d0084 /* EMC_CFG_DIG_DLL */
3112                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3113                                         0x0003c000 /* EMC_DLL_XFORM_DQS0 */
3114                                         0x0003c000 /* EMC_DLL_XFORM_DQS1 */
3115                                         0x0003c000 /* EMC_DLL_XFORM_DQS2 */
3116                                         0x0003c000 /* EMC_DLL_XFORM_DQS3 */
3117                                         0x0003c000 /* EMC_DLL_XFORM_DQS4 */
3118                                         0x0003c000 /* EMC_DLL_XFORM_DQS5 */
3119                                         0x0003c000 /* EMC_DLL_XFORM_DQS6 */
3120                                         0x0003c000 /* EMC_DLL_XFORM_DQS7 */
3121                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
3122                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
3123                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
3124                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
3125                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
3126                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
3127                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
3128                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
3129                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3130                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3131                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3132                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3133                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3134                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3135                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3136                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3137                                         0x00048000 /* EMC_DLL_XFORM_DQ0 */
3138                                         0x00048000 /* EMC_DLL_XFORM_DQ1 */
3139                                         0x00048000 /* EMC_DLL_XFORM_DQ2 */
3140                                         0x00048000 /* EMC_DLL_XFORM_DQ3 */
3141                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3142                                         0x0800013d /* EMC_XM2DQSPADCTRL2 */
3143                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
3144                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3145                                         0x01f1f508 /* EMC_XM2COMPPADCTRL */
3146                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
3147                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
3148                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
3149                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
3150                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3151                                         0x00020000 /* EMC_ZCAL_INTERVAL */
3152                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
3153                                         0x0158000c /* EMC_MRS_WAIT_CNT */
3154                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3155                                         0x00000000 /* EMC_CTT */
3156                                         0x00000000 /* EMC_CTT_DURATION */
3157                                         0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
3158                                         0xe8000000 /* EMC_FBIO_SPARE */
3159                                         0xff00ff89 /* EMC_CFG_RSV */
3160                                 >;
3161                         };
3162
3163                         timing-800000000 {
3164                                 clock-frequency = <800000000>;
3165                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3166                                 nvidia,emc-mode-1 = <0x80100002>;
3167                                 nvidia,emc-mode-2 = <0x80200018>;
3168                                 nvidia,emc-mode-reset = <0x80000d71>;
3169                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3170                                 nvidia,emc-cfg-periodic-qrst;
3171                                 nvidia,emc-configuration = <
3172                                         0x00000025 /* EMC_RC */
3173                                         0x000000ce /* EMC_RFC */
3174                                         0x0000001a /* EMC_RAS */
3175                                         0x00000009 /* EMC_RP */
3176                                         0x00000005 /* EMC_R2W */
3177                                         0x0000000d /* EMC_W2R */
3178                                         0x00000004 /* EMC_R2P */
3179                                         0x00000013 /* EMC_W2P */
3180                                         0x00000009 /* EMC_RD_RCD */
3181                                         0x00000009 /* EMC_WR_RCD */
3182                                         0x00000004 /* EMC_RRD */
3183                                         0x00000001 /* EMC_REXT */
3184                                         0x00000000 /* EMC_WEXT */
3185                                         0x00000007 /* EMC_WDV */
3186                                         0x0000000a /* EMC_QUSE */
3187                                         0x00000009 /* EMC_QRST */
3188                                         0x0000000b /* EMC_QSAFE */
3189                                         0x00000011 /* EMC_RDV */
3190                                         0x00001820 /* EMC_REFRESH */
3191                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3192                                         0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
3193                                         0x00000003 /* EMC_PDEX2WR */
3194                                         0x00000012 /* EMC_PDEX2RD */
3195                                         0x00000001 /* EMC_PCHG2PDEN */
3196                                         0x00000000 /* EMC_ACT2PDEN */
3197                                         0x0000000f /* EMC_AR2PDEN */
3198                                         0x00000018 /* EMC_RW2PDEN */
3199                                         0x000000d8 /* EMC_TXSR */
3200                                         0x00000200 /* EMC_TXSRDLL */
3201                                         0x00000005 /* EMC_TCKE */
3202                                         0x00000020 /* EMC_TFAW */
3203                                         0x00000000 /* EMC_TRPAB */
3204                                         0x00000007 /* EMC_TCLKSTABLE */
3205                                         0x00000008 /* EMC_TCLKSTOP */
3206                                         0x00001860 /* EMC_TREFBW */
3207                                         0x0000000b /* EMC_QUSE_EXTRA */
3208                                         0x00000006 /* EMC_FBIO_CFG6 */
3209                                         0x00000000 /* EMC_ODT_WRITE */
3210                                         0x00000000 /* EMC_ODT_READ */
3211                                         0x00005088 /* EMC_FBIO_CFG5 */
3212                                         0xf0070191 /* EMC_CFG_DIG_DLL */
3213                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3214                                         0x0000800a /* EMC_DLL_XFORM_DQS0 */
3215                                         0x0000000a /* EMC_DLL_XFORM_DQS1 */
3216                                         0x0000000a /* EMC_DLL_XFORM_DQS2 */
3217                                         0x0000000a /* EMC_DLL_XFORM_DQS3 */
3218                                         0x0000000a /* EMC_DLL_XFORM_DQS4 */
3219                                         0x0000000a /* EMC_DLL_XFORM_DQS5 */
3220                                         0x0000000a /* EMC_DLL_XFORM_DQS6 */
3221                                         0x0000000a /* EMC_DLL_XFORM_DQS7 */
3222                                         0x00018000 /* EMC_DLL_XFORM_QUSE0 */
3223                                         0x00018000 /* EMC_DLL_XFORM_QUSE1 */
3224                                         0x00018000 /* EMC_DLL_XFORM_QUSE2 */
3225                                         0x00018000 /* EMC_DLL_XFORM_QUSE3 */
3226                                         0x00018000 /* EMC_DLL_XFORM_QUSE4 */
3227                                         0x00018000 /* EMC_DLL_XFORM_QUSE5 */
3228                                         0x00018000 /* EMC_DLL_XFORM_QUSE6 */
3229                                         0x00018000 /* EMC_DLL_XFORM_QUSE7 */
3230                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3231                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3232                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3233                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3234                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3235                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3236                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3237                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3238                                         0x0000000a /* EMC_DLL_XFORM_DQ0 */
3239                                         0x0000000a /* EMC_DLL_XFORM_DQ1 */
3240                                         0x0000000a /* EMC_DLL_XFORM_DQ2 */
3241                                         0x0000000a /* EMC_DLL_XFORM_DQ3 */
3242                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3243                                         0x0600013d /* EMC_XM2DQSPADCTRL2 */
3244                                         0x22220000 /* EMC_XM2DQPADCTRL2 */
3245                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3246                                         0x01f1f501 /* EMC_XM2COMPPADCTRL */
3247                                         0x07077404 /* EMC_XM2VTTGENPADCTRL */
3248                                         0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
3249                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
3250                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
3251                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3252                                         0x00020000 /* EMC_ZCAL_INTERVAL */
3253                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
3254                                         0x00f0000c /* EMC_MRS_WAIT_CNT */
3255                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3256                                         0x00000000 /* EMC_CTT */
3257                                         0x00000000 /* EMC_CTT_DURATION */
3258                                         0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
3259                                         0xe8000000 /* EMC_FBIO_SPARE */
3260                                         0xff00ff49 /* EMC_CFG_RSV */
3261                                 >;
3262                         };
3263                 };
3264
3265                 emc-timings-1 {
3266                         nvidia,ram-code = <1>;  /* Hynix M RAM */
3267
3268                         timing-25500000 {
3269                                 clock-frequency = <25500000>;
3270                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3271                                 nvidia,emc-mode-1 = <0x80100003>;
3272                                 nvidia,emc-mode-2 = <0x80200008>;
3273                                 nvidia,emc-mode-reset = <0x80001221>;
3274                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3275                                 nvidia,emc-cfg-periodic-qrst;
3276                                 nvidia,emc-cfg-dyn-self-ref;
3277                                 nvidia,emc-configuration = <
3278                                         0x00000001 /* EMC_RC */
3279                                         0x00000006 /* EMC_RFC */
3280                                         0x00000000 /* EMC_RAS */
3281                                         0x00000000 /* EMC_RP */
3282                                         0x00000002 /* EMC_R2W */
3283                                         0x0000000a /* EMC_W2R */
3284                                         0x00000005 /* EMC_R2P */
3285                                         0x0000000b /* EMC_W2P */
3286                                         0x00000000 /* EMC_RD_RCD */
3287                                         0x00000000 /* EMC_WR_RCD */
3288                                         0x00000003 /* EMC_RRD */
3289                                         0x00000001 /* EMC_REXT */
3290                                         0x00000000 /* EMC_WEXT */
3291                                         0x00000005 /* EMC_WDV */
3292                                         0x00000005 /* EMC_QUSE */
3293                                         0x00000004 /* EMC_QRST */
3294                                         0x0000000a /* EMC_QSAFE */
3295                                         0x0000000b /* EMC_RDV */
3296                                         0x000000c0 /* EMC_REFRESH */
3297                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3298                                         0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
3299                                         0x00000002 /* EMC_PDEX2WR */
3300                                         0x00000002 /* EMC_PDEX2RD */
3301                                         0x00000001 /* EMC_PCHG2PDEN */
3302                                         0x00000000 /* EMC_ACT2PDEN */
3303                                         0x00000007 /* EMC_AR2PDEN */
3304                                         0x0000000f /* EMC_RW2PDEN */
3305                                         0x00000007 /* EMC_TXSR */
3306                                         0x00000007 /* EMC_TXSRDLL */
3307                                         0x00000004 /* EMC_TCKE */
3308                                         0x00000002 /* EMC_TFAW */
3309                                         0x00000000 /* EMC_TRPAB */
3310                                         0x00000004 /* EMC_TCLKSTABLE */
3311                                         0x00000005 /* EMC_TCLKSTOP */
3312                                         0x000000c7 /* EMC_TREFBW */
3313                                         0x00000006 /* EMC_QUSE_EXTRA */
3314                                         0x00000004 /* EMC_FBIO_CFG6 */
3315                                         0x00000000 /* EMC_ODT_WRITE */
3316                                         0x00000000 /* EMC_ODT_READ */
3317                                         0x00004288 /* EMC_FBIO_CFG5 */
3318                                         0x007800a4 /* EMC_CFG_DIG_DLL */
3319                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3320                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
3321                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
3322                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
3323                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
3324                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
3325                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
3326                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
3327                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
3328                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
3329                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
3330                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
3331                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
3332                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
3333                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
3334                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
3335                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
3336                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3337                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3338                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3339                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3340                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3341                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3342                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3343                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3344                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
3345                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
3346                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
3347                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
3348                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3349                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
3350                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
3351                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3352                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
3353                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
3354                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
3355                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
3356                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
3357                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3358                                         0x00000000 /* EMC_ZCAL_INTERVAL */
3359                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
3360                                         0x000c000c /* EMC_MRS_WAIT_CNT */
3361                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3362                                         0x00000000 /* EMC_CTT */
3363                                         0x00000000 /* EMC_CTT_DURATION */
3364                                         0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
3365                                         0xe8000000 /* EMC_FBIO_SPARE */
3366                                         0xff00ff00 /* EMC_CFG_RSV */
3367                                 >;
3368                         };
3369
3370                         timing-51000000 {
3371                                 clock-frequency = <51000000>;
3372                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3373                                 nvidia,emc-mode-1 = <0x80100003>;
3374                                 nvidia,emc-mode-2 = <0x80200008>;
3375                                 nvidia,emc-mode-reset = <0x80001221>;
3376                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3377                                 nvidia,emc-cfg-periodic-qrst;
3378                                 nvidia,emc-cfg-dyn-self-ref;
3379                                 nvidia,emc-configuration = <
3380                                         0x00000002 /* EMC_RC */
3381                                         0x0000000d /* EMC_RFC */
3382                                         0x00000001 /* EMC_RAS */
3383                                         0x00000000 /* EMC_RP */
3384                                         0x00000002 /* EMC_R2W */
3385                                         0x0000000a /* EMC_W2R */
3386                                         0x00000005 /* EMC_R2P */
3387                                         0x0000000b /* EMC_W2P */
3388                                         0x00000000 /* EMC_RD_RCD */
3389                                         0x00000000 /* EMC_WR_RCD */
3390                                         0x00000003 /* EMC_RRD */
3391                                         0x00000001 /* EMC_REXT */
3392                                         0x00000000 /* EMC_WEXT */
3393                                         0x00000005 /* EMC_WDV */
3394                                         0x00000005 /* EMC_QUSE */
3395                                         0x00000004 /* EMC_QRST */
3396                                         0x0000000a /* EMC_QSAFE */
3397                                         0x0000000b /* EMC_RDV */
3398                                         0x00000181 /* EMC_REFRESH */
3399                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3400                                         0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
3401                                         0x00000002 /* EMC_PDEX2WR */
3402                                         0x00000002 /* EMC_PDEX2RD */
3403                                         0x00000001 /* EMC_PCHG2PDEN */
3404                                         0x00000000 /* EMC_ACT2PDEN */
3405                                         0x00000007 /* EMC_AR2PDEN */
3406                                         0x0000000f /* EMC_RW2PDEN */
3407                                         0x0000000e /* EMC_TXSR */
3408                                         0x0000000e /* EMC_TXSRDLL */
3409                                         0x00000004 /* EMC_TCKE */
3410                                         0x00000003 /* EMC_TFAW */
3411                                         0x00000000 /* EMC_TRPAB */
3412                                         0x00000004 /* EMC_TCLKSTABLE */
3413                                         0x00000005 /* EMC_TCLKSTOP */
3414                                         0x0000018e /* EMC_TREFBW */
3415                                         0x00000006 /* EMC_QUSE_EXTRA */
3416                                         0x00000004 /* EMC_FBIO_CFG6 */
3417                                         0x00000000 /* EMC_ODT_WRITE */
3418                                         0x00000000 /* EMC_ODT_READ */
3419                                         0x00004288 /* EMC_FBIO_CFG5 */
3420                                         0x007800a4 /* EMC_CFG_DIG_DLL */
3421                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3422                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
3423                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
3424                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
3425                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
3426                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
3427                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
3428                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
3429                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
3430                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
3431                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
3432                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
3433                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
3434                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
3435                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
3436                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
3437                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
3438                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3439                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3440                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3441                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3442                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3443                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3444                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3445                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3446                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
3447                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
3448                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
3449                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
3450                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3451                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
3452                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
3453                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3454                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
3455                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
3456                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
3457                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
3458                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
3459                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3460                                         0x00000000 /* EMC_ZCAL_INTERVAL */
3461                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
3462                                         0x000c000c /* EMC_MRS_WAIT_CNT */
3463                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3464                                         0x00000000 /* EMC_CTT */
3465                                         0x00000000 /* EMC_CTT_DURATION */
3466                                         0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
3467                                         0xe8000000 /* EMC_FBIO_SPARE */
3468                                         0xff00ff00 /* EMC_CFG_RSV */
3469                                 >;
3470                         };
3471
3472                         timing-102000000 {
3473                                 clock-frequency = <102000000>;
3474                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3475                                 nvidia,emc-mode-1 = <0x80100003>;
3476                                 nvidia,emc-mode-2 = <0x80200008>;
3477                                 nvidia,emc-mode-reset = <0x80001221>;
3478                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3479                                 nvidia,emc-cfg-periodic-qrst;
3480                                 nvidia,emc-cfg-dyn-self-ref;
3481                                 nvidia,emc-configuration = <
3482                                         0x00000004 /* EMC_RC */
3483                                         0x0000001a /* EMC_RFC */
3484                                         0x00000003 /* EMC_RAS */
3485                                         0x00000001 /* EMC_RP */
3486                                         0x00000002 /* EMC_R2W */
3487                                         0x0000000a /* EMC_W2R */
3488                                         0x00000005 /* EMC_R2P */
3489                                         0x0000000b /* EMC_W2P */
3490                                         0x00000001 /* EMC_RD_RCD */
3491                                         0x00000001 /* EMC_WR_RCD */
3492                                         0x00000003 /* EMC_RRD */
3493                                         0x00000001 /* EMC_REXT */
3494                                         0x00000000 /* EMC_WEXT */
3495                                         0x00000005 /* EMC_WDV */
3496                                         0x00000005 /* EMC_QUSE */
3497                                         0x00000004 /* EMC_QRST */
3498                                         0x0000000a /* EMC_QSAFE */
3499                                         0x0000000b /* EMC_RDV */
3500                                         0x00000303 /* EMC_REFRESH */
3501                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3502                                         0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
3503                                         0x00000002 /* EMC_PDEX2WR */
3504                                         0x00000002 /* EMC_PDEX2RD */
3505                                         0x00000001 /* EMC_PCHG2PDEN */
3506                                         0x00000000 /* EMC_ACT2PDEN */
3507                                         0x00000007 /* EMC_AR2PDEN */
3508                                         0x0000000f /* EMC_RW2PDEN */
3509                                         0x0000001c /* EMC_TXSR */
3510                                         0x0000001c /* EMC_TXSRDLL */
3511                                         0x00000004 /* EMC_TCKE */
3512                                         0x00000005 /* EMC_TFAW */
3513                                         0x00000000 /* EMC_TRPAB */
3514                                         0x00000004 /* EMC_TCLKSTABLE */
3515                                         0x00000005 /* EMC_TCLKSTOP */
3516                                         0x0000031c /* EMC_TREFBW */
3517                                         0x00000006 /* EMC_QUSE_EXTRA */
3518                                         0x00000004 /* EMC_FBIO_CFG6 */
3519                                         0x00000000 /* EMC_ODT_WRITE */
3520                                         0x00000000 /* EMC_ODT_READ */
3521                                         0x00004288 /* EMC_FBIO_CFG5 */
3522                                         0x007800a4 /* EMC_CFG_DIG_DLL */
3523                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3524                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
3525                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
3526                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
3527                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
3528                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
3529                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
3530                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
3531                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
3532                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
3533                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
3534                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
3535                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
3536                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
3537                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
3538                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
3539                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
3540                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3541                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3542                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3543                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3544                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3545                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3546                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3547                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3548                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
3549                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
3550                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
3551                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
3552                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3553                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
3554                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
3555                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3556                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
3557                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
3558                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
3559                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
3560                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
3561                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3562                                         0x00000000 /* EMC_ZCAL_INTERVAL */
3563                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
3564                                         0x000c000c /* EMC_MRS_WAIT_CNT */
3565                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3566                                         0x00000000 /* EMC_CTT */
3567                                         0x00000000 /* EMC_CTT_DURATION */
3568                                         0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
3569                                         0xe8000000 /* EMC_FBIO_SPARE */
3570                                         0xff00ff00 /* EMC_CFG_RSV */
3571                                 >;
3572                         };
3573
3574                         timing-204000000 {
3575                                 clock-frequency = <204000000>;
3576                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3577                                 nvidia,emc-mode-1 = <0x80100003>;
3578                                 nvidia,emc-mode-2 = <0x80200008>;
3579                                 nvidia,emc-mode-reset = <0x80001221>;
3580                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3581                                 nvidia,emc-cfg-periodic-qrst;
3582                                 nvidia,emc-cfg-dyn-self-ref;
3583                                 nvidia,emc-configuration = <
3584                                         0x00000009 /* EMC_RC */
3585                                         0x00000035 /* EMC_RFC */
3586                                         0x00000007 /* EMC_RAS */
3587                                         0x00000002 /* EMC_RP */
3588                                         0x00000002 /* EMC_R2W */
3589                                         0x0000000a /* EMC_W2R */
3590                                         0x00000005 /* EMC_R2P */
3591                                         0x0000000b /* EMC_W2P */
3592                                         0x00000002 /* EMC_RD_RCD */
3593                                         0x00000002 /* EMC_WR_RCD */
3594                                         0x00000003 /* EMC_RRD */
3595                                         0x00000001 /* EMC_REXT */
3596                                         0x00000000 /* EMC_WEXT */
3597                                         0x00000005 /* EMC_WDV */
3598                                         0x00000005 /* EMC_QUSE */
3599                                         0x00000004 /* EMC_QRST */
3600                                         0x0000000a /* EMC_QSAFE */
3601                                         0x0000000b /* EMC_RDV */
3602                                         0x00000607 /* EMC_REFRESH */
3603                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3604                                         0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
3605                                         0x00000002 /* EMC_PDEX2WR */
3606                                         0x00000002 /* EMC_PDEX2RD */
3607                                         0x00000001 /* EMC_PCHG2PDEN */
3608                                         0x00000000 /* EMC_ACT2PDEN */
3609                                         0x00000007 /* EMC_AR2PDEN */
3610                                         0x0000000f /* EMC_RW2PDEN */
3611                                         0x00000038 /* EMC_TXSR */
3612                                         0x00000038 /* EMC_TXSRDLL */
3613                                         0x00000004 /* EMC_TCKE */
3614                                         0x00000009 /* EMC_TFAW */
3615                                         0x00000000 /* EMC_TRPAB */
3616                                         0x00000004 /* EMC_TCLKSTABLE */
3617                                         0x00000005 /* EMC_TCLKSTOP */
3618                                         0x00000638 /* EMC_TREFBW */
3619                                         0x00000006 /* EMC_QUSE_EXTRA */
3620                                         0x00000006 /* EMC_FBIO_CFG6 */
3621                                         0x00000000 /* EMC_ODT_WRITE */
3622                                         0x00000000 /* EMC_ODT_READ */
3623                                         0x00004288 /* EMC_FBIO_CFG5 */
3624                                         0x004400a4 /* EMC_CFG_DIG_DLL */
3625                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3626                                         0x00080000 /* EMC_DLL_XFORM_DQS0 */
3627                                         0x00080000 /* EMC_DLL_XFORM_DQS1 */
3628                                         0x00080000 /* EMC_DLL_XFORM_DQS2 */
3629                                         0x00080000 /* EMC_DLL_XFORM_DQS3 */
3630                                         0x00080000 /* EMC_DLL_XFORM_DQS4 */
3631                                         0x00080000 /* EMC_DLL_XFORM_DQS5 */
3632                                         0x00080000 /* EMC_DLL_XFORM_DQS6 */
3633                                         0x00080000 /* EMC_DLL_XFORM_DQS7 */
3634                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
3635                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
3636                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
3637                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
3638                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
3639                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
3640                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
3641                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
3642                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3643                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3644                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3645                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3646                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3647                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3648                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3649                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3650                                         0x00080000 /* EMC_DLL_XFORM_DQ0 */
3651                                         0x00080000 /* EMC_DLL_XFORM_DQ1 */
3652                                         0x00080000 /* EMC_DLL_XFORM_DQ2 */
3653                                         0x00080000 /* EMC_DLL_XFORM_DQ3 */
3654                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3655                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
3656                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
3657                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3658                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
3659                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
3660                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
3661                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
3662                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
3663                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3664                                         0x00020000 /* EMC_ZCAL_INTERVAL */
3665                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
3666                                         0x000c000c /* EMC_MRS_WAIT_CNT */
3667                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3668                                         0x00000000 /* EMC_CTT */
3669                                         0x00000000 /* EMC_CTT_DURATION */
3670                                         0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
3671                                         0xe8000000 /* EMC_FBIO_SPARE */
3672                                         0xff00ff00 /* EMC_CFG_RSV */
3673                                 >;
3674                         };
3675
3676                         timing-400000000 {
3677                                 clock-frequency = <400000000>;
3678                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3679                                 nvidia,emc-mode-1 = <0x80100002>;
3680                                 nvidia,emc-mode-2 = <0x80200000>;
3681                                 nvidia,emc-mode-reset = <0x80000521>;
3682                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3683                                 nvidia,emc-configuration = <
3684                                         0x00000012 /* EMC_RC */
3685                                         0x00000066 /* EMC_RFC */
3686                                         0x0000000c /* EMC_RAS */
3687                                         0x00000004 /* EMC_RP */
3688                                         0x00000003 /* EMC_R2W */
3689                                         0x00000008 /* EMC_W2R */
3690                                         0x00000002 /* EMC_R2P */
3691                                         0x0000000a /* EMC_W2P */
3692                                         0x00000004 /* EMC_RD_RCD */
3693                                         0x00000004 /* EMC_WR_RCD */
3694                                         0x00000002 /* EMC_RRD */
3695                                         0x00000001 /* EMC_REXT */
3696                                         0x00000000 /* EMC_WEXT */
3697                                         0x00000004 /* EMC_WDV */
3698                                         0x00000006 /* EMC_QUSE */
3699                                         0x00000004 /* EMC_QRST */
3700                                         0x0000000a /* EMC_QSAFE */
3701                                         0x0000000c /* EMC_RDV */
3702                                         0x00000bf0 /* EMC_REFRESH */
3703                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3704                                         0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
3705                                         0x00000001 /* EMC_PDEX2WR */
3706                                         0x00000008 /* EMC_PDEX2RD */
3707                                         0x00000001 /* EMC_PCHG2PDEN */
3708                                         0x00000000 /* EMC_ACT2PDEN */
3709                                         0x00000008 /* EMC_AR2PDEN */
3710                                         0x0000000f /* EMC_RW2PDEN */
3711                                         0x0000006c /* EMC_TXSR */
3712                                         0x00000200 /* EMC_TXSRDLL */
3713                                         0x00000004 /* EMC_TCKE */
3714                                         0x00000010 /* EMC_TFAW */
3715                                         0x00000000 /* EMC_TRPAB */
3716                                         0x00000004 /* EMC_TCLKSTABLE */
3717                                         0x00000005 /* EMC_TCLKSTOP */
3718                                         0x00000c30 /* EMC_TREFBW */
3719                                         0x00000000 /* EMC_QUSE_EXTRA */
3720                                         0x00000004 /* EMC_FBIO_CFG6 */
3721                                         0x00000000 /* EMC_ODT_WRITE */
3722                                         0x00000000 /* EMC_ODT_READ */
3723                                         0x00007088 /* EMC_FBIO_CFG5 */
3724                                         0x001d0084 /* EMC_CFG_DIG_DLL */
3725                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3726                                         0x0003c000 /* EMC_DLL_XFORM_DQS0 */
3727                                         0x0003c000 /* EMC_DLL_XFORM_DQS1 */
3728                                         0x0003c000 /* EMC_DLL_XFORM_DQS2 */
3729                                         0x0003c000 /* EMC_DLL_XFORM_DQS3 */
3730                                         0x0003c000 /* EMC_DLL_XFORM_DQS4 */
3731                                         0x0003c000 /* EMC_DLL_XFORM_DQS5 */
3732                                         0x0003c000 /* EMC_DLL_XFORM_DQS6 */
3733                                         0x0003c000 /* EMC_DLL_XFORM_DQS7 */
3734                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
3735                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
3736                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
3737                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
3738                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
3739                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
3740                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
3741                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
3742                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3743                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3744                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3745                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3746                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3747                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3748                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3749                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3750                                         0x00048000 /* EMC_DLL_XFORM_DQ0 */
3751                                         0x00048000 /* EMC_DLL_XFORM_DQ1 */
3752                                         0x00048000 /* EMC_DLL_XFORM_DQ2 */
3753                                         0x00048000 /* EMC_DLL_XFORM_DQ3 */
3754                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3755                                         0x0800013d /* EMC_XM2DQSPADCTRL2 */
3756                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
3757                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3758                                         0x01f1f508 /* EMC_XM2COMPPADCTRL */
3759                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
3760                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
3761                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
3762                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
3763                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3764                                         0x00020000 /* EMC_ZCAL_INTERVAL */
3765                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
3766                                         0x0158000c /* EMC_MRS_WAIT_CNT */
3767                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3768                                         0x00000000 /* EMC_CTT */
3769                                         0x00000000 /* EMC_CTT_DURATION */
3770                                         0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
3771                                         0xe8000000 /* EMC_FBIO_SPARE */
3772                                         0xff00ff89 /* EMC_CFG_RSV */
3773                                 >;
3774                         };
3775
3776                         timing-800000000 {
3777                                 clock-frequency = <800000000>;
3778                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3779                                 nvidia,emc-mode-1 = <0x80100002>;
3780                                 nvidia,emc-mode-2 = <0x80200018>;
3781                                 nvidia,emc-mode-reset = <0x80000d71>;
3782                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3783                                 nvidia,emc-cfg-periodic-qrst;
3784                                 nvidia,emc-configuration = <
3785                                         0x00000025 /* EMC_RC */
3786                                         0x000000ce /* EMC_RFC */
3787                                         0x0000001a /* EMC_RAS */
3788                                         0x00000009 /* EMC_RP */
3789                                         0x00000005 /* EMC_R2W */
3790                                         0x0000000d /* EMC_W2R */
3791                                         0x00000004 /* EMC_R2P */
3792                                         0x00000013 /* EMC_W2P */
3793                                         0x00000009 /* EMC_RD_RCD */
3794                                         0x00000009 /* EMC_WR_RCD */
3795                                         0x00000004 /* EMC_RRD */
3796                                         0x00000001 /* EMC_REXT */
3797                                         0x00000000 /* EMC_WEXT */
3798                                         0x00000007 /* EMC_WDV */
3799                                         0x0000000a /* EMC_QUSE */
3800                                         0x00000009 /* EMC_QRST */
3801                                         0x0000000b /* EMC_QSAFE */
3802                                         0x00000011 /* EMC_RDV */
3803                                         0x00001820 /* EMC_REFRESH */
3804                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3805                                         0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
3806                                         0x00000003 /* EMC_PDEX2WR */
3807                                         0x00000012 /* EMC_PDEX2RD */
3808                                         0x00000001 /* EMC_PCHG2PDEN */
3809                                         0x00000000 /* EMC_ACT2PDEN */
3810                                         0x0000000f /* EMC_AR2PDEN */
3811                                         0x00000018 /* EMC_RW2PDEN */
3812                                         0x000000d8 /* EMC_TXSR */
3813                                         0x00000200 /* EMC_TXSRDLL */
3814                                         0x00000005 /* EMC_TCKE */
3815                                         0x00000020 /* EMC_TFAW */
3816                                         0x00000000 /* EMC_TRPAB */
3817                                         0x00000007 /* EMC_TCLKSTABLE */
3818                                         0x00000008 /* EMC_TCLKSTOP */
3819                                         0x00001860 /* EMC_TREFBW */
3820                                         0x0000000b /* EMC_QUSE_EXTRA */
3821                                         0x00000006 /* EMC_FBIO_CFG6 */
3822                                         0x00000000 /* EMC_ODT_WRITE */
3823                                         0x00000000 /* EMC_ODT_READ */
3824                                         0x00005088 /* EMC_FBIO_CFG5 */
3825                                         0xf0070191 /* EMC_CFG_DIG_DLL */
3826                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3827                                         0x0000800a /* EMC_DLL_XFORM_DQS0 */
3828                                         0x0000000a /* EMC_DLL_XFORM_DQS1 */
3829                                         0x0000000a /* EMC_DLL_XFORM_DQS2 */
3830                                         0x0000000a /* EMC_DLL_XFORM_DQS3 */
3831                                         0x0000000a /* EMC_DLL_XFORM_DQS4 */
3832                                         0x0000000a /* EMC_DLL_XFORM_DQS5 */
3833                                         0x0000000a /* EMC_DLL_XFORM_DQS6 */
3834                                         0x0000000a /* EMC_DLL_XFORM_DQS7 */
3835                                         0x00018000 /* EMC_DLL_XFORM_QUSE0 */
3836                                         0x00018000 /* EMC_DLL_XFORM_QUSE1 */
3837                                         0x00018000 /* EMC_DLL_XFORM_QUSE2 */
3838                                         0x00018000 /* EMC_DLL_XFORM_QUSE3 */
3839                                         0x00018000 /* EMC_DLL_XFORM_QUSE4 */
3840                                         0x00018000 /* EMC_DLL_XFORM_QUSE5 */
3841                                         0x00018000 /* EMC_DLL_XFORM_QUSE6 */
3842                                         0x00018000 /* EMC_DLL_XFORM_QUSE7 */
3843                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3844                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3845                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3846                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3847                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3848                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3849                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3850                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3851                                         0x0000000a /* EMC_DLL_XFORM_DQ0 */
3852                                         0x0000000a /* EMC_DLL_XFORM_DQ1 */
3853                                         0x0000000a /* EMC_DLL_XFORM_DQ2 */
3854                                         0x0000000a /* EMC_DLL_XFORM_DQ3 */
3855                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3856                                         0x0600013d /* EMC_XM2DQSPADCTRL2 */
3857                                         0x22220000 /* EMC_XM2DQPADCTRL2 */
3858                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3859                                         0x01f1f501 /* EMC_XM2COMPPADCTRL */
3860                                         0x07077404 /* EMC_XM2VTTGENPADCTRL */
3861                                         0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
3862                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
3863                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
3864                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3865                                         0x00020000 /* EMC_ZCAL_INTERVAL */
3866                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
3867                                         0x00f0000c /* EMC_MRS_WAIT_CNT */
3868                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3869                                         0x00000000 /* EMC_CTT */
3870                                         0x00000000 /* EMC_CTT_DURATION */
3871                                         0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
3872                                         0xe8000000 /* EMC_FBIO_SPARE */
3873                                         0xff00ff49 /* EMC_CFG_RSV */
3874                                 >;
3875                         };
3876                 };
3877
3878                 emc-timings-2 {
3879                         nvidia,ram-code = <2>;  /* Hynix A RAM */
3880
3881                         timing-25500000 {
3882                                 clock-frequency = <25500000>;
3883                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3884                                 nvidia,emc-mode-1 = <0x80100003>;
3885                                 nvidia,emc-mode-2 = <0x80200008>;
3886                                 nvidia,emc-mode-reset = <0x80001221>;
3887                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3888                                 nvidia,emc-cfg-periodic-qrst;
3889                                 nvidia,emc-cfg-dyn-self-ref;
3890                                 nvidia,emc-configuration = <
3891                                         0x00000001 /* EMC_RC */
3892                                         0x00000007 /* EMC_RFC */
3893                                         0x00000000 /* EMC_RAS */
3894                                         0x00000000 /* EMC_RP */
3895                                         0x00000002 /* EMC_R2W */
3896                                         0x0000000a /* EMC_W2R */
3897                                         0x00000005 /* EMC_R2P */
3898                                         0x0000000b /* EMC_W2P */
3899                                         0x00000000 /* EMC_RD_RCD */
3900                                         0x00000000 /* EMC_WR_RCD */
3901                                         0x00000003 /* EMC_RRD */
3902                                         0x00000001 /* EMC_REXT */
3903                                         0x00000000 /* EMC_WEXT */
3904                                         0x00000005 /* EMC_WDV */
3905                                         0x00000005 /* EMC_QUSE */
3906                                         0x00000004 /* EMC_QRST */
3907                                         0x0000000a /* EMC_QSAFE */
3908                                         0x0000000b /* EMC_RDV */
3909                                         0x000000c0 /* EMC_REFRESH */
3910                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
3911                                         0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
3912                                         0x00000002 /* EMC_PDEX2WR */
3913                                         0x00000002 /* EMC_PDEX2RD */
3914                                         0x00000001 /* EMC_PCHG2PDEN */
3915                                         0x00000000 /* EMC_ACT2PDEN */
3916                                         0x00000007 /* EMC_AR2PDEN */
3917                                         0x0000000f /* EMC_RW2PDEN */
3918                                         0x00000008 /* EMC_TXSR */
3919                                         0x00000008 /* EMC_TXSRDLL */
3920                                         0x00000004 /* EMC_TCKE */
3921                                         0x00000002 /* EMC_TFAW */
3922                                         0x00000000 /* EMC_TRPAB */
3923                                         0x00000004 /* EMC_TCLKSTABLE */
3924                                         0x00000005 /* EMC_TCLKSTOP */
3925                                         0x000000c7 /* EMC_TREFBW */
3926                                         0x00000006 /* EMC_QUSE_EXTRA */
3927                                         0x00000004 /* EMC_FBIO_CFG6 */
3928                                         0x00000000 /* EMC_ODT_WRITE */
3929                                         0x00000000 /* EMC_ODT_READ */
3930                                         0x00004288 /* EMC_FBIO_CFG5 */
3931                                         0x007800a4 /* EMC_CFG_DIG_DLL */
3932                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
3933                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
3934                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
3935                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
3936                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
3937                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
3938                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
3939                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
3940                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
3941                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
3942                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
3943                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
3944                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
3945                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
3946                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
3947                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
3948                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
3949                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
3950                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
3951                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
3952                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
3953                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
3954                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
3955                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
3956                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
3957                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
3958                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
3959                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
3960                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
3961                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
3962                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
3963                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
3964                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
3965                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
3966                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
3967                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
3968                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
3969                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
3970                                         0x00000802 /* EMC_CTT_TERM_CTRL */
3971                                         0x00000000 /* EMC_ZCAL_INTERVAL */
3972                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
3973                                         0x000c000c /* EMC_MRS_WAIT_CNT */
3974                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
3975                                         0x00000000 /* EMC_CTT */
3976                                         0x00000000 /* EMC_CTT_DURATION */
3977                                         0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
3978                                         0xe8000000 /* EMC_FBIO_SPARE */
3979                                         0xff00ff00 /* EMC_CFG_RSV */
3980                                 >;
3981                         };
3982
3983                         timing-51000000 {
3984                                 clock-frequency = <51000000>;
3985                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
3986                                 nvidia,emc-mode-1 = <0x80100003>;
3987                                 nvidia,emc-mode-2 = <0x80200008>;
3988                                 nvidia,emc-mode-reset = <0x80001221>;
3989                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
3990                                 nvidia,emc-cfg-periodic-qrst;
3991                                 nvidia,emc-cfg-dyn-self-ref;
3992                                 nvidia,emc-configuration = <
3993                                         0x00000002 /* EMC_RC */
3994                                         0x0000000f /* EMC_RFC */
3995                                         0x00000001 /* EMC_RAS */
3996                                         0x00000000 /* EMC_RP */
3997                                         0x00000002 /* EMC_R2W */
3998                                         0x0000000a /* EMC_W2R */
3999                                         0x00000005 /* EMC_R2P */
4000                                         0x0000000b /* EMC_W2P */
4001                                         0x00000000 /* EMC_RD_RCD */
4002                                         0x00000000 /* EMC_WR_RCD */
4003                                         0x00000003 /* EMC_RRD */
4004                                         0x00000001 /* EMC_REXT */
4005                                         0x00000000 /* EMC_WEXT */
4006                                         0x00000005 /* EMC_WDV */
4007                                         0x00000005 /* EMC_QUSE */
4008                                         0x00000004 /* EMC_QRST */
4009                                         0x0000000a /* EMC_QSAFE */
4010                                         0x0000000b /* EMC_RDV */
4011                                         0x00000181 /* EMC_REFRESH */
4012                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
4013                                         0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
4014                                         0x00000002 /* EMC_PDEX2WR */
4015                                         0x00000002 /* EMC_PDEX2RD */
4016                                         0x00000001 /* EMC_PCHG2PDEN */
4017                                         0x00000000 /* EMC_ACT2PDEN */
4018                                         0x00000007 /* EMC_AR2PDEN */
4019                                         0x0000000f /* EMC_RW2PDEN */
4020                                         0x00000010 /* EMC_TXSR */
4021                                         0x00000010 /* EMC_TXSRDLL */
4022                                         0x00000004 /* EMC_TCKE */
4023                                         0x00000003 /* EMC_TFAW */
4024                                         0x00000000 /* EMC_TRPAB */
4025                                         0x00000004 /* EMC_TCLKSTABLE */
4026                                         0x00000005 /* EMC_TCLKSTOP */
4027                                         0x0000018e /* EMC_TREFBW */
4028                                         0x00000006 /* EMC_QUSE_EXTRA */
4029                                         0x00000004 /* EMC_FBIO_CFG6 */
4030                                         0x00000000 /* EMC_ODT_WRITE */
4031                                         0x00000000 /* EMC_ODT_READ */
4032                                         0x00004288 /* EMC_FBIO_CFG5 */
4033                                         0x007800a4 /* EMC_CFG_DIG_DLL */
4034                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
4035                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
4036                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
4037                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
4038                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
4039                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
4040                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
4041                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
4042                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
4043                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
4044                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
4045                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
4046                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
4047                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
4048                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
4049                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
4050                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
4051                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
4052                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
4053                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
4054                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
4055                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
4056                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
4057                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
4058                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
4059                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
4060                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
4061                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
4062                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
4063                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
4064                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
4065                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
4066                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
4067                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
4068                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
4069                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
4070                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
4071                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
4072                                         0x00000802 /* EMC_CTT_TERM_CTRL */
4073                                         0x00000000 /* EMC_ZCAL_INTERVAL */
4074                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
4075                                         0x000c000c /* EMC_MRS_WAIT_CNT */
4076                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
4077                                         0x00000000 /* EMC_CTT */
4078                                         0x00000000 /* EMC_CTT_DURATION */
4079                                         0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
4080                                         0xe8000000 /* EMC_FBIO_SPARE */
4081                                         0xff00ff00 /* EMC_CFG_RSV */
4082                                 >;
4083                         };
4084
4085                         timing-102000000 {
4086                                 clock-frequency = <102000000>;
4087                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
4088                                 nvidia,emc-mode-1 = <0x80100003>;
4089                                 nvidia,emc-mode-2 = <0x80200008>;
4090                                 nvidia,emc-mode-reset = <0x80001221>;
4091                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
4092                                 nvidia,emc-cfg-periodic-qrst;
4093                                 nvidia,emc-cfg-dyn-self-ref;
4094                                 nvidia,emc-configuration = <
4095                                         0x00000004 /* EMC_RC */
4096                                         0x0000001e /* EMC_RFC */
4097                                         0x00000003 /* EMC_RAS */
4098                                         0x00000001 /* EMC_RP */
4099                                         0x00000002 /* EMC_R2W */
4100                                         0x0000000a /* EMC_W2R */
4101                                         0x00000005 /* EMC_R2P */
4102                                         0x0000000b /* EMC_W2P */
4103                                         0x00000001 /* EMC_RD_RCD */
4104                                         0x00000001 /* EMC_WR_RCD */
4105                                         0x00000003 /* EMC_RRD */
4106                                         0x00000001 /* EMC_REXT */
4107                                         0x00000000 /* EMC_WEXT */
4108                                         0x00000005 /* EMC_WDV */
4109                                         0x00000005 /* EMC_QUSE */
4110                                         0x00000004 /* EMC_QRST */
4111                                         0x0000000a /* EMC_QSAFE */
4112                                         0x0000000b /* EMC_RDV */
4113                                         0x00000303 /* EMC_REFRESH */
4114                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
4115                                         0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
4116                                         0x00000002 /* EMC_PDEX2WR */
4117                                         0x00000002 /* EMC_PDEX2RD */
4118                                         0x00000001 /* EMC_PCHG2PDEN */
4119                                         0x00000000 /* EMC_ACT2PDEN */
4120                                         0x00000007 /* EMC_AR2PDEN */
4121                                         0x0000000f /* EMC_RW2PDEN */
4122                                         0x00000020 /* EMC_TXSR */
4123                                         0x00000020 /* EMC_TXSRDLL */
4124                                         0x00000004 /* EMC_TCKE */
4125                                         0x00000005 /* EMC_TFAW */
4126                                         0x00000000 /* EMC_TRPAB */
4127                                         0x00000004 /* EMC_TCLKSTABLE */
4128                                         0x00000005 /* EMC_TCLKSTOP */
4129                                         0x0000031c /* EMC_TREFBW */
4130                                         0x00000006 /* EMC_QUSE_EXTRA */
4131                                         0x00000004 /* EMC_FBIO_CFG6 */
4132                                         0x00000000 /* EMC_ODT_WRITE */
4133                                         0x00000000 /* EMC_ODT_READ */
4134                                         0x00004288 /* EMC_FBIO_CFG5 */
4135                                         0x007800a4 /* EMC_CFG_DIG_DLL */
4136                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
4137                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
4138                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
4139                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
4140                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
4141                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
4142                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
4143                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
4144                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
4145                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
4146                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
4147                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
4148                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
4149                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
4150                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
4151                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
4152                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
4153                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
4154                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
4155                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
4156                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
4157                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
4158                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
4159                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
4160                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
4161                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
4162                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
4163                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
4164                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
4165                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
4166                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
4167                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
4168                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
4169                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
4170                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
4171                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
4172                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
4173                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
4174                                         0x00000802 /* EMC_CTT_TERM_CTRL */
4175                                         0x00000000 /* EMC_ZCAL_INTERVAL */
4176                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
4177                                         0x000c000c /* EMC_MRS_WAIT_CNT */
4178                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
4179                                         0x00000000 /* EMC_CTT */
4180                                         0x00000000 /* EMC_CTT_DURATION */
4181                                         0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
4182                                         0xe8000000 /* EMC_FBIO_SPARE */
4183                                         0xff00ff00 /* EMC_CFG_RSV */
4184                                 >;
4185                         };
4186
4187                         timing-204000000 {
4188                                 clock-frequency = <204000000>;
4189                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
4190                                 nvidia,emc-mode-1 = <0x80100003>;
4191                                 nvidia,emc-mode-2 = <0x80200008>;
4192                                 nvidia,emc-mode-reset = <0x80001221>;
4193                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
4194                                 nvidia,emc-cfg-periodic-qrst;
4195                                 nvidia,emc-cfg-dyn-self-ref;
4196                                 nvidia,emc-configuration = <
4197                                         0x00000009 /* EMC_RC */
4198                                         0x0000003d /* EMC_RFC */
4199                                         0x00000007 /* EMC_RAS */
4200                                         0x00000002 /* EMC_RP */
4201                                         0x00000002 /* EMC_R2W */
4202                                         0x0000000a /* EMC_W2R */
4203                                         0x00000005 /* EMC_R2P */
4204                                         0x0000000b /* EMC_W2P */
4205                                         0x00000002 /* EMC_RD_RCD */
4206                                         0x00000002 /* EMC_WR_RCD */
4207                                         0x00000003 /* EMC_RRD */
4208                                         0x00000001 /* EMC_REXT */
4209                                         0x00000000 /* EMC_WEXT */
4210                                         0x00000005 /* EMC_WDV */
4211                                         0x00000005 /* EMC_QUSE */
4212                                         0x00000004 /* EMC_QRST */
4213                                         0x0000000a /* EMC_QSAFE */
4214                                         0x0000000b /* EMC_RDV */
4215                                         0x00000607 /* EMC_REFRESH */
4216                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
4217                                         0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
4218                                         0x00000002 /* EMC_PDEX2WR */
4219                                         0x00000002 /* EMC_PDEX2RD */
4220                                         0x00000001 /* EMC_PCHG2PDEN */
4221                                         0x00000000 /* EMC_ACT2PDEN */
4222                                         0x00000007 /* EMC_AR2PDEN */
4223                                         0x0000000f /* EMC_RW2PDEN */
4224                                         0x00000040 /* EMC_TXSR */
4225                                         0x00000040 /* EMC_TXSRDLL */
4226                                         0x00000004 /* EMC_TCKE */
4227                                         0x00000009 /* EMC_TFAW */
4228                                         0x00000000 /* EMC_TRPAB */
4229                                         0x00000004 /* EMC_TCLKSTABLE */
4230                                         0x00000005 /* EMC_TCLKSTOP */
4231                                         0x00000638 /* EMC_TREFBW */
4232                                         0x00000006 /* EMC_QUSE_EXTRA */
4233                                         0x00000006 /* EMC_FBIO_CFG6 */
4234                                         0x00000000 /* EMC_ODT_WRITE */
4235                                         0x00000000 /* EMC_ODT_READ */
4236                                         0x00004288 /* EMC_FBIO_CFG5 */
4237                                         0x004400a4 /* EMC_CFG_DIG_DLL */
4238                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
4239                                         0x00080000 /* EMC_DLL_XFORM_DQS0 */
4240                                         0x00080000 /* EMC_DLL_XFORM_DQS1 */
4241                                         0x00080000 /* EMC_DLL_XFORM_DQS2 */
4242                                         0x00080000 /* EMC_DLL_XFORM_DQS3 */
4243                                         0x00080000 /* EMC_DLL_XFORM_DQS4 */
4244                                         0x00080000 /* EMC_DLL_XFORM_DQS5 */
4245                                         0x00080000 /* EMC_DLL_XFORM_DQS6 */
4246                                         0x00080000 /* EMC_DLL_XFORM_DQS7 */
4247                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
4248                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
4249                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
4250                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
4251                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
4252                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
4253                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
4254                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
4255                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
4256                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
4257                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
4258                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
4259                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
4260                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
4261                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
4262                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
4263                                         0x00080000 /* EMC_DLL_XFORM_DQ0 */
4264                                         0x00080000 /* EMC_DLL_XFORM_DQ1 */
4265                                         0x00080000 /* EMC_DLL_XFORM_DQ2 */
4266                                         0x00080000 /* EMC_DLL_XFORM_DQ3 */
4267                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
4268                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
4269                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
4270                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
4271                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
4272                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
4273                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
4274                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
4275                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
4276                                         0x00000802 /* EMC_CTT_TERM_CTRL */
4277                                         0x00020000 /* EMC_ZCAL_INTERVAL */
4278                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
4279                                         0x000c000c /* EMC_MRS_WAIT_CNT */
4280                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
4281                                         0x00000000 /* EMC_CTT */
4282                                         0x00000000 /* EMC_CTT_DURATION */
4283                                         0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
4284                                         0xe8000000 /* EMC_FBIO_SPARE */
4285                                         0xff00ff00 /* EMC_CFG_RSV */
4286                                 >;
4287                         };
4288
4289                         timing-400000000 {
4290                                 clock-frequency = <400000000>;
4291                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
4292                                 nvidia,emc-mode-1 = <0x80100002>;
4293                                 nvidia,emc-mode-2 = <0x80200000>;
4294                                 nvidia,emc-mode-reset = <0x80000521>;
4295                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
4296                                 nvidia,emc-configuration = <
4297                                         0x00000012 /* EMC_RC */
4298                                         0x00000076 /* EMC_RFC */
4299                                         0x0000000c /* EMC_RAS */
4300                                         0x00000004 /* EMC_RP */
4301                                         0x00000003 /* EMC_R2W */
4302                                         0x00000008 /* EMC_W2R */
4303                                         0x00000002 /* EMC_R2P */
4304                                         0x0000000a /* EMC_W2P */
4305                                         0x00000004 /* EMC_RD_RCD */
4306                                         0x00000004 /* EMC_WR_RCD */
4307                                         0x00000002 /* EMC_RRD */
4308                                         0x00000001 /* EMC_REXT */
4309                                         0x00000000 /* EMC_WEXT */
4310                                         0x00000004 /* EMC_WDV */
4311                                         0x00000006 /* EMC_QUSE */
4312                                         0x00000004 /* EMC_QRST */
4313                                         0x0000000a /* EMC_QSAFE */
4314                                         0x0000000c /* EMC_RDV */
4315                                         0x00000bf0 /* EMC_REFRESH */
4316                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
4317                                         0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
4318                                         0x00000001 /* EMC_PDEX2WR */
4319                                         0x00000008 /* EMC_PDEX2RD */
4320                                         0x00000001 /* EMC_PCHG2PDEN */
4321                                         0x00000000 /* EMC_ACT2PDEN */
4322                                         0x00000008 /* EMC_AR2PDEN */
4323                                         0x0000000f /* EMC_RW2PDEN */
4324                                         0x0000007c /* EMC_TXSR */
4325                                         0x00000200 /* EMC_TXSRDLL */
4326                                         0x00000004 /* EMC_TCKE */
4327                                         0x00000010 /* EMC_TFAW */
4328                                         0x00000000 /* EMC_TRPAB */
4329                                         0x00000004 /* EMC_TCLKSTABLE */
4330                                         0x00000005 /* EMC_TCLKSTOP */
4331                                         0x00000c30 /* EMC_TREFBW */
4332                                         0x00000000 /* EMC_QUSE_EXTRA */
4333                                         0x00000004 /* EMC_FBIO_CFG6 */
4334                                         0x00000000 /* EMC_ODT_WRITE */
4335                                         0x00000000 /* EMC_ODT_READ */
4336                                         0x00007088 /* EMC_FBIO_CFG5 */
4337                                         0x001d0084 /* EMC_CFG_DIG_DLL */
4338                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
4339                                         0x00044000 /* EMC_DLL_XFORM_DQS0 */
4340                                         0x00044000 /* EMC_DLL_XFORM_DQS1 */
4341                                         0x00044000 /* EMC_DLL_XFORM_DQS2 */
4342                                         0x00044000 /* EMC_DLL_XFORM_DQS3 */
4343                                         0x00044000 /* EMC_DLL_XFORM_DQS4 */
4344                                         0x00044000 /* EMC_DLL_XFORM_DQS5 */
4345                                         0x00044000 /* EMC_DLL_XFORM_DQS6 */
4346                                         0x00044000 /* EMC_DLL_XFORM_DQS7 */
4347                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
4348                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
4349                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
4350                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
4351                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
4352                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
4353                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
4354                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
4355                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
4356                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
4357                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
4358                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
4359                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
4360                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
4361                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
4362                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
4363                                         0x00058000 /* EMC_DLL_XFORM_DQ0 */
4364                                         0x00058000 /* EMC_DLL_XFORM_DQ1 */
4365                                         0x00058000 /* EMC_DLL_XFORM_DQ2 */
4366                                         0x00058000 /* EMC_DLL_XFORM_DQ3 */
4367                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
4368                                         0x0800013d /* EMC_XM2DQSPADCTRL2 */
4369                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
4370                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
4371                                         0x01f1f508 /* EMC_XM2COMPPADCTRL */
4372                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
4373                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
4374                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
4375                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
4376                                         0x00000802 /* EMC_CTT_TERM_CTRL */
4377                                         0x00020000 /* EMC_ZCAL_INTERVAL */
4378                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
4379                                         0x0148000c /* EMC_MRS_WAIT_CNT */
4380                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
4381                                         0x00000000 /* EMC_CTT */
4382                                         0x00000000 /* EMC_CTT_DURATION */
4383                                         0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
4384                                         0xe8000000 /* EMC_FBIO_SPARE */
4385                                         0xff00ff89 /* EMC_CFG_RSV */
4386                                 >;
4387                         };
4388
4389                         timing-800000000 {
4390                                 clock-frequency = <800000000>;
4391                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
4392                                 nvidia,emc-mode-1 = <0x80100002>;
4393                                 nvidia,emc-mode-2 = <0x80200018>;
4394                                 nvidia,emc-mode-reset = <0x80000d71>;
4395                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
4396                                 nvidia,emc-cfg-periodic-qrst;
4397                                 nvidia,emc-configuration = <
4398                                         0x00000025 /* EMC_RC */
4399                                         0x000000ee /* EMC_RFC */
4400                                         0x0000001a /* EMC_RAS */
4401                                         0x00000009 /* EMC_RP */
4402                                         0x00000005 /* EMC_R2W */
4403                                         0x0000000d /* EMC_W2R */
4404                                         0x00000004 /* EMC_R2P */
4405                                         0x00000013 /* EMC_W2P */
4406                                         0x00000009 /* EMC_RD_RCD */
4407                                         0x00000009 /* EMC_WR_RCD */
4408                                         0x00000003 /* EMC_RRD */
4409                                         0x00000001 /* EMC_REXT */
4410                                         0x00000000 /* EMC_WEXT */
4411                                         0x00000007 /* EMC_WDV */
4412                                         0x0000000a /* EMC_QUSE */
4413                                         0x00000009 /* EMC_QRST */
4414                                         0x0000000b /* EMC_QSAFE */
4415                                         0x00000011 /* EMC_RDV */
4416                                         0x00001820 /* EMC_REFRESH */
4417                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
4418                                         0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
4419                                         0x00000003 /* EMC_PDEX2WR */
4420                                         0x00000012 /* EMC_PDEX2RD */
4421                                         0x00000001 /* EMC_PCHG2PDEN */
4422                                         0x00000000 /* EMC_ACT2PDEN */
4423                                         0x0000000f /* EMC_AR2PDEN */
4424                                         0x00000018 /* EMC_RW2PDEN */
4425                                         0x000000f8 /* EMC_TXSR */
4426                                         0x00000200 /* EMC_TXSRDLL */
4427                                         0x00000005 /* EMC_TCKE */
4428                                         0x00000020 /* EMC_TFAW */
4429                                         0x00000000 /* EMC_TRPAB */
4430                                         0x00000007 /* EMC_TCLKSTABLE */
4431                                         0x00000008 /* EMC_TCLKSTOP */
4432                                         0x00001860 /* EMC_TREFBW */
4433                                         0x0000000b /* EMC_QUSE_EXTRA */
4434                                         0x00000006 /* EMC_FBIO_CFG6 */
4435                                         0x00000000 /* EMC_ODT_WRITE */
4436                                         0x00000000 /* EMC_ODT_READ */
4437                                         0x00005088 /* EMC_FBIO_CFG5 */
4438                                         0xf0070191 /* EMC_CFG_DIG_DLL */
4439                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
4440                                         0x0000000c /* EMC_DLL_XFORM_DQS0 */
4441                                         0x007fc00a /* EMC_DLL_XFORM_DQS1 */
4442                                         0x00000008 /* EMC_DLL_XFORM_DQS2 */
4443                                         0x0000000a /* EMC_DLL_XFORM_DQS3 */
4444                                         0x0000000a /* EMC_DLL_XFORM_DQS4 */
4445                                         0x0000000a /* EMC_DLL_XFORM_DQS5 */
4446                                         0x0000000a /* EMC_DLL_XFORM_DQS6 */
4447                                         0x0000000a /* EMC_DLL_XFORM_DQS7 */
4448                                         0x00018000 /* EMC_DLL_XFORM_QUSE0 */
4449                                         0x00018000 /* EMC_DLL_XFORM_QUSE1 */
4450                                         0x00018000 /* EMC_DLL_XFORM_QUSE2 */
4451                                         0x00018000 /* EMC_DLL_XFORM_QUSE3 */
4452                                         0x00018000 /* EMC_DLL_XFORM_QUSE4 */
4453                                         0x00018000 /* EMC_DLL_XFORM_QUSE5 */
4454                                         0x00018000 /* EMC_DLL_XFORM_QUSE6 */
4455                                         0x00018000 /* EMC_DLL_XFORM_QUSE7 */
4456                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
4457                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
4458                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
4459                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
4460                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
4461                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
4462                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
4463                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
4464                                         0x0000000a /* EMC_DLL_XFORM_DQ0 */
4465                                         0x0000000c /* EMC_DLL_XFORM_DQ1 */
4466                                         0x0000000a /* EMC_DLL_XFORM_DQ2 */
4467                                         0x0000000a /* EMC_DLL_XFORM_DQ3 */
4468                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
4469                                         0x0600013d /* EMC_XM2DQSPADCTRL2 */
4470                                         0x22220000 /* EMC_XM2DQPADCTRL2 */
4471                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
4472                                         0x01f1f501 /* EMC_XM2COMPPADCTRL */
4473                                         0x07077404 /* EMC_XM2VTTGENPADCTRL */
4474                                         0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
4475                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
4476                                         0x0a000021 /* EMC_XM2DQSPADCTRL3 */
4477                                         0x00000802 /* EMC_CTT_TERM_CTRL */
4478                                         0x00020000 /* EMC_ZCAL_INTERVAL */
4479                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
4480                                         0x00d0000c /* EMC_MRS_WAIT_CNT */
4481                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
4482                                         0x00000000 /* EMC_CTT */
4483                                         0x00000000 /* EMC_CTT_DURATION */
4484                                         0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
4485                                         0xe8000000 /* EMC_FBIO_SPARE */
4486                                         0xff00ff49 /* EMC_CFG_RSV */
4487                                 >;
4488                         };
4489                 };
4490         };
4491
4492         hda@70030000 {
4493                 status = "okay";
4494         };
4495
4496         sdmmc3: mmc@78000400 {
4497                 status = "okay";
4498
4499                 #address-cells = <1>;
4500                 #size-cells = <0>;
4501
4502                 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
4503                 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
4504                 assigned-clock-rates = <50000000>;
4505
4506                 max-frequency = <50000000>;
4507                 keep-power-in-suspend;
4508
4509                 bus-width = <4>;
4510                 non-removable;
4511
4512                 mmc-pwrseq = <&wifi_pwrseq>;
4513                 vmmc-supply = <&sdmmc_3v3_reg>;
4514                 vqmmc-supply = <&vdd_1v8>;
4515
4516                 /* Azurewave AW-NH660 BCM4330 */
4517                 brcmf: wifi@1 {
4518                         reg = <1>;
4519                         compatible = "brcm,bcm4329-fmac";
4520                         interrupt-parent = <&gpio>;
4521                         interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
4522                         interrupt-names = "host-wake";
4523                 };
4524         };
4525
4526         sdmmc4: mmc@78000600 {
4527                 status = "okay";
4528
4529                 keep-power-in-suspend;
4530                 bus-width = <8>;
4531                 non-removable;
4532                 vmmc-supply = <&sys_3v3_reg>;
4533                 vqmmc-supply = <&vdd_1v8>;
4534                 nvidia,default-tap = <0x0F>;
4535                 max-frequency = <25500000>;
4536         };
4537
4538         usb@7d000000 {
4539                 compatible = "nvidia,tegra30-udc";
4540                 status = "okay";
4541         };
4542
4543         usb-phy@7d000000 {
4544                 status = "okay";
4545                 dr_mode = "peripheral";
4546         };
4547
4548         usb@7d004000 {
4549                 status = "okay";
4550                 #address-cells = <1>;
4551                 #size-cells = <0>;
4552
4553                 ethernet@2 { /* SMSC 10/100T Ethernet Controller */
4554                         compatible = "usb424,9e00";
4555                         reg = <2>;
4556                         local-mac-address = [00 11 22 33 44 55];
4557                 };
4558         };
4559
4560         usb-phy@7d004000 {
4561                 vbus-supply = <&vdd_smsc>;
4562                 status = "okay";
4563         };
4564
4565         usb@7d008000 {
4566                 status = "okay";
4567         };
4568
4569         usb-phy@7d008000 {
4570                 vbus-supply = <&usb3_vbus_reg>;
4571                 status = "okay";
4572         };
4573
4574         /* PMIC has a built-in 32KHz oscillator which is used by PMC */
4575         clk32k_in: clock {
4576                 compatible = "fixed-clock";
4577                 #clock-cells = <0>;
4578                 clock-frequency = <32768>;
4579                 clock-output-names = "pmic-oscillator";
4580         };
4581
4582         cpus {
4583                 cpu0: cpu@0 {
4584                         operating-points-v2 = <&cpu0_opp_table>;
4585                         cpu-supply = <&vdd_cpu>;
4586                         #cooling-cells = <2>;
4587                 };
4588
4589                 cpu1: cpu@1 {
4590                         operating-points-v2 = <&cpu0_opp_table>;
4591                         cpu-supply = <&vdd_cpu>;
4592                         #cooling-cells = <2>;
4593                 };
4594
4595                 cpu2: cpu@2 {
4596                         operating-points-v2 = <&cpu0_opp_table>;
4597                         cpu-supply = <&vdd_cpu>;
4598                         #cooling-cells = <2>;
4599                 };
4600
4601                 cpu3: cpu@3 {
4602                         operating-points-v2 = <&cpu0_opp_table>;
4603                         cpu-supply = <&vdd_cpu>;
4604                         #cooling-cells = <2>;
4605                 };
4606         };
4607
4608         fan: fan {
4609                 compatible = "gpio-fan";
4610                 gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
4611                 gpio-fan,speed-map = <0    0
4612                                       4500 1>;
4613                 #cooling-cells = <2>;
4614         };
4615
4616         gpio-keys {
4617                 compatible = "gpio-keys";
4618
4619                 key-power {
4620                         gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
4621                         debounce-interval = <10>;
4622                         linux,code = <KEY_POWER>;
4623                         wakeup-event-action = <EV_ACT_ASSERTED>;
4624                         wakeup-source;
4625                 };
4626         };
4627
4628         leds {
4629                 compatible = "gpio-leds";
4630
4631                 led-power {
4632                         label = "power-led";
4633                         gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
4634                         default-state = "on";
4635                         linux,default-trigger = "heartbeat";
4636                         retain-state-suspended;
4637                 };
4638         };
4639
4640         opp-table-actmon {
4641                 /delete-node/ opp-900000000;
4642         };
4643
4644         opp-table-emc {
4645                 /delete-node/ opp-900000000-1350;
4646         };
4647
4648         wifi_pwrseq: pwrseq-wifi {
4649                 compatible = "mmc-pwrseq-simple";
4650
4651                 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
4652                 clock-names = "ext_clock";
4653
4654                 reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
4655                 post-power-on-delay-ms = <300>;
4656                 power-off-delay-us = <300>;
4657         };
4658
4659         vdd_12v_in: regulator-vdd-12v-in {
4660                 compatible = "regulator-fixed";
4661                 regulator-name = "vdd_12v_in";
4662                 regulator-min-microvolt = <12000000>;
4663                 regulator-max-microvolt = <12000000>;
4664                 regulator-always-on;
4665         };
4666
4667         sdmmc_3v3_reg: regulator-sdmmc-3v3 {
4668                 compatible = "regulator-fixed";
4669                 regulator-name = "sdmmc_3v3";
4670                 regulator-min-microvolt = <3300000>;
4671                 regulator-max-microvolt = <3300000>;
4672                 enable-active-high;
4673                 regulator-always-on;
4674                 gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
4675                 vin-supply = <&sys_3v3_reg>;
4676         };
4677
4678         vdd_fuse_3v3_reg: regulator-vdd-fuse-3v3 {
4679                 compatible = "regulator-fixed";
4680                 regulator-name = "vdd_fuse_3v3";
4681                 regulator-min-microvolt = <3300000>;
4682                 regulator-max-microvolt = <3300000>;
4683                 enable-active-high;
4684                 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
4685                 vin-supply = <&sys_3v3_reg>;
4686                 regulator-always-on;
4687         };
4688
4689         vdd_vid_reg: regulator-vdd-vid {
4690                 compatible = "regulator-fixed";
4691                 regulator-name = "vddio_vid";
4692                 regulator-min-microvolt = <5000000>;
4693                 regulator-max-microvolt = <5000000>;
4694                 enable-active-high;
4695                 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
4696                 vin-supply = <&vdd_5v0_reg>;
4697                 regulator-boot-on;
4698         };
4699
4700         ddr_reg: regulator-ddr {
4701                 compatible = "regulator-fixed";
4702                 regulator-name = "vdd_ddr";
4703                 regulator-min-microvolt = <1500000>;
4704                 regulator-max-microvolt = <1500000>;
4705                 regulator-always-on;
4706                 enable-active-high;
4707                 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
4708                 regulator-boot-on;
4709                 vin-supply = <&vdd_12v_in>;
4710         };
4711
4712         sys_3v3_reg: regulator-sys-3v3 {
4713                 compatible = "regulator-fixed";
4714                 regulator-name = "sys_3v3";
4715                 regulator-min-microvolt = <3300000>;
4716                 regulator-max-microvolt = <3300000>;
4717                 enable-active-high;
4718                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
4719                 regulator-always-on;
4720                 regulator-boot-on;
4721                 vin-supply = <&vdd_12v_in>;
4722         };
4723
4724         vdd_5v0_reg: regulator-vdd-5v0 {
4725                 compatible = "regulator-fixed";
4726                 regulator-name = "vdd_5v0";
4727                 regulator-min-microvolt = <5000000>;
4728                 regulator-max-microvolt = <5000000>;
4729                 enable-active-high;
4730                 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
4731                 regulator-always-on;
4732                 regulator-boot-on;
4733                 vin-supply = <&vdd_12v_in>;
4734         };
4735
4736         vdd_smsc: regulator-vdd-smsc {
4737                 compatible = "regulator-fixed";
4738                 regulator-name = "vdd_smsc";
4739                 enable-active-high;
4740                 gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
4741         };
4742
4743         usb3_vbus_reg: regulator-usb3-vbus {
4744                 compatible = "regulator-fixed";
4745                 regulator-name = "usb3_vbus";
4746                 regulator-min-microvolt = <5000000>;
4747                 regulator-max-microvolt = <5000000>;
4748                 enable-active-high;
4749                 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
4750                 vin-supply = <&vdd_5v0_reg>;
4751         };
4752
4753         thermal-zones {
4754                 cpu_thermal: cpu-thermal {
4755                         polling-delay = <5000>;
4756                         polling-delay-passive = <5000>;
4757
4758                         thermal-sensors = <&cpu_temp 1>;
4759
4760                         trips {
4761                                 cpu_alert0: cpu-alert0 {
4762                                         temperature = <50000>;
4763                                         hysteresis = <10000>;
4764                                         type = "active";
4765                                 };
4766                                 cpu_alert1: cpu-alert1 {
4767                                         temperature = <70000>;
4768                                         hysteresis = <5000>;
4769                                         type = "passive";
4770                                 };
4771                                 cpu_crit: cpu-crit {
4772                                         temperature = <90000>;
4773                                         hysteresis = <2000>;
4774                                         type = "critical";
4775                                 };
4776                         };
4777
4778                         cooling-maps {
4779                                 map0 {
4780                                         trip = <&cpu_alert0>;
4781                                         cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4782                                 };
4783                                 map1 {
4784                                         trip = <&cpu_alert1>;
4785                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4786                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4787                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4788                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4789                                                          <&actmon THERMAL_NO_LIMIT
4790                                                                   THERMAL_NO_LIMIT>;
4791                                 };
4792                         };
4793                 };
4794         };
4795 };