arch/arm/boot/dts/tegra30-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/input/input.h>
   3 #include "tegra30.dtsi"
   4
   5 /*
   6  * Toradex Colibri T30 Module Device Tree
   7  * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
   8  */
   9 / {
  10         model = "Toradex Colibri T30";
  11         compatible = "toradex,colibri_t30", "nvidia,tegra30";
  12
  13         memory@80000000 {
  14                 reg = <0x80000000 0x40000000>;
  15         };
  16
  17         host1x@50000000 {
  18                 hdmi@54280000 {
  19                         nvidia,ddc-i2c-bus = <&hdmiddc>;
  20                         nvidia,hpd-gpio =
  21                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  22                         pll-supply = <&reg_1v8_avdd_hdmi_pll>;
  23                         vdd-supply = <&reg_3v3_avdd_hdmi>;
  24                 };
  25         };
  26
  27         pinmux@70000868 {
  28                 pinctrl-names = "default";
  29                 pinctrl-0 = <&state_default>;
  30
  31                 state_default: pinmux {
  32                         /* Analogue Audio (On-module) */
  33                         clk1-out-pw4 {
  34                                 nvidia,pins = "clk1_out_pw4";
  35                                 nvidia,function = "extperiph1";
  36                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  37                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  38                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  39                         };
  40                         dap3-fs-pp0 {
  41                                 nvidia,pins = "dap3_fs_pp0",
  42                                               "dap3_sclk_pp3",
  43                                               "dap3_din_pp1",
  44                                               "dap3_dout_pp2";
  45                                 nvidia,function = "i2s2";
  46                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  47                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  48                         };
  49
  50                         /* Colibri Address/Data Bus (GMI) */
  51                         gmi-ad0-pg0 {
  52                                 nvidia,pins = "gmi_ad0_pg0",
  53                                               "gmi_ad2_pg2",
  54                                               "gmi_ad3_pg3",
  55                                               "gmi_ad4_pg4",
  56                                               "gmi_ad5_pg5",
  57                                               "gmi_ad6_pg6",
  58                                               "gmi_ad7_pg7",
  59                                               "gmi_ad8_ph0",
  60                                               "gmi_ad9_ph1",
  61                                               "gmi_ad10_ph2",
  62                                               "gmi_ad11_ph3",
  63                                               "gmi_ad12_ph4",
  64                                               "gmi_ad13_ph5",
  65                                               "gmi_ad14_ph6",
  66                                               "gmi_ad15_ph7",
  67                                               "gmi_adv_n_pk0",
  68                                               "gmi_clk_pk1",
  69                                               "gmi_cs4_n_pk2",
  70                                               "gmi_cs2_n_pk3",
  71                                               "gmi_iordy_pi5",
  72                                               "gmi_oe_n_pi1",
  73                                               "gmi_wait_pi7",
  74                                               "gmi_wr_n_pi0",
  75                                               "dap1_fs_pn0",
  76                                               "dap1_din_pn1",
  77                                               "dap1_dout_pn2",
  78                                               "dap1_sclk_pn3",
  79                                               "dap2_fs_pa2",
  80                                               "dap2_sclk_pa3",
  81                                               "dap2_din_pa4",
  82                                               "dap2_dout_pa5",
  83                                               "spi1_sck_px5",
  84                                               "spi1_mosi_px4",
  85                                               "spi1_cs0_n_px6",
  86                                               "spi2_cs0_n_px3",
  87                                               "spi2_miso_px1",
  88                                               "spi2_mosi_px0",
  89                                               "spi2_sck_px2",
  90                                               "uart2_cts_n_pj5",
  91                                               "uart2_rts_n_pj6";
  92                                 nvidia,function = "gmi";
  93                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  94                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  95                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  96                         };
  97                         /* Further pins may be used as GPIOs */
  98                         dap4-din-pp5 {
  99                                 nvidia,pins = "dap4_din_pp5",
 100                                               "dap4_dout_pp6",
 101                                               "dap4_fs_pp4",
 102                                               "dap4_sclk_pp7",
 103                                               "pbb7",
 104                                               "sdmmc1_clk_pz0",
 105                                               "sdmmc1_cmd_pz1",
 106                                               "sdmmc1_dat0_py7",
 107                                               "sdmmc1_dat1_py6",
 108                                               "sdmmc1_dat3_py4",
 109                                               "uart3_cts_n_pa1",
 110                                               "uart3_txd_pw6",
 111                                               "uart3_rxd_pw7";
 112                                 nvidia,function = "rsvd2";
 113                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 114                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 115                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 116                         };
 117                         lcd-d18-pm2 {
 118                                 nvidia,pins = "lcd_d18_pm2",
 119                                               "lcd_d19_pm3",
 120                                               "lcd_d20_pm4",
 121                                               "lcd_d21_pm5",
 122                                               "lcd_d22_pm6",
 123                                               "lcd_d23_pm7",
 124                                               "lcd_dc0_pn6",
 125                                               "pex_l2_clkreq_n_pcc7";
 126                                 nvidia,function = "rsvd3";
 127                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 128                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 129                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 130                         };
 131                         lcd-cs0-n-pn4 {
 132                                 nvidia,pins = "lcd_cs0_n_pn4",
 133                                               "lcd_sdin_pz2",
 134                                               "pu0",
 135                                               "pu1",
 136                                               "pu2",
 137                                               "pu3",
 138                                               "pu4",
 139                                               "pu5",
 140                                               "pu6",
 141                                               "spi1_miso_px7",
 142                                               "uart3_rts_n_pc0";
 143                                 nvidia,function = "rsvd4";
 144                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 145                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 146                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 147                         };
 148                         lcd-pwr0-pb2 {
 149                                 nvidia,pins = "lcd_pwr0_pb2",
 150                                               "lcd_sck_pz4",
 151                                               "lcd_sdout_pn5",
 152                                               "lcd_wr_n_pz3";
 153                                 nvidia,function = "hdcp";
 154                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 155                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 156                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 157                         };
 158                         pbb4 {
 159                                 nvidia,pins = "pbb4",
 160                                               "pbb5",
 161                                               "pbb6";
 162                                 nvidia,function = "displayb";
 163                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 164                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 165                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 166                         };
 167                         /* Multiplexed RDnWR and therefore disabled */
 168                         lcd-cs1-n-pw0 {
 169                                 nvidia,pins = "lcd_cs1_n_pw0";
 170                                 nvidia,function = "rsvd4";
 171                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 172                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 173                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 174                         };
 175                         /* Multiplexed GMI_CLK and therefore disabled */
 176                         owr {
 177                                 nvidia,pins = "owr";
 178                                 nvidia,function = "rsvd3";
 179                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 180                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 181                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 182                         };
 183                         /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
 184                         sdmmc3-dat4-pd1 {
 185                                 nvidia,pins = "sdmmc3_dat4_pd1";
 186                                 nvidia,function = "sdmmc3";
 187                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 188                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 189                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 190                         };
 191                         /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
 192                         sdmmc3-dat5-pd0 {
 193                                 nvidia,pins = "sdmmc3_dat5_pd0";
 194                                 nvidia,function = "sdmmc3";
 195                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 196                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 197                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 198                         };
 199
 200                         /* Colibri BL_ON */
 201                         pv2 {
 202                                 nvidia,pins = "pv2";
 203                                 nvidia,function = "rsvd4";
 204                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 205                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 206                         };
 207
 208                         /* Colibri Backlight PWM<A> */
 209                         sdmmc3-dat3-pb4 {
 210                                 nvidia,pins = "sdmmc3_dat3_pb4";
 211                                 nvidia,function = "pwm0";
 212                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 213                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 214                         };
 215
 216                         /* Colibri CAN_INT */
 217                         kb-row8-ps0 {
 218                                 nvidia,pins = "kb_row8_ps0";
 219                                 nvidia,function = "kbc";
 220                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 221                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 222                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 223                         };
 224
 225                         /* Colibri DDC */
 226                         ddc-scl-pv4 {
 227                                 nvidia,pins = "ddc_scl_pv4",
 228                                               "ddc_sda_pv5";
 229                                 nvidia,function = "i2c4";
 230                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 231                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 232                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 233                         };
 234
 235                         /* Colibri EXT_IO* */
 236                         gen2-i2c-scl-pt5 {
 237                                 nvidia,pins = "gen2_i2c_scl_pt5",
 238                                               "gen2_i2c_sda_pt6";
 239                                 nvidia,function = "rsvd4";
 240                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 241                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 242                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 243                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 244                         };
 245                         spdif-in-pk6 {
 246                                 nvidia,pins =   "spdif_in_pk6";
 247                                 nvidia,function = "hda";
 248                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 249                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 250                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 251                         };
 252
 253                         /* Colibri GPIO */
 254                         clk2-out-pw5 {
 255                                 nvidia,pins = "clk2_out_pw5",
 256                                               "pcc2",
 257                                               "pv3",
 258                                               "sdmmc1_dat2_py5";
 259                                 nvidia,function = "rsvd2";
 260                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 261                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 262                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 263                         };
 264                         lcd-pwr1-pc1 {
 265                                 nvidia,pins = "lcd_pwr1_pc1",
 266                                               "pex_l1_clkreq_n_pdd6",
 267                                               "pex_l1_rst_n_pdd5";
 268                                 nvidia,function = "rsvd3";
 269                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 270                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 271                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 272                         };
 273                         pv1 {
 274                                 nvidia,pins = "pv1",
 275                                               "sdmmc3_dat0_pb7",
 276                                               "sdmmc3_dat1_pb6";
 277                                 nvidia,function = "rsvd1";
 278                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 279                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 280                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 281                         };
 282
 283                         /* Colibri HOTPLUG_DETECT (HDMI) */
 284                         hdmi-int-pn7 {
 285                                 nvidia,pins = "hdmi_int_pn7";
 286                                 nvidia,function = "hdmi";
 287                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 288                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 289                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 290                         };
 291
 292                         /* Colibri I2C */
 293                         gen1-i2c-scl-pc4 {
 294                                 nvidia,pins = "gen1_i2c_scl_pc4",
 295                                               "gen1_i2c_sda_pc5";
 296                                 nvidia,function = "i2c1";
 297                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 298                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 299                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 300                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 301                         };
 302
 303                         /* Colibri LCD (L_* resp. LDD<*>) */
 304                         lcd-d0-pe0 {
 305                                 nvidia,pins = "lcd_d0_pe0",
 306                                               "lcd_d1_pe1",
 307                                               "lcd_d2_pe2",
 308                                               "lcd_d3_pe3",
 309                                               "lcd_d4_pe4",
 310                                               "lcd_d5_pe5",
 311                                               "lcd_d6_pe6",
 312                                               "lcd_d7_pe7",
 313                                               "lcd_d8_pf0",
 314                                               "lcd_d9_pf1",
 315                                               "lcd_d10_pf2",
 316                                               "lcd_d11_pf3",
 317                                               "lcd_d12_pf4",
 318                                               "lcd_d13_pf5",
 319                                               "lcd_d14_pf6",
 320                                               "lcd_d15_pf7",
 321                                               "lcd_d16_pm0",
 322                                               "lcd_d17_pm1",
 323                                               "lcd_de_pj1",
 324                                               "lcd_hsync_pj3",
 325                                               "lcd_pclk_pb3",
 326                                               "lcd_vsync_pj4";
 327                                 nvidia,function = "displaya";
 328                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 329                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 330                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 331                         };
 332                         /*
 333                          * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
 334                          * today's display need DE, disable LCD_M1
 335                          */
 336                         lcd-m1-pw1 {
 337                                 nvidia,pins = "lcd_m1_pw1";
 338                                 nvidia,function = "rsvd3";
 339                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 340                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 341                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 342                         };
 343
 344                         /* Colibri MMC */
 345                         kb-row10-ps2 {
 346                                 nvidia,pins = "kb_row10_ps2";
 347                                 nvidia,function = "sdmmc2";
 348                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 349                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 350                         };
 351                         kb-row11-ps3 {
 352                                 nvidia,pins = "kb_row11_ps3",
 353                                               "kb_row12_ps4",
 354                                               "kb_row13_ps5",
 355                                               "kb_row14_ps6",
 356                                               "kb_row15_ps7";
 357                                 nvidia,function = "sdmmc2";
 358                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 359                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 360                         };
 361                         /* Colibri MMC_CD */
 362                         gmi-wp-n-pc7 {
 363                                 nvidia,pins = "gmi_wp_n_pc7";
 364                                 nvidia,function = "rsvd1";
 365                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 366                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 367                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 368                         };
 369                         /* Multiplexed and therefore disabled */
 370                         cam-mclk-pcc0 {
 371                                 nvidia,pins =   "cam_mclk_pcc0";
 372                                 nvidia,function = "vi_alt3";
 373                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 374                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 375                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 376                         };
 377                         cam-i2c-scl-pbb1 {
 378                                 nvidia,pins = "cam_i2c_scl_pbb1",
 379                                               "cam_i2c_sda_pbb2";
 380                                 nvidia,function = "rsvd3";
 381                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 382                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 383                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 384                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 385                         };
 386                         pbb0 {
 387                                 nvidia,pins = "pbb0",
 388                                               "pcc1";
 389                                 nvidia,function = "rsvd2";
 390                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 391                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 392                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 393                         };
 394                         pbb3 {
 395                                 nvidia,pins = "pbb3";
 396                                 nvidia,function = "displayb";
 397                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 398                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 399                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 400                         };
 401
 402                         /* Colibri nRESET_OUT */
 403                         gmi-rst-n-pi4 {
 404                                 nvidia,pins = "gmi_rst_n_pi4";
 405                                 nvidia,function = "gmi";
 406                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 407                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 408                         };
 409
 410                         /*
 411                          * Colibri Parallel Camera (Optional)
 412                          * pins multiplexed with others and therefore disabled
 413                          */
 414                         vi-vsync-pd6 {
 415                                 nvidia,pins = "vi_d0_pt4",
 416                                               "vi_d1_pd5",
 417                                               "vi_d2_pl0",
 418                                               "vi_d3_pl1",
 419                                               "vi_d4_pl2",
 420                                               "vi_d5_pl3",
 421                                               "vi_d6_pl4",
 422                                               "vi_d7_pl5",
 423                                               "vi_d8_pl6",
 424                                               "vi_d9_pl7",
 425                                               "vi_d10_pt2",
 426                                               "vi_d11_pt3",
 427                                               "vi_hsync_pd7",
 428                                               "vi_mclk_pt1",
 429                                               "vi_pclk_pt0",
 430                                               "vi_vsync_pd6";
 431                                 nvidia,function = "vi";
 432                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 433                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 434                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 435                         };
 436
 437                         /* Colibri PWM<B> */
 438                         sdmmc3-dat2-pb5 {
 439                                 nvidia,pins = "sdmmc3_dat2_pb5";
 440                                 nvidia,function = "pwm1";
 441                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 442                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 443                         };
 444
 445                         /* Colibri PWM<C> */
 446                         sdmmc3-clk-pa6 {
 447                                 nvidia,pins = "sdmmc3_clk_pa6";
 448                                 nvidia,function = "pwm2";
 449                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 450                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 451                         };
 452
 453                         /* Colibri PWM<D> */
 454                         sdmmc3-cmd-pa7 {
 455                                 nvidia,pins = "sdmmc3_cmd_pa7";
 456                                 nvidia,function = "pwm3";
 457                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 458                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 459                         };
 460
 461                         /* Colibri SSP */
 462                         ulpi-clk-py0 {
 463                                 nvidia,pins = "ulpi_clk_py0",
 464                                               "ulpi_dir_py1",
 465                                               "ulpi_nxt_py2",
 466                                               "ulpi_stp_py3";
 467                                 nvidia,function = "spi1";
 468                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 469                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 470                         };
 471                         /* Multiplexed SSPFRM, SSPTXD and therefore disabled */
 472                         sdmmc3-dat6-pd3 {
 473                                 nvidia,pins = "sdmmc3_dat6_pd3",
 474                                               "sdmmc3_dat7_pd4";
 475                                 nvidia,function = "spdif";
 476                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 477                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 478                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 479                         };
 480
 481                         /* Colibri UART-A */
 482                         ulpi-data0 {
 483                                 nvidia,pins = "ulpi_data0_po1",
 484                                               "ulpi_data1_po2",
 485                                               "ulpi_data2_po3",
 486                                               "ulpi_data3_po4",
 487                                               "ulpi_data4_po5",
 488                                               "ulpi_data5_po6",
 489                                               "ulpi_data6_po7",
 490                                               "ulpi_data7_po0";
 491                                 nvidia,function = "uarta";
 492                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 493                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 494                         };
 495
 496                         /* Colibri UART-B */
 497                         gmi-a16-pj7 {
 498                                 nvidia,pins = "gmi_a16_pj7",
 499                                               "gmi_a17_pb0",
 500                                               "gmi_a18_pb1",
 501                                               "gmi_a19_pk7";
 502                                 nvidia,function = "uartd";
 503                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 504                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 505                         };
 506
 507                         /* Colibri UART-C */
 508                         uart2-rxd {
 509                                 nvidia,pins = "uart2_rxd_pc3",
 510                                               "uart2_txd_pc2";
 511                                 nvidia,function = "uartb";
 512                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 513                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 514                         };
 515
 516                         /* Colibri USBC_DET */
 517                         spdif-out-pk5 {
 518                                 nvidia,pins =   "spdif_out_pk5";
 519                                 nvidia,function = "rsvd2";
 520                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 521                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 522                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 523                         };
 524
 525                         /* Colibri USBH_PEN */
 526                         spi2-cs1-n-pw2 {
 527                                 nvidia,pins = "spi2_cs1_n_pw2";
 528                                 nvidia,function = "spi2_alt";
 529                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 530                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 531                         };
 532
 533                         /* Colibri USBH_OC */
 534                         spi2-cs2-n-pw3, {
 535                                 nvidia,pins = "spi2_cs2_n_pw3";
 536                                 nvidia,function = "spi2_alt";
 537                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 538                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 539                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 540                         };
 541
 542                         /* Colibri VGA not supported and therefore disabled */
 543                         crt-hsync-pv6 {
 544                                 nvidia,pins = "crt_hsync_pv6",
 545                                               "crt_vsync_pv7";
 546                                 nvidia,function = "rsvd2";
 547                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 548                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 549                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 550                         };
 551
 552                         /* eMMC (On-module) */
 553                         sdmmc4-clk-pcc4 {
 554                                 nvidia,pins = "sdmmc4_clk_pcc4",
 555                                               "sdmmc4_cmd_pt7",
 556                                               "sdmmc4_rst_n_pcc3";
 557                                 nvidia,function = "sdmmc4";
 558                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 559                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 560                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 561                         };
 562                         sdmmc4-dat0-paa0 {
 563                                 nvidia,pins = "sdmmc4_dat0_paa0",
 564                                               "sdmmc4_dat1_paa1",
 565                                               "sdmmc4_dat2_paa2",
 566                                               "sdmmc4_dat3_paa3",
 567                                               "sdmmc4_dat4_paa4",
 568                                               "sdmmc4_dat5_paa5",
 569                                               "sdmmc4_dat6_paa6",
 570                                               "sdmmc4_dat7_paa7";
 571                                 nvidia,function = "sdmmc4";
 572                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 573                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 574                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 575                         };
 576
 577                         /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
 578                         pex-l0-rst-n-pdd1 {
 579                                 nvidia,pins = "pex_l0_rst_n_pdd1",
 580                                               "pex_wake_n_pdd3";
 581                                 nvidia,function = "rsvd3";
 582                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 583                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 584                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 585                         };
 586                         /* LAN_V_BUS, LAN_RESET# (On-module) */
 587                         pex-l0-clkreq-n-pdd2 {
 588                                 nvidia,pins = "pex_l0_clkreq_n_pdd2",
 589                                               "pex_l0_prsnt_n_pdd0";
 590                                 nvidia,function = "rsvd3";
 591                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 592                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 593                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 594                         };
 595
 596                         /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */
 597                         pex-l2-rst-n-pcc6 {
 598                                 nvidia,pins = "pex_l2_rst_n_pcc6",
 599                                               "pex_l2_prsnt_n_pdd7";
 600                                 nvidia,function = "rsvd3";
 601                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 602                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 603                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 604                         };
 605
 606                         /* Not connected and therefore disabled */
 607                         clk1-req-pee2 {
 608                                 nvidia,pins = "clk1_req_pee2",
 609                                               "pex_l1_prsnt_n_pdd4";
 610                                 nvidia,function = "rsvd3";
 611                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 612                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 613                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 614                         };
 615                         clk2-req-pcc5 {
 616                                 nvidia,pins = "clk2_req_pcc5",
 617                                               "clk3_out_pee0",
 618                                               "clk3_req_pee1",
 619                                               "clk_32k_out_pa0",
 620                                               "hdmi_cec_pee3",
 621                                               "sys_clk_req_pz5";
 622                                 nvidia,function = "rsvd2";
 623                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 624                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 625                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 626                         };
 627                         gmi-dqs-pi2 {
 628                                 nvidia,pins = "gmi_dqs_pi2",
 629                                               "kb_col2_pq2",
 630                                               "kb_col3_pq3",
 631                                               "kb_col4_pq4",
 632                                               "kb_col5_pq5",
 633                                               "kb_row4_pr4";
 634                                 nvidia,function = "rsvd4";
 635                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 636                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 637                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 638                         };
 639                         kb-col0-pq0 {
 640                                 nvidia,pins = "kb_col0_pq0",
 641                                               "kb_col1_pq1",
 642                                               "kb_col6_pq6",
 643                                               "kb_col7_pq7",
 644                                               "kb_row5_pr5",
 645                                               "kb_row6_pr6",
 646                                               "kb_row7_pr7",
 647                                               "kb_row9_ps1";
 648                                 nvidia,function = "kbc";
 649                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 650                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 651                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 652                         };
 653                         kb-row0-pr0 {
 654                                 nvidia,pins = "kb_row0_pr0",
 655                                               "kb_row1_pr1",
 656                                               "kb_row2_pr2",
 657                                               "kb_row3_pr3";
 658                                 nvidia,function = "rsvd3";
 659                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 660                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 661                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 662                         };
 663                         lcd-pwr2-pc6 {
 664                                 nvidia,pins = "lcd_pwr2_pc6";
 665                                 nvidia,function = "hdcp";
 666                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 667                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 668                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 669                         };
 670
 671                         /* Power I2C (On-module) */
 672                         pwr-i2c-scl-pz6 {
 673                                 nvidia,pins = "pwr_i2c_scl_pz6",
 674                                               "pwr_i2c_sda_pz7";
 675                                 nvidia,function = "i2cpwr";
 676                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 677                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 678                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 679                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 680                         };
 681
 682                         /*
 683                          * THERMD_ALERT#, unlatched I2C address pin of LM95245
 684                          * temperature sensor therefore requires disabling for
 685                          * now
 686                          */
 687                         lcd-dc1-pd2 {
 688                                 nvidia,pins = "lcd_dc1_pd2";
 689                                 nvidia,function = "rsvd3";
 690                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 691                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 692                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 693                         };
 694
 695                         /* TOUCH_PEN_INT# (On-module) */
 696                         pv0 {
 697                                 nvidia,pins = "pv0";
 698                                 nvidia,function = "rsvd1";
 699                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 700                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 701                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 702                         };
 703                 };
 704         };
 705
 706         serial@70006040 {
 707                 compatible = "nvidia,tegra30-hsuart";
 708         };
 709
 710         serial@70006300 {
 711                 compatible = "nvidia,tegra30-hsuart";
 712         };
 713
 714         hdmiddc: i2c@7000c700 {
 715                 clock-frequency = <10000>;
 716         };
 717
 718         /*
 719          * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 720          * touch screen controller
 721          */
 722         i2c@7000d000 {
 723                 status = "okay";
 724                 clock-frequency = <100000>;
 725
 726                 /* SGTL5000 audio codec */
 727                 sgtl5000: codec@a {
 728                         compatible = "fsl,sgtl5000";
 729                         reg = <0x0a>;
 730                         VDDA-supply = <&reg_module_3v3_audio>;
 731                         VDDD-supply = <&reg_1v8_vio>;
 732                         VDDIO-supply = <&reg_module_3v3>;
 733                         clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
 734                 };
 735
 736                 pmic: tps65911@2d {
 737                         compatible = "ti,tps65911";
 738                         reg = <0x2d>;
 739
 740                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 741                         #interrupt-cells = <2>;
 742                         interrupt-controller;
 743
 744                         ti,system-power-controller;
 745
 746                         #gpio-cells = <2>;
 747                         gpio-controller;
 748
 749                         vcc1-supply = <&reg_module_3v3>;
 750                         vcc2-supply = <&reg_module_3v3>;
 751                         vcc3-supply = <&reg_1v8_vio>;
 752                         vcc4-supply = <&reg_module_3v3>;
 753                         vcc5-supply = <&reg_module_3v3>;
 754                         vcc6-supply = <&reg_1v8_vio>;
 755                         vcc7-supply = <&reg_5v0_charge_pump>;
 756                         vccio-supply = <&reg_module_3v3>;
 757
 758                         regulators {
 759                                 vdd1_reg: vdd1 {
 760                                         regulator-name = "+V1.35_VDDIO_DDR";
 761                                         regulator-min-microvolt = <1350000>;
 762                                         regulator-max-microvolt = <1350000>;
 763                                         regulator-always-on;
 764                                 };
 765
 766                                 /* SW2: unused */
 767
 768                                 vddctrl_reg: vddctrl {
 769                                         regulator-name = "+V1.0_VDD_CPU";
 770                                         regulator-min-microvolt = <1150000>;
 771                                         regulator-max-microvolt = <1150000>;
 772                                         regulator-always-on;
 773                                 };
 774
 775                                 reg_1v8_vio: vio {
 776                                         regulator-name = "+V1.8";
 777                                         regulator-min-microvolt = <1800000>;
 778                                         regulator-max-microvolt = <1800000>;
 779                                         regulator-always-on;
 780                                 };
 781
 782                                 /* LDO1: unused */
 783
 784                                 /*
 785                                  * EN_+V3.3 switching via FET:
 786                                  * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
 787                                  * see also +V3.3 fixed supply
 788                                  */
 789                                 ldo2_reg: ldo2 {
 790                                         regulator-name = "EN_+V3.3";
 791                                         regulator-min-microvolt = <3300000>;
 792                                         regulator-max-microvolt = <3300000>;
 793                                         regulator-always-on;
 794                                 };
 795
 796                                 /* LDO3: unused */
 797
 798                                 ldo4_reg: ldo4 {
 799                                         regulator-name = "+V1.2_VDD_RTC";
 800                                         regulator-min-microvolt = <1200000>;
 801                                         regulator-max-microvolt = <1200000>;
 802                                         regulator-always-on;
 803                                 };
 804
 805                                 /*
 806                                  * +V2.8_AVDD_VDAC:
 807                                  * only required for (unsupported) analog RGB
 808                                  */
 809                                 ldo5_reg: ldo5 {
 810                                         regulator-name = "+V2.8_AVDD_VDAC";
 811                                         regulator-min-microvolt = <2800000>;
 812                                         regulator-max-microvolt = <2800000>;
 813                                         regulator-always-on;
 814                                 };
 815
 816                                 /*
 817                                  * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
 818                                  * but LDO6 can't set voltage in 50mV
 819                                  * granularity
 820                                  */
 821                                 ldo6_reg: ldo6 {
 822                                         regulator-name = "+V1.05_AVDD_PLLE";
 823                                         regulator-min-microvolt = <1100000>;
 824                                         regulator-max-microvolt = <1100000>;
 825                                 };
 826
 827                                 ldo7_reg: ldo7 {
 828                                         regulator-name = "+V1.2_AVDD_PLL";
 829                                         regulator-min-microvolt = <1200000>;
 830                                         regulator-max-microvolt = <1200000>;
 831                                         regulator-always-on;
 832                                 };
 833
 834                                 ldo8_reg: ldo8 {
 835                                         regulator-name = "+V1.0_VDD_DDR_HS";
 836                                         regulator-min-microvolt = <1000000>;
 837                                         regulator-max-microvolt = <1000000>;
 838                                         regulator-always-on;
 839                                 };
 840                         };
 841                 };
 842
 843                 /* STMPE811 touch screen controller */
 844                 stmpe811@41 {
 845                         compatible = "st,stmpe811";
 846                         reg = <0x41>;
 847                         irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
 848                         interrupt-controller;
 849                         id = <0>;
 850                         blocks = <0x5>;
 851                         irq-trigger = <0x1>;
 852
 853                         stmpe_touchscreen {
 854                                 compatible = "st,stmpe-ts";
 855                                 /* 3.25 MHz ADC clock speed */
 856                                 st,adc-freq = <1>;
 857                                 /* 8 sample average control */
 858                                 st,ave-ctrl = <3>;
 859                                 /* 7 length fractional part in z */
 860                                 st,fraction-z = <7>;
 861                                 /*
 862                                  * 50 mA typical 80 mA max touchscreen drivers
 863                                  * current limit value
 864                                  */
 865                                 st,i-drive = <1>;
 866                                 /* 12-bit ADC */
 867                                 st,mod-12b = <1>;
 868                                 /* internal ADC reference */
 869                                 st,ref-sel = <0>;
 870                                 /* ADC converstion time: 80 clocks */
 871                                 st,sample-time = <4>;
 872                                 /* 1 ms panel driver settling time */
 873                                 st,settling = <3>;
 874                                 /* 5 ms touch detect interrupt delay */
 875                                 st,touch-det-delay = <5>;
 876                         };
 877                 };
 878
 879                 /*
 880                  * LM95245 temperature sensor
 881                  * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
 882                  */
 883                 temp-sensor@4c {
 884                         compatible = "national,lm95245";
 885                         reg = <0x4c>;
 886                 };
 887
 888                 /* SW: +V1.2_VDD_CORE */
 889                 tps62362@60 {
 890                         compatible = "ti,tps62362";
 891                         reg = <0x60>;
 892
 893                         regulator-name = "tps62362-vout";
 894                         regulator-min-microvolt = <900000>;
 895                         regulator-max-microvolt = <1400000>;
 896                         regulator-boot-on;
 897                         regulator-always-on;
 898                         ti,vsel0-state-low;
 899                         /* VSEL1: EN_CORE_DVFS_N low for DVFS */
 900                         ti,vsel1-state-low;
 901                 };
 902         };
 903
 904         pmc@7000e400 {
 905                 nvidia,invert-interrupt;
 906                 nvidia,suspend-mode = <1>;
 907                 nvidia,cpu-pwr-good-time = <5000>;
 908                 nvidia,cpu-pwr-off-time = <5000>;
 909                 nvidia,core-pwr-good-time = <3845 3845>;
 910                 nvidia,core-pwr-off-time = <0>;
 911                 nvidia,core-power-req-active-high;
 912                 nvidia,sys-clock-req-active-high;
 913         };
 914
 915         ahub@70080000 {
 916                 i2s@70080500 {
 917                         status = "okay";
 918                 };
 919         };
 920
 921         /* eMMC */
 922         sdhci@78000600 {
 923                 status = "okay";
 924                 bus-width = <8>;
 925                 non-removable;
 926         };
 927
 928         /* EHCI instance 1: USB2_DP/N -> AX88772B */
 929         usb@7d004000 {
 930                 status = "okay";
 931                 #address-cells = <1>;
 932                 #size-cells = <0>;
 933
 934                 asix@1 {
 935                         reg = <1>;
 936                         local-mac-address = [00 00 00 00 00 00];
 937                 };
 938         };
 939
 940         usb-phy@7d004000 {
 941                 status = "okay";
 942                 nvidia,is-wired = <1>;
 943                 vbus-supply = <&reg_lan_v_bus>;
 944         };
 945
 946         clocks {
 947                 compatible = "simple-bus";
 948                 #address-cells = <1>;
 949                 #size-cells = <0>;
 950
 951                 clk32k_in: clk@0 {
 952                         compatible = "fixed-clock";
 953                         reg = <0>;
 954                         #clock-cells = <0>;
 955                         clock-frequency = <32768>;
 956                 };
 957         };
 958
 959         reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
 960                 compatible = "regulator-fixed";
 961                 regulator-name = "+V1.8_AVDD_HDMI_PLL";
 962                 regulator-min-microvolt = <1800000>;
 963                 regulator-max-microvolt = <1800000>;
 964                 enable-active-high;
 965                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 966                 vin-supply = <&reg_1v8_vio>;
 967         };
 968
 969         reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
 970                 compatible = "regulator-fixed";
 971                 regulator-name = "+V3.3_AVDD_HDMI";
 972                 regulator-min-microvolt = <3300000>;
 973                 regulator-max-microvolt = <3300000>;
 974                 enable-active-high;
 975                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 976                 vin-supply = <&reg_module_3v3>;
 977         };
 978
 979         reg_5v0_charge_pump: regulator-5v0-charge-pump {
 980                 compatible = "regulator-fixed";
 981                 regulator-name = "+V5.0";
 982                 regulator-min-microvolt = <5000000>;
 983                 regulator-max-microvolt = <5000000>;
 984                 regulator-always-on;
 985         };
 986
 987         reg_lan_v_bus: regulator-lan-v-bus {
 988                 compatible = "regulator-fixed";
 989                 regulator-name = "LAN_V_BUS";
 990                 regulator-min-microvolt = <5000000>;
 991                 regulator-max-microvolt = <5000000>;
 992                 enable-active-high;
 993                 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
 994         };
 995
 996         reg_module_3v3: regulator-module-3v3 {
 997                 compatible = "regulator-fixed";
 998                 regulator-name = "+V3.3";
 999                 regulator-min-microvolt = <3300000>;
1000                 regulator-max-microvolt = <3300000>;
1001                 regulator-always-on;
1002         };
1003
1004         reg_module_3v3_audio: regulator-module-3v3-audio {
1005                 compatible = "regulator-fixed";
1006                 regulator-name = "+V3.3_AUDIO_AVDD_S";
1007                 regulator-min-microvolt = <3300000>;
1008                 regulator-max-microvolt = <3300000>;
1009                 regulator-always-on;
1010         };
1011
1012         sound {
1013                 compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
1014                              "nvidia,tegra-audio-sgtl5000";
1015                 nvidia,model = "Toradex Colibri T30";
1016                 nvidia,audio-routing =
1017                         "Headphone Jack", "HP_OUT",
1018                         "LINE_IN", "Line In Jack",
1019                         "MIC_IN", "Mic Jack";
1020                 nvidia,i2s-controller = <&tegra_i2s2>;
1021                 nvidia,audio-codec = <&sgtl5000>;
1022                 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1023                          <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1024                          <&tegra_car TEGRA30_CLK_EXTERN1>;
1025                 clock-names = "pll_a", "pll_a_out0", "mclk";
1026         };
1027 };