arch/arm/boot/dts/tegra30-apalis.dtsi

   1 #include "tegra30.dtsi"
   2
   3 /*
   4  * Toradex Apalis T30 Device Tree
   5  * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C
   6  */
   7 / {
   8         model = "Toradex Apalis T30";
   9         compatible = "toradex,apalis_t30", "nvidia,tegra30";
  10
  11         pcie-controller@00003000 {
  12                 pex-clk-supply = <&sys_3v3_reg>;
  13                 vdd-supply = <&vdd2_reg>;
  14                 avdd-supply = <&ldo6_reg>;
  15
  16                 pci@1,0 {
  17                         nvidia,num-lanes = <4>;
  18                 };
  19
  20                 pci@2,0 {
  21                         nvidia,num-lanes = <1>;
  22                 };
  23
  24                 pci@3,0 {
  25                         nvidia,num-lanes = <1>;
  26                 };
  27         };
  28
  29         host1x@50000000 {
  30                 hdmi@54280000 {
  31                         vdd-supply = <&sys_3v3_reg>;
  32                         pll-supply = <&vio_reg>;
  33
  34                         nvidia,hpd-gpio =
  35                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  36                         nvidia,ddc-i2c-bus = <&hdmiddc>;
  37                 };
  38         };
  39
  40         pinmux@70000868 {
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&state_default>;
  43
  44                 state_default: pinmux {
  45                         /* Apalis BKL1_ON */
  46                         pv2 {
  47                                 nvidia,pins = "pv2";
  48                                 nvidia,function = "rsvd4";
  49                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  50                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  51                         };
  52
  53                         /* Apalis BKL1_PWM */
  54                         uart3_rts_n_pc0 {
  55                                 nvidia,pins =   "uart3_rts_n_pc0";
  56                                 nvidia,function = "pwm0";
  57                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  58                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  59                         };
  60                         /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
  61                         uart3_cts_n_pa1 {
  62                                 nvidia,pins =   "uart3_cts_n_pa1";
  63                                 nvidia,function = "rsvd1";
  64                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  65                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  66                         };
  67
  68                         /* Apalis CAN1 on SPI6 */
  69                         spi2_cs0_n_px3 {
  70                                 nvidia,pins =   "spi2_cs0_n_px3",
  71                                                 "spi2_miso_px1",
  72                                                 "spi2_mosi_px0",
  73                                                 "spi2_sck_px2";
  74                                 nvidia,function = "spi6";
  75                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  76                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  77                         };
  78                         /* CAN_INT1 */
  79                         spi2_cs1_n_pw2 {
  80                                 nvidia,pins = "spi2_cs1_n_pw2";
  81                                 nvidia,function = "spi3";
  82                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  83                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  84                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  85                         };
  86
  87                         /* Apalis CAN2 on SPI4 */
  88                         gmi_a16_pj7 {
  89                                 nvidia,pins =   "gmi_a16_pj7",
  90                                                 "gmi_a17_pb0",
  91                                                 "gmi_a18_pb1",
  92                                                 "gmi_a19_pk7";
  93                                 nvidia,function = "spi4";
  94                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  95                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  96                         };
  97                         /* CAN_INT2 */
  98                         spi2_cs2_n_pw3 {
  99                                 nvidia,pins = "spi2_cs2_n_pw3";
 100                                 nvidia,function = "spi3";
 101                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 102                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 103                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 104                         };
 105
 106                         /* Apalis I2C3 */
 107                         cam_i2c_scl_pbb1 {
 108                                 nvidia,pins = "cam_i2c_scl_pbb1",
 109                                               "cam_i2c_sda_pbb2";
 110                                 nvidia,function = "i2c3";
 111                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 112                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 113                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 114                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 115                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 116                         };
 117
 118                         /* Apalis MMC1 */
 119                         sdmmc3_clk_pa6 {
 120                                 nvidia,pins =   "sdmmc3_clk_pa6",
 121                                                 "sdmmc3_cmd_pa7";
 122                                 nvidia,function = "sdmmc3";
 123                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 124                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 125                         };
 126                         sdmmc3_dat0_pb7 {
 127                                 nvidia,pins =   "sdmmc3_dat0_pb7",
 128                                                 "sdmmc3_dat1_pb6",
 129                                                 "sdmmc3_dat2_pb5",
 130                                                 "sdmmc3_dat3_pb4",
 131                                                 "sdmmc3_dat4_pd1",
 132                                                 "sdmmc3_dat5_pd0",
 133                                                 "sdmmc3_dat6_pd3",
 134                                                 "sdmmc3_dat7_pd4";
 135                                 nvidia,function = "sdmmc3";
 136                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 137                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 138                         };
 139                         /* Apalis MMC1_CD# */
 140                         pv3 {
 141                                 nvidia,pins = "pv3";
 142                                 nvidia,function = "rsvd2";
 143                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 144                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 145                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 146                         };
 147
 148                         /* Apalis PWM1 */
 149                         gpio_pu6 {
 150                                 nvidia,pins =   "gpio_pu6";
 151                                 nvidia,function = "pwm3";
 152                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 153                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 154                         };
 155
 156                         /* Apalis PWM2 */
 157                         gpio_pu5 {
 158                                 nvidia,pins =   "gpio_pu5";
 159                                 nvidia,function = "pwm2";
 160                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 161                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 162                         };
 163
 164                         /* Apalis PWM3 */
 165                         gpio_pu4 {
 166                                 nvidia,pins =   "gpio_pu4";
 167                                 nvidia,function = "pwm1";
 168                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 169                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 170                         };
 171
 172                         /* Apalis PWM4 */
 173                         gpio_pu3 {
 174                                 nvidia,pins =   "gpio_pu3";
 175                                 nvidia,function = "pwm0";
 176                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 177                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 178                         };
 179
 180                         /* Apalis RESET_MOCI# */
 181                         gmi_rst_n_pi4 {
 182                                 nvidia,pins = "gmi_rst_n_pi4";
 183                                 nvidia,function = "gmi";
 184                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 185                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 186                         };
 187
 188                         /* Apalis SD1 */
 189                         sdmmc1_clk_pz0 {
 190                                 nvidia,pins = "sdmmc1_clk_pz0";
 191                                 nvidia,function = "sdmmc1";
 192                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 193                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 194                         };
 195                         sdmmc1_cmd_pz1 {
 196                                 nvidia,pins =   "sdmmc1_cmd_pz1",
 197                                                 "sdmmc1_dat0_py7",
 198                                                 "sdmmc1_dat1_py6",
 199                                                 "sdmmc1_dat2_py5",
 200                                                 "sdmmc1_dat3_py4";
 201                                 nvidia,function = "sdmmc1";
 202                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 203                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 204                         };
 205                         /* Apalis SD1_CD# */
 206                         clk2_req_pcc5 {
 207                                 nvidia,pins = "clk2_req_pcc5";
 208                                 nvidia,function = "rsvd2";
 209                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 210                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 211                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 212                         };
 213
 214                         /* Apalis SPI1 */
 215                         spi1_sck_px5 {
 216                                 nvidia,pins =   "spi1_sck_px5",
 217                                                 "spi1_mosi_px4",
 218                                                 "spi1_miso_px7",
 219                                                 "spi1_cs0_n_px6";
 220                                 nvidia,function = "spi1";
 221                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 222                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 223                         };
 224
 225                         /* Apalis SPI2 */
 226                         lcd_sck_pz4 {
 227                                 nvidia,pins =   "lcd_sck_pz4",
 228                                                 "lcd_sdout_pn5",
 229                                                 "lcd_sdin_pz2",
 230                                                 "lcd_cs0_n_pn4";
 231                                 nvidia,function = "spi5";
 232                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 233                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 234                         };
 235
 236                         /* Apalis UART1 */
 237                         ulpi_data0 {
 238                                 nvidia,pins =   "ulpi_data0_po1",
 239                                                 "ulpi_data1_po2",
 240                                                 "ulpi_data2_po3",
 241                                                 "ulpi_data3_po4",
 242                                                 "ulpi_data4_po5",
 243                                                 "ulpi_data5_po6",
 244                                                 "ulpi_data6_po7",
 245                                                 "ulpi_data7_po0";
 246                                 nvidia,function = "uarta";
 247                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 248                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 249                         };
 250
 251                         /* Apalis UART2 */
 252                         ulpi_clk_py0 {
 253                                 nvidia,pins =   "ulpi_clk_py0",
 254                                                 "ulpi_dir_py1",
 255                                                 "ulpi_nxt_py2",
 256                                                 "ulpi_stp_py3";
 257                                 nvidia,function = "uartd";
 258                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 259                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 260                         };
 261
 262                         /* Apalis UART3 */
 263                         uart2_rxd_pc3 {
 264                                 nvidia,pins =   "uart2_rxd_pc3",
 265                                                 "uart2_txd_pc2";
 266                                 nvidia,function = "uartb";
 267                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 268                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 269                         };
 270
 271                         /* Apalis UART4 */
 272                         uart3_rxd_pw7 {
 273                                 nvidia,pins =   "uart3_rxd_pw7",
 274                                                 "uart3_txd_pw6";
 275                                 nvidia,function = "uartc";
 276                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 277                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 278                         };
 279
 280                         /* Apalis USBO1_EN */
 281                         gen2_i2c_scl_pt5 {
 282                                 nvidia,pins = "gen2_i2c_scl_pt5";
 283                                 nvidia,function = "rsvd4";
 284                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 285                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 286                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 287                         };
 288
 289                         /* Apalis USBO1_OC# */
 290                         gen2_i2c_sda_pt6 {
 291                                 nvidia,pins = "gen2_i2c_sda_pt6";
 292                                 nvidia,function = "rsvd4";
 293                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 294                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 295                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 296                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 297                         };
 298
 299                         /* Apalis WAKE1_MICO */
 300                         pv1 {
 301                                 nvidia,pins = "pv1";
 302                                 nvidia,function = "rsvd1";
 303                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 304                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 305                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 306                         };
 307
 308                         /* eMMC (On-module) */
 309                         sdmmc4_clk_pcc4 {
 310                                 nvidia,pins =   "sdmmc4_clk_pcc4",
 311                                                 "sdmmc4_rst_n_pcc3";
 312                                 nvidia,function = "sdmmc4";
 313                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 314                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 315                         };
 316                         sdmmc4_dat0_paa0 {
 317                                 nvidia,pins =   "sdmmc4_dat0_paa0",
 318                                                 "sdmmc4_dat1_paa1",
 319                                                 "sdmmc4_dat2_paa2",
 320                                                 "sdmmc4_dat3_paa3",
 321                                                 "sdmmc4_dat4_paa4",
 322                                                 "sdmmc4_dat5_paa5",
 323                                                 "sdmmc4_dat6_paa6",
 324                                                 "sdmmc4_dat7_paa7";
 325                                 nvidia,function = "sdmmc4";
 326                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 327                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 328                         };
 329
 330                         /* LVDS Transceiver Configuration */
 331                         pbb0 {
 332                                 nvidia,pins =   "pbb0",
 333                                                 "pbb7",
 334                                                 "pcc1",
 335                                                 "pcc2";
 336                                 nvidia,function = "rsvd2";
 337                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 338                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 339                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 340                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 341                         };
 342                         pbb3 {
 343                                 nvidia,pins =   "pbb3",
 344                                                 "pbb4",
 345                                                 "pbb5",
 346                                                 "pbb6";
 347                                 nvidia,function = "displayb";
 348                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 349                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 350                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 351                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 352                         };
 353
 354                         /* Power I2C (On-module) */
 355                         pwr_i2c_scl_pz6 {
 356                                 nvidia,pins = "pwr_i2c_scl_pz6",
 357                                               "pwr_i2c_sda_pz7";
 358                                 nvidia,function = "i2cpwr";
 359                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 360                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 361                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 362                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 363                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 364                         };
 365
 366                         /*
 367                          * THERMD_ALERT#, unlatched I2C address pin of LM95245
 368                          * temperature sensor therefore requires disabling for
 369                          * now
 370                          */
 371                         lcd_dc1_pd2 {
 372                                 nvidia,pins = "lcd_dc1_pd2";
 373                                 nvidia,function = "rsvd3";
 374                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 375                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 376                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 377                         };
 378
 379                         /* TOUCH_PEN_INT# */
 380                         pv0 {
 381                                 nvidia,pins = "pv0";
 382                                 nvidia,function = "rsvd1";
 383                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 384                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 385                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 386                         };
 387                 };
 388         };
 389
 390         hdmiddc: i2c@7000c700 {
 391                 clock-frequency = <100000>;
 392         };
 393
 394         /*
 395          * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 396          * touch screen controller
 397          */
 398         i2c@7000d000 {
 399                 status = "okay";
 400                 clock-frequency = <100000>;
 401
 402                 pmic: tps65911@2d {
 403                         compatible = "ti,tps65911";
 404                         reg = <0x2d>;
 405
 406                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 407                         #interrupt-cells = <2>;
 408                         interrupt-controller;
 409
 410                         ti,system-power-controller;
 411
 412                         #gpio-cells = <2>;
 413                         gpio-controller;
 414
 415                         vcc1-supply = <&sys_3v3_reg>;
 416                         vcc2-supply = <&sys_3v3_reg>;
 417                         vcc3-supply = <&vio_reg>;
 418                         vcc4-supply = <&sys_3v3_reg>;
 419                         vcc5-supply = <&sys_3v3_reg>;
 420                         vcc6-supply = <&vio_reg>;
 421                         vcc7-supply = <&sys_5v0_reg>;
 422                         vccio-supply = <&sys_3v3_reg>;
 423
 424                         regulators {
 425                                 /* SW1: +V1.35_VDDIO_DDR */
 426                                 vdd1_reg: vdd1 {
 427                                         regulator-name = "vddio_ddr_1v35";
 428                                         regulator-min-microvolt = <1350000>;
 429                                         regulator-max-microvolt = <1350000>;
 430                                         regulator-always-on;
 431                                 };
 432
 433                                 /* SW2: +V1.05 */
 434                                 vdd2_reg: vdd2 {
 435                                         regulator-name =
 436                                                 "vdd_pexa,vdd_pexb,vdd_sata";
 437                                         regulator-min-microvolt = <1050000>;
 438                                         regulator-max-microvolt = <1050000>;
 439                                 };
 440
 441                                 /* SW CTRL: +V1.0_VDD_CPU */
 442                                 vddctrl_reg: vddctrl {
 443                                         regulator-name = "vdd_cpu,vdd_sys";
 444                                         regulator-min-microvolt = <1150000>;
 445                                         regulator-max-microvolt = <1150000>;
 446                                         regulator-always-on;
 447                                 };
 448
 449                                 /* SWIO: +V1.8 */
 450                                 vio_reg: vio {
 451                                         regulator-name = "vdd_1v8_gen";
 452                                         regulator-min-microvolt = <1800000>;
 453                                         regulator-max-microvolt = <1800000>;
 454                                         regulator-always-on;
 455                                 };
 456
 457                                 /* LDO1: unused */
 458
 459                                 /*
 460                                  * EN_+V3.3 switching via FET:
 461                                  * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
 462                                  * see also v3_3 fixed supply
 463                                  */
 464                                 ldo2_reg: ldo2 {
 465                                         regulator-name = "en_3v3";
 466                                         regulator-min-microvolt = <3300000>;
 467                                         regulator-max-microvolt = <3300000>;
 468                                         regulator-always-on;
 469                                 };
 470
 471                                 /* +V1.2_CSI */
 472                                 ldo3_reg: ldo3 {
 473                                         regulator-name =
 474                                                 "avdd_dsi_csi,pwrdet_mipi";
 475                                         regulator-min-microvolt = <1200000>;
 476                                         regulator-max-microvolt = <1200000>;
 477                                 };
 478
 479                                 /* +V1.2_VDD_RTC */
 480                                 ldo4_reg: ldo4 {
 481                                         regulator-name = "vdd_rtc";
 482                                         regulator-min-microvolt = <1200000>;
 483                                         regulator-max-microvolt = <1200000>;
 484                                         regulator-always-on;
 485                                 };
 486
 487                                 /*
 488                                  * +V2.8_AVDD_VDAC:
 489                                  * only required for analog RGB
 490                                  */
 491                                 ldo5_reg: ldo5 {
 492                                         regulator-name = "avdd_vdac";
 493                                         regulator-min-microvolt = <2800000>;
 494                                         regulator-max-microvolt = <2800000>;
 495                                         regulator-always-on;
 496                                 };
 497
 498                                 /*
 499                                  * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
 500                                  * but LDO6 can't set voltage in 50mV
 501                                  * granularity
 502                                  */
 503                                 ldo6_reg: ldo6 {
 504                                         regulator-name = "avdd_plle";
 505                                         regulator-min-microvolt = <1100000>;
 506                                         regulator-max-microvolt = <1100000>;
 507                                 };
 508
 509                                 /* +V1.2_AVDD_PLL */
 510                                 ldo7_reg: ldo7 {
 511                                         regulator-name = "avdd_pll";
 512                                         regulator-min-microvolt = <1200000>;
 513                                         regulator-max-microvolt = <1200000>;
 514                                         regulator-always-on;
 515                                 };
 516
 517                                 /* +V1.0_VDD_DDR_HS */
 518                                 ldo8_reg: ldo8 {
 519                                         regulator-name = "vdd_ddr_hs";
 520                                         regulator-min-microvolt = <1000000>;
 521                                         regulator-max-microvolt = <1000000>;
 522                                         regulator-always-on;
 523                                 };
 524                         };
 525                 };
 526
 527                 /* STMPE811 touch screen controller */
 528                 stmpe811@41 {
 529                         compatible = "st,stmpe811";
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         reg = <0x41>;
 533                         interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
 534                         interrupt-parent = <&gpio>;
 535                         interrupt-controller;
 536                         id = <0>;
 537                         blocks = <0x5>;
 538                         irq-trigger = <0x1>;
 539
 540                         stmpe_touchscreen {
 541                                 compatible = "st,stmpe-ts";
 542                                 reg = <0>;
 543                                 /* 3.25 MHz ADC clock speed */
 544                                 st,adc-freq = <1>;
 545                                 /* 8 sample average control */
 546                                 st,ave-ctrl = <3>;
 547                                 /* 7 length fractional part in z */
 548                                 st,fraction-z = <7>;
 549                                 /*
 550                                  * 50 mA typical 80 mA max touchscreen drivers
 551                                  * current limit value
 552                                  */
 553                                 st,i-drive = <1>;
 554                                 /* 12-bit ADC */
 555                                 st,mod-12b = <1>;
 556                                 /* internal ADC reference */
 557                                 st,ref-sel = <0>;
 558                                 /* ADC converstion time: 80 clocks */
 559                                 st,sample-time = <4>;
 560                                 /* 1 ms panel driver settling time */
 561                                 st,settling = <3>;
 562                                 /* 5 ms touch detect interrupt delay */
 563                                 st,touch-det-delay = <5>;
 564                         };
 565                 };
 566
 567                 /*
 568                  * LM95245 temperature sensor
 569                  * Note: OVERT_N directly connected to PMIC PWRDN
 570                  */
 571                 temp-sensor@4c {
 572                         compatible = "national,lm95245";
 573                         reg = <0x4c>;
 574                 };
 575
 576                 /* SW: +V1.2_VDD_CORE */
 577                 tps62362@60 {
 578                         compatible = "ti,tps62362";
 579                         reg = <0x60>;
 580
 581                         regulator-name = "tps62362-vout";
 582                         regulator-min-microvolt = <900000>;
 583                         regulator-max-microvolt = <1400000>;
 584                         regulator-boot-on;
 585                         regulator-always-on;
 586                         ti,vsel0-state-low;
 587                         /* VSEL1: EN_CORE_DVFS_N low for DVFS */
 588                         ti,vsel1-state-low;
 589                 };
 590         };
 591
 592         /* SPI4: CAN2 */
 593         spi@7000da00 {
 594                 status = "okay";
 595                 spi-max-frequency = <10000000>;
 596
 597                 can@1 {
 598                         compatible = "microchip,mcp2515";
 599                         reg = <1>;
 600                         clocks = <&clk16m>;
 601                         interrupt-parent = <&gpio>;
 602                         interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
 603                         spi-max-frequency = <10000000>;
 604                 };
 605         };
 606
 607         /* SPI6: CAN1 */
 608         spi@7000de00 {
 609                 status = "okay";
 610                 spi-max-frequency = <10000000>;
 611
 612                 can@0 {
 613                         compatible = "microchip,mcp2515";
 614                         reg = <0>;
 615                         clocks = <&clk16m>;
 616                         interrupt-parent = <&gpio>;
 617                         interrupts = <TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
 618                         spi-max-frequency = <10000000>;
 619                 };
 620         };
 621
 622         pmc@7000e400 {
 623                 nvidia,invert-interrupt;
 624                 nvidia,suspend-mode = <1>;
 625                 nvidia,cpu-pwr-good-time = <5000>;
 626                 nvidia,cpu-pwr-off-time = <5000>;
 627                 nvidia,core-pwr-good-time = <3845 3845>;
 628                 nvidia,core-pwr-off-time = <0>;
 629                 nvidia,core-power-req-active-high;
 630                 nvidia,sys-clock-req-active-high;
 631         };
 632
 633         sdhci@78000600 {
 634                 status = "okay";
 635                 bus-width = <8>;
 636                 non-removable;
 637         };
 638
 639         clocks {
 640                 compatible = "simple-bus";
 641                 #address-cells = <1>;
 642                 #size-cells = <0>;
 643
 644                 clk32k_in: clk@0 {
 645                         compatible = "fixed-clock";
 646                         reg=<0>;
 647                         #clock-cells = <0>;
 648                         clock-frequency = <32768>;
 649                 };
 650                 clk16m: clk@1 {
 651                         compatible = "fixed-clock";
 652                         reg=<1>;
 653                         #clock-cells = <0>;
 654                         clock-frequency = <16000000>;
 655                         clock-output-names = "clk16m";
 656                 };
 657         };
 658
 659         regulators {
 660                 compatible = "simple-bus";
 661                 #address-cells = <1>;
 662                 #size-cells = <0>;
 663
 664                 sys_3v3_reg: regulator@100 {
 665                         compatible = "regulator-fixed";
 666                         reg = <100>;
 667                         regulator-name = "3v3";
 668                         regulator-min-microvolt = <3300000>;
 669                         regulator-max-microvolt = <3300000>;
 670                         regulator-always-on;
 671                 };
 672         };
 673 };