1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
14 compatible = "nvidia,tegra124";
15 interrupt-parent = <&lic>;
20 device_type = "memory";
21 reg = <0x0 0x80000000 0x0 0x0>;
25 compatible = "nvidia,tegra124-pcie";
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 reg-names = "pads", "afi", "cs";
31 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
32 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
33 interrupt-names = "intr", "msi";
35 #interrupt-cells = <1>;
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
49 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
50 <&tegra_car TEGRA124_CLK_AFI>,
51 <&tegra_car TEGRA124_CLK_PLL_E>,
52 <&tegra_car TEGRA124_CLK_CML0>;
53 clock-names = "pex", "afi", "pll_e", "cml";
54 resets = <&tegra_car 70>,
57 reset-names = "pex", "afi", "pcie_x";
62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
63 reg = <0x000800 0 0 0 0>;
64 bus-range = <0x00 0xff>;
71 nvidia,num-lanes = <2>;
76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
77 reg = <0x001000 0 0 0 0>;
78 bus-range = <0x00 0xff>;
85 nvidia,num-lanes = <1>;
90 compatible = "nvidia,tegra124-host1x";
91 reg = <0x0 0x50000000 0x0 0x00034000>;
92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
94 interrupt-names = "syncpt", "host1x";
95 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
96 clock-names = "host1x";
97 resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>;
98 reset-names = "host1x", "mc";
99 iommus = <&mc TEGRA_SWGROUP_HC>;
101 #address-cells = <2>;
104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
107 compatible = "nvidia,tegra124-dc";
108 reg = <0x0 0x54200000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car TEGRA124_CLK_DISP1>;
112 resets = <&tegra_car 27>;
115 iommus = <&mc TEGRA_SWGROUP_DC>;
119 interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>,
120 <&mc TEGRA124_MC_DISPLAY0B &emc>,
121 <&mc TEGRA124_MC_DISPLAY0C &emc>,
122 <&mc TEGRA124_MC_DISPLAYHC &emc>,
123 <&mc TEGRA124_MC_DISPLAYD &emc>,
124 <&mc TEGRA124_MC_DISPLAYT &emc>;
125 interconnect-names = "wina",
134 compatible = "nvidia,tegra124-dc";
135 reg = <0x0 0x54240000 0x0 0x00040000>;
136 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&tegra_car TEGRA124_CLK_DISP2>;
139 resets = <&tegra_car 26>;
142 iommus = <&mc TEGRA_SWGROUP_DCB>;
146 interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>,
147 <&mc TEGRA124_MC_DISPLAY0BB &emc>,
148 <&mc TEGRA124_MC_DISPLAY0CB &emc>,
149 <&mc TEGRA124_MC_DISPLAYHCB &emc>;
150 interconnect-names = "wina",
156 hdmi: hdmi@54280000 {
157 compatible = "nvidia,tegra124-hdmi";
158 reg = <0x0 0x54280000 0x0 0x00040000>;
159 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
161 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
162 clock-names = "hdmi", "parent";
163 resets = <&tegra_car 51>;
164 reset-names = "hdmi";
169 compatible = "nvidia,tegra124-vic";
170 reg = <0x0 0x54340000 0x0 0x00040000>;
171 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&tegra_car TEGRA124_CLK_VIC03>;
174 resets = <&tegra_car 178>;
177 iommus = <&mc TEGRA_SWGROUP_VIC>;
181 compatible = "nvidia,tegra124-sor";
182 reg = <0x0 0x54540000 0x0 0x00040000>;
183 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
185 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
186 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
187 <&tegra_car TEGRA124_CLK_PLL_DP>,
188 <&tegra_car TEGRA124_CLK_CLK_M>;
189 clock-names = "sor", "out", "parent", "dp", "safe";
190 resets = <&tegra_car 182>;
195 dpaux: dpaux@545c0000 {
196 compatible = "nvidia,tegra124-dpaux";
197 reg = <0x0 0x545c0000 0x0 0x00040000>;
198 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
200 <&tegra_car TEGRA124_CLK_PLL_DP>;
201 clock-names = "dpaux", "parent";
202 resets = <&tegra_car 181>;
203 reset-names = "dpaux";
207 #address-cells = <1>;
213 gic: interrupt-controller@50041000 {
214 compatible = "arm,cortex-a15-gic";
215 #interrupt-cells = <3>;
216 interrupt-controller;
217 reg = <0x0 0x50041000 0x0 0x1000>,
218 <0x0 0x50042000 0x0 0x1000>,
219 <0x0 0x50044000 0x0 0x2000>,
220 <0x0 0x50046000 0x0 0x2000>;
221 interrupts = <GIC_PPI 9
222 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
223 interrupt-parent = <&gic>;
227 compatible = "nvidia,gk20a";
228 reg = <0x0 0x57000000 0x0 0x01000000>,
229 <0x0 0x58000000 0x0 0x01000000>;
230 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
232 interrupt-names = "stall", "nonstall";
233 clocks = <&tegra_car TEGRA124_CLK_GPU>,
234 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
235 clock-names = "gpu", "pwr";
236 resets = <&tegra_car 184>;
239 iommus = <&mc TEGRA_SWGROUP_GPU>;
244 lic: interrupt-controller@60004000 {
245 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
246 reg = <0x0 0x60004000 0x0 0x100>,
247 <0x0 0x60004100 0x0 0x100>,
248 <0x0 0x60004200 0x0 0x100>,
249 <0x0 0x60004300 0x0 0x100>,
250 <0x0 0x60004400 0x0 0x100>;
251 interrupt-controller;
252 #interrupt-cells = <3>;
253 interrupt-parent = <&gic>;
257 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
258 reg = <0x0 0x60005000 0x0 0x400>;
259 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
268 tegra_car: clock@60006000 {
269 compatible = "nvidia,tegra124-car";
270 reg = <0x0 0x60006000 0x0 0x1000>;
273 nvidia,external-memory-controller = <&emc>;
276 flow-controller@60007000 {
277 compatible = "nvidia,tegra124-flowctrl";
278 reg = <0x0 0x60007000 0x0 0x1000>;
281 actmon: actmon@6000c800 {
282 compatible = "nvidia,tegra124-actmon";
283 reg = <0x0 0x6000c800 0x0 0x400>;
284 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
286 <&tegra_car TEGRA124_CLK_EMC>;
287 clock-names = "actmon", "emc";
288 resets = <&tegra_car 119>;
289 reset-names = "actmon";
290 operating-points-v2 = <&emc_bw_dfs_opp_table>;
291 interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
292 interconnect-names = "cpu-read";
293 #cooling-cells = <2>;
296 gpio: gpio@6000d000 {
297 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
298 reg = <0x0 0x6000d000 0x0 0x1000>;
299 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
309 #interrupt-cells = <2>;
310 interrupt-controller;
311 gpio-ranges = <&pinmux 0 0 251>;
314 apbdma: dma@60020000 {
315 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
316 reg = <0x0 0x60020000 0x0 0x1400>;
317 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
350 resets = <&tegra_car 34>;
356 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
357 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
358 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
361 pinmux: pinmux@70000868 {
362 compatible = "nvidia,tegra124-pinmux";
363 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
364 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
365 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
369 * There are two serial driver i.e. 8250 based simple serial
370 * driver and APB DMA based serial driver for higher baudrate
371 * and performace. To enable the 8250 based driver, the compatible
372 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
373 * the APB DMA based serial driver, the compatible is
374 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
376 uarta: serial@70006000 {
377 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
378 reg = <0x0 0x70006000 0x0 0x40>;
380 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
382 resets = <&tegra_car 6>;
383 reset-names = "serial";
384 dmas = <&apbdma 8>, <&apbdma 8>;
385 dma-names = "rx", "tx";
389 uartb: serial@70006040 {
390 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
391 reg = <0x0 0x70006040 0x0 0x40>;
393 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
395 resets = <&tegra_car 7>;
396 reset-names = "serial";
397 dmas = <&apbdma 9>, <&apbdma 9>;
398 dma-names = "rx", "tx";
402 uartc: serial@70006200 {
403 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
404 reg = <0x0 0x70006200 0x0 0x40>;
406 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
408 resets = <&tegra_car 55>;
409 reset-names = "serial";
410 dmas = <&apbdma 10>, <&apbdma 10>;
411 dma-names = "rx", "tx";
415 uartd: serial@70006300 {
416 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
417 reg = <0x0 0x70006300 0x0 0x40>;
419 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
421 resets = <&tegra_car 65>;
422 reset-names = "serial";
423 dmas = <&apbdma 19>, <&apbdma 19>;
424 dma-names = "rx", "tx";
429 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
430 reg = <0x0 0x7000a000 0x0 0x100>;
432 clocks = <&tegra_car TEGRA124_CLK_PWM>;
433 resets = <&tegra_car 17>;
439 compatible = "nvidia,tegra124-i2c";
440 reg = <0x0 0x7000c000 0x0 0x100>;
441 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
444 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
445 clock-names = "div-clk";
446 resets = <&tegra_car 12>;
448 dmas = <&apbdma 21>, <&apbdma 21>;
449 dma-names = "rx", "tx";
454 compatible = "nvidia,tegra124-i2c";
455 reg = <0x0 0x7000c400 0x0 0x100>;
456 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
457 #address-cells = <1>;
459 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
460 clock-names = "div-clk";
461 resets = <&tegra_car 54>;
463 dmas = <&apbdma 22>, <&apbdma 22>;
464 dma-names = "rx", "tx";
469 compatible = "nvidia,tegra124-i2c";
470 reg = <0x0 0x7000c500 0x0 0x100>;
471 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
472 #address-cells = <1>;
474 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
475 clock-names = "div-clk";
476 resets = <&tegra_car 67>;
478 dmas = <&apbdma 23>, <&apbdma 23>;
479 dma-names = "rx", "tx";
484 compatible = "nvidia,tegra124-i2c";
485 reg = <0x0 0x7000c700 0x0 0x100>;
486 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
487 #address-cells = <1>;
489 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
490 clock-names = "div-clk";
491 resets = <&tegra_car 103>;
493 dmas = <&apbdma 26>, <&apbdma 26>;
494 dma-names = "rx", "tx";
499 compatible = "nvidia,tegra124-i2c";
500 reg = <0x0 0x7000d000 0x0 0x100>;
501 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
502 #address-cells = <1>;
504 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
505 clock-names = "div-clk";
506 resets = <&tegra_car 47>;
508 dmas = <&apbdma 24>, <&apbdma 24>;
509 dma-names = "rx", "tx";
514 compatible = "nvidia,tegra124-i2c";
515 reg = <0x0 0x7000d100 0x0 0x100>;
516 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
519 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
520 clock-names = "div-clk";
521 resets = <&tegra_car 166>;
523 dmas = <&apbdma 30>, <&apbdma 30>;
524 dma-names = "rx", "tx";
529 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
530 reg = <0x0 0x7000d400 0x0 0x200>;
531 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
532 #address-cells = <1>;
534 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
536 resets = <&tegra_car 41>;
538 dmas = <&apbdma 15>, <&apbdma 15>;
539 dma-names = "rx", "tx";
544 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
545 reg = <0x0 0x7000d600 0x0 0x200>;
546 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <1>;
549 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
551 resets = <&tegra_car 44>;
553 dmas = <&apbdma 16>, <&apbdma 16>;
554 dma-names = "rx", "tx";
559 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
560 reg = <0x0 0x7000d800 0x0 0x200>;
561 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
562 #address-cells = <1>;
564 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
566 resets = <&tegra_car 46>;
568 dmas = <&apbdma 17>, <&apbdma 17>;
569 dma-names = "rx", "tx";
574 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
575 reg = <0x0 0x7000da00 0x0 0x200>;
576 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
579 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
581 resets = <&tegra_car 68>;
583 dmas = <&apbdma 18>, <&apbdma 18>;
584 dma-names = "rx", "tx";
589 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
590 reg = <0x0 0x7000dc00 0x0 0x200>;
591 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
592 #address-cells = <1>;
594 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
596 resets = <&tegra_car 104>;
598 dmas = <&apbdma 27>, <&apbdma 27>;
599 dma-names = "rx", "tx";
604 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
605 reg = <0x0 0x7000de00 0x0 0x200>;
606 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
607 #address-cells = <1>;
609 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
611 resets = <&tegra_car 105>;
613 dmas = <&apbdma 28>, <&apbdma 28>;
614 dma-names = "rx", "tx";
619 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
620 reg = <0x0 0x7000e000 0x0 0x100>;
621 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&tegra_car TEGRA124_CLK_RTC>;
625 tegra_pmc: pmc@7000e400 {
626 compatible = "nvidia,tegra124-pmc";
627 reg = <0x0 0x7000e400 0x0 0x400>;
628 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
629 clock-names = "pclk", "clk32k_in";
634 compatible = "nvidia,tegra124-efuse";
635 reg = <0x0 0x7000f800 0x0 0x400>;
636 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
637 clock-names = "fuse";
638 resets = <&tegra_car 39>;
639 reset-names = "fuse";
642 mc: memory-controller@70019000 {
643 compatible = "nvidia,tegra124-mc";
644 reg = <0x0 0x70019000 0x0 0x1000>;
645 clocks = <&tegra_car TEGRA124_CLK_MC>;
648 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
652 #interconnect-cells = <1>;
655 emc: external-memory-controller@7001b000 {
656 compatible = "nvidia,tegra124-emc";
657 reg = <0x0 0x7001b000 0x0 0x1000>;
658 clocks = <&tegra_car TEGRA124_CLK_EMC>;
661 nvidia,memory-controller = <&mc>;
662 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
664 #interconnect-cells = <0>;
668 compatible = "nvidia,tegra124-ahci";
669 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
670 <0x0 0x70020000 0x0 0x7000>; /* SATA */
671 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&tegra_car TEGRA124_CLK_SATA>,
673 <&tegra_car TEGRA124_CLK_SATA_OOB>;
674 clock-names = "sata", "sata-oob";
675 resets = <&tegra_car 124>,
678 reset-names = "sata", "sata-cold", "sata-oob";
683 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
684 reg = <0x0 0x70030000 0x0 0x10000>;
685 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&tegra_car TEGRA124_CLK_HDA>,
687 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
688 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
689 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
690 resets = <&tegra_car 125>, /* hda */
691 <&tegra_car 128>, /* hda2hdmi */
692 <&tegra_car 111>; /* hda2codec_2x */
693 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
698 compatible = "nvidia,tegra124-xusb";
699 reg = <0x0 0x70090000 0x0 0x8000>,
700 <0x0 0x70098000 0x0 0x1000>,
701 <0x0 0x70099000 0x0 0x1000>;
702 reg-names = "hcd", "fpci", "ipfs";
704 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
708 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
709 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
710 <&tegra_car TEGRA124_CLK_XUSB_SS>,
711 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
712 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
713 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
714 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
715 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
716 <&tegra_car TEGRA124_CLK_CLK_M>,
717 <&tegra_car TEGRA124_CLK_PLL_E>;
718 clock-names = "xusb_host", "xusb_host_src",
719 "xusb_falcon_src", "xusb_ss",
720 "xusb_ss_div2", "xusb_ss_src",
721 "xusb_hs_src", "xusb_fs_src",
722 "pll_u_480m", "clk_m", "pll_e";
723 resets = <&tegra_car 89>, <&tegra_car 156>,
725 reset-names = "xusb_host", "xusb_ss", "xusb_src";
727 nvidia,xusb-padctl = <&padctl>;
732 padctl: padctl@7009f000 {
733 compatible = "nvidia,tegra124-xusb-padctl";
734 reg = <0x0 0x7009f000 0x0 0x1000>;
735 resets = <&tegra_car 142>;
736 reset-names = "padctl";
866 compatible = "nvidia,tegra124-sdhci";
867 reg = <0x0 0x700b0000 0x0 0x200>;
868 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
870 clock-names = "sdhci";
871 resets = <&tegra_car 14>;
872 reset-names = "sdhci";
877 compatible = "nvidia,tegra124-sdhci";
878 reg = <0x0 0x700b0200 0x0 0x200>;
879 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
881 clock-names = "sdhci";
882 resets = <&tegra_car 9>;
883 reset-names = "sdhci";
888 compatible = "nvidia,tegra124-sdhci";
889 reg = <0x0 0x700b0400 0x0 0x200>;
890 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
892 clock-names = "sdhci";
893 resets = <&tegra_car 69>;
894 reset-names = "sdhci";
899 compatible = "nvidia,tegra124-sdhci";
900 reg = <0x0 0x700b0600 0x0 0x200>;
901 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
903 clock-names = "sdhci";
904 resets = <&tegra_car 15>;
905 reset-names = "sdhci";
910 compatible = "nvidia,tegra124-cec";
911 reg = <0x0 0x70015000 0x0 0x00001000>;
912 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&tegra_car TEGRA124_CLK_CEC>;
916 hdmi-phandle = <&hdmi>;
919 soctherm: thermal-sensor@700e2000 {
920 compatible = "nvidia,tegra124-soctherm";
921 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
922 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
923 reg-names = "soctherm-reg", "car-reg";
924 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
926 interrupt-names = "thermal", "edp";
927 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
928 <&tegra_car TEGRA124_CLK_SOC_THERM>;
929 clock-names = "tsensor", "soctherm";
930 resets = <&tegra_car 78>;
931 reset-names = "soctherm";
932 #thermal-sensor-cells = <1>;
935 throttle_heavy: heavy {
936 nvidia,priority = <100>;
937 nvidia,cpu-throt-percent = <85>;
938 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
940 #cooling-cells = <2>;
945 dfll: clock@70110000 {
946 compatible = "nvidia,tegra124-dfll";
947 reg = <0 0x70110000 0 0x100>, /* DFLL control */
948 <0 0x70110000 0 0x100>, /* I2C output control */
949 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
950 <0 0x70110200 0 0x100>; /* Look-up table RAM */
951 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
953 <&tegra_car TEGRA124_CLK_DFLL_REF>,
954 <&tegra_car TEGRA124_CLK_I2C5>;
955 clock-names = "soc", "ref", "i2c";
956 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
957 reset-names = "dvco";
959 clock-output-names = "dfllCPU_out";
960 nvidia,sample-rate = <12500>;
961 nvidia,droop-ctrl = <0x00000f00>;
962 nvidia,force-mode = <1>;
970 compatible = "nvidia,tegra124-ahub";
971 reg = <0x0 0x70300000 0x0 0x200>,
972 <0x0 0x70300800 0x0 0x800>,
973 <0x0 0x70300200 0x0 0x600>;
974 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
976 <&tegra_car TEGRA124_CLK_APBIF>;
977 clock-names = "d_audio", "apbif";
978 resets = <&tegra_car 106>, /* d_audio */
979 <&tegra_car 107>, /* apbif */
980 <&tegra_car 30>, /* i2s0 */
981 <&tegra_car 11>, /* i2s1 */
982 <&tegra_car 18>, /* i2s2 */
983 <&tegra_car 101>, /* i2s3 */
984 <&tegra_car 102>, /* i2s4 */
985 <&tegra_car 108>, /* dam0 */
986 <&tegra_car 109>, /* dam1 */
987 <&tegra_car 110>, /* dam2 */
988 <&tegra_car 10>, /* spdif */
989 <&tegra_car 153>, /* amx */
990 <&tegra_car 185>, /* amx1 */
991 <&tegra_car 154>, /* adx */
992 <&tegra_car 180>, /* adx1 */
993 <&tegra_car 186>, /* afc0 */
994 <&tegra_car 187>, /* afc1 */
995 <&tegra_car 188>, /* afc2 */
996 <&tegra_car 189>, /* afc3 */
997 <&tegra_car 190>, /* afc4 */
998 <&tegra_car 191>; /* afc5 */
999 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1000 "i2s3", "i2s4", "dam0", "dam1", "dam2",
1001 "spdif", "amx", "amx1", "adx", "adx1",
1002 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
1003 dmas = <&apbdma 1>, <&apbdma 1>,
1004 <&apbdma 2>, <&apbdma 2>,
1005 <&apbdma 3>, <&apbdma 3>,
1006 <&apbdma 4>, <&apbdma 4>,
1007 <&apbdma 6>, <&apbdma 6>,
1008 <&apbdma 7>, <&apbdma 7>,
1009 <&apbdma 12>, <&apbdma 12>,
1010 <&apbdma 13>, <&apbdma 13>,
1011 <&apbdma 14>, <&apbdma 14>,
1012 <&apbdma 29>, <&apbdma 29>;
1013 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1014 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
1015 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
1018 #address-cells = <2>;
1021 tegra_i2s0: i2s@70301000 {
1022 compatible = "nvidia,tegra124-i2s";
1023 reg = <0x0 0x70301000 0x0 0x100>;
1024 nvidia,ahub-cif-ids = <4 4>;
1025 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
1026 resets = <&tegra_car 30>;
1027 reset-names = "i2s";
1028 status = "disabled";
1031 tegra_i2s1: i2s@70301100 {
1032 compatible = "nvidia,tegra124-i2s";
1033 reg = <0x0 0x70301100 0x0 0x100>;
1034 nvidia,ahub-cif-ids = <5 5>;
1035 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1036 resets = <&tegra_car 11>;
1037 reset-names = "i2s";
1038 status = "disabled";
1041 tegra_i2s2: i2s@70301200 {
1042 compatible = "nvidia,tegra124-i2s";
1043 reg = <0x0 0x70301200 0x0 0x100>;
1044 nvidia,ahub-cif-ids = <6 6>;
1045 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1046 resets = <&tegra_car 18>;
1047 reset-names = "i2s";
1048 status = "disabled";
1051 tegra_i2s3: i2s@70301300 {
1052 compatible = "nvidia,tegra124-i2s";
1053 reg = <0x0 0x70301300 0x0 0x100>;
1054 nvidia,ahub-cif-ids = <7 7>;
1055 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1056 resets = <&tegra_car 101>;
1057 reset-names = "i2s";
1058 status = "disabled";
1061 tegra_i2s4: i2s@70301400 {
1062 compatible = "nvidia,tegra124-i2s";
1063 reg = <0x0 0x70301400 0x0 0x100>;
1064 nvidia,ahub-cif-ids = <8 8>;
1065 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1066 resets = <&tegra_car 102>;
1067 reset-names = "i2s";
1068 status = "disabled";
1073 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1074 reg = <0x0 0x7d000000 0x0 0x4000>;
1075 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1078 resets = <&tegra_car 22>;
1079 reset-names = "usb";
1080 nvidia,phy = <&phy1>;
1081 status = "disabled";
1084 phy1: usb-phy@7d000000 {
1085 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1086 reg = <0x0 0x7d000000 0x0 0x4000>,
1087 <0x0 0x7d000000 0x0 0x4000>;
1088 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1091 <&tegra_car TEGRA124_CLK_PLL_U>,
1092 <&tegra_car TEGRA124_CLK_USBD>;
1093 clock-names = "reg", "pll_u", "utmi-pads";
1094 resets = <&tegra_car 22>, <&tegra_car 22>;
1095 reset-names = "usb", "utmi-pads";
1097 nvidia,hssync-start-delay = <0>;
1098 nvidia,idle-wait-delay = <17>;
1099 nvidia,elastic-limit = <16>;
1100 nvidia,term-range-adj = <6>;
1101 nvidia,xcvr-setup = <9>;
1102 nvidia,xcvr-lsfslew = <0>;
1103 nvidia,xcvr-lsrslew = <3>;
1104 nvidia,hssquelch-level = <2>;
1105 nvidia,hsdiscon-level = <5>;
1106 nvidia,xcvr-hsslew = <12>;
1107 nvidia,has-utmi-pad-registers;
1108 nvidia,pmc = <&tegra_pmc 0>;
1109 status = "disabled";
1113 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1114 reg = <0x0 0x7d004000 0x0 0x4000>;
1115 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1117 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1118 resets = <&tegra_car 58>;
1119 reset-names = "usb";
1120 nvidia,phy = <&phy2>;
1121 status = "disabled";
1124 phy2: usb-phy@7d004000 {
1125 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1126 reg = <0x0 0x7d004000 0x0 0x4000>,
1127 <0x0 0x7d000000 0x0 0x4000>;
1128 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1131 <&tegra_car TEGRA124_CLK_PLL_U>,
1132 <&tegra_car TEGRA124_CLK_USBD>;
1133 clock-names = "reg", "pll_u", "utmi-pads";
1134 resets = <&tegra_car 58>, <&tegra_car 22>;
1135 reset-names = "usb", "utmi-pads";
1137 nvidia,hssync-start-delay = <0>;
1138 nvidia,idle-wait-delay = <17>;
1139 nvidia,elastic-limit = <16>;
1140 nvidia,term-range-adj = <6>;
1141 nvidia,xcvr-setup = <9>;
1142 nvidia,xcvr-lsfslew = <0>;
1143 nvidia,xcvr-lsrslew = <3>;
1144 nvidia,hssquelch-level = <2>;
1145 nvidia,hsdiscon-level = <5>;
1146 nvidia,xcvr-hsslew = <12>;
1147 nvidia,pmc = <&tegra_pmc 1>;
1148 status = "disabled";
1152 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1153 reg = <0x0 0x7d008000 0x0 0x4000>;
1154 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1157 resets = <&tegra_car 59>;
1158 reset-names = "usb";
1159 nvidia,phy = <&phy3>;
1160 status = "disabled";
1163 phy3: usb-phy@7d008000 {
1164 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1165 reg = <0x0 0x7d008000 0x0 0x4000>,
1166 <0x0 0x7d000000 0x0 0x4000>;
1167 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1170 <&tegra_car TEGRA124_CLK_PLL_U>,
1171 <&tegra_car TEGRA124_CLK_USBD>;
1172 clock-names = "reg", "pll_u", "utmi-pads";
1173 resets = <&tegra_car 59>, <&tegra_car 22>;
1174 reset-names = "usb", "utmi-pads";
1176 nvidia,hssync-start-delay = <0>;
1177 nvidia,idle-wait-delay = <17>;
1178 nvidia,elastic-limit = <16>;
1179 nvidia,term-range-adj = <6>;
1180 nvidia,xcvr-setup = <9>;
1181 nvidia,xcvr-lsfslew = <0>;
1182 nvidia,xcvr-lsrslew = <3>;
1183 nvidia,hssquelch-level = <2>;
1184 nvidia,hsdiscon-level = <5>;
1185 nvidia,xcvr-hsslew = <12>;
1186 nvidia,pmc = <&tegra_pmc 2>;
1187 status = "disabled";
1191 #address-cells = <1>;
1195 device_type = "cpu";
1196 compatible = "arm,cortex-a15";
1199 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1200 <&tegra_car TEGRA124_CLK_CCLK_LP>,
1201 <&tegra_car TEGRA124_CLK_PLL_X>,
1202 <&tegra_car TEGRA124_CLK_PLL_P>,
1204 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1205 /* FIXME: what's the actual transition time? */
1206 clock-latency = <300000>;
1210 device_type = "cpu";
1211 compatible = "arm,cortex-a15";
1216 device_type = "cpu";
1217 compatible = "arm,cortex-a15";
1222 device_type = "cpu";
1223 compatible = "arm,cortex-a15";
1229 compatible = "arm,cortex-a15-pmu";
1230 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1234 interrupt-affinity = <&{/cpus/cpu@0}>,
1242 polling-delay-passive = <1000>;
1243 polling-delay = <1000>;
1246 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1250 temperature = <103000>;
1254 cpu_throttle_trip: throttle-trip {
1255 temperature = <100000>;
1256 hysteresis = <1000>;
1263 trip = <&cpu_throttle_trip>;
1264 cooling-device = <&throttle_heavy 1 1>;
1270 polling-delay-passive = <1000>;
1271 polling-delay = <1000>;
1274 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1278 temperature = <103000>;
1283 temperature = <99000>;
1284 hysteresis = <1000>;
1291 * There are currently no cooling maps,
1292 * because there are no cooling devices.
1298 polling-delay-passive = <1000>;
1299 polling-delay = <1000>;
1302 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1306 temperature = <101000>;
1310 gpu_throttle_trip: throttle-trip {
1311 temperature = <99000>;
1312 hysteresis = <1000>;
1319 trip = <&gpu_throttle_trip>;
1320 cooling-device = <&throttle_heavy 1 1>;
1326 polling-delay-passive = <1000>;
1327 polling-delay = <1000>;
1330 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1333 pllx-shutdown-trip {
1334 temperature = <103000>;
1338 pllx-throttle-trip {
1339 temperature = <99000>;
1340 hysteresis = <1000>;
1347 * There are currently no cooling maps,
1348 * because there are no cooling devices.
1355 compatible = "arm,armv7-timer";
1356 interrupts = <GIC_PPI 13
1357 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1359 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1361 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1363 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1364 interrupt-parent = <&gic>;