2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/sun8i-h3-ccu.h>
44 #include <dt-bindings/clock/sun8i-r-ccu.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/reset/sun8i-h3-ccu.h>
47 #include <dt-bindings/reset/sun8i-r-ccu.h>
50 interrupt-parent = <&gic>;
61 compatible = "fixed-clock";
62 clock-frequency = <24000000>;
63 clock-output-names = "osc24M";
68 compatible = "fixed-clock";
69 clock-frequency = <32768>;
70 clock-output-names = "osc32k";
73 iosc: internal-osc-clk {
75 compatible = "fixed-clock";
76 clock-frequency = <16000000>;
77 clock-accuracy = <300000000>;
78 clock-output-names = "iosc";
83 compatible = "simple-bus";
88 syscon: syscon@1c00000 {
89 compatible = "allwinner,sun8i-h3-system-controller",
91 reg = <0x01c00000 0x1000>;
94 dma: dma-controller@1c02000 {
95 compatible = "allwinner,sun8i-h3-dma";
96 reg = <0x01c02000 0x1000>;
97 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&ccu CLK_BUS_DMA>;
99 resets = <&ccu RST_BUS_DMA>;
104 /* compatible and clocks are in per SoC .dtsi file */
105 reg = <0x01c0f000 0x1000>;
106 resets = <&ccu RST_BUS_MMC0>;
108 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
110 #address-cells = <1>;
115 /* compatible and clocks are in per SoC .dtsi file */
116 reg = <0x01c10000 0x1000>;
117 resets = <&ccu RST_BUS_MMC1>;
119 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
121 #address-cells = <1>;
126 /* compatible and clocks are in per SoC .dtsi file */
127 reg = <0x01c11000 0x1000>;
128 resets = <&ccu RST_BUS_MMC2>;
130 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
132 #address-cells = <1>;
136 usb_otg: usb@1c19000 {
137 compatible = "allwinner,sun8i-h3-musb";
138 reg = <0x01c19000 0x400>;
139 clocks = <&ccu CLK_BUS_OTG>;
140 resets = <&ccu RST_BUS_OTG>;
141 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
142 interrupt-names = "mc";
145 extcon = <&usbphy 0>;
149 usbphy: phy@1c19400 {
150 compatible = "allwinner,sun8i-h3-usb-phy";
151 reg = <0x01c19400 0x2c>,
156 reg-names = "phy_ctrl",
161 clocks = <&ccu CLK_USB_PHY0>,
165 clock-names = "usb0_phy",
169 resets = <&ccu RST_USB_PHY0>,
173 reset-names = "usb0_reset",
182 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
183 reg = <0x01c1a000 0x100>;
184 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
186 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
191 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
192 reg = <0x01c1a400 0x100>;
193 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
195 <&ccu CLK_USB_OHCI0>;
196 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
201 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
202 reg = <0x01c1b000 0x100>;
203 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
205 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
212 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
213 reg = <0x01c1b400 0x100>;
214 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
216 <&ccu CLK_USB_OHCI1>;
217 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
224 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
225 reg = <0x01c1c000 0x100>;
226 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
228 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
235 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
236 reg = <0x01c1c400 0x100>;
237 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
239 <&ccu CLK_USB_OHCI2>;
240 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
247 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
248 reg = <0x01c1d000 0x100>;
249 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
251 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
258 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
259 reg = <0x01c1d400 0x100>;
260 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
262 <&ccu CLK_USB_OHCI3>;
263 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
270 /* compatible is in per SoC .dtsi file */
271 reg = <0x01c20000 0x400>;
272 clocks = <&osc24M>, <&osc32k>;
273 clock-names = "hosc", "losc";
278 pio: pinctrl@1c20800 {
279 /* compatible is in per SoC .dtsi file */
280 reg = <0x01c20800 0x400>;
281 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
284 clock-names = "apb", "hosc", "losc";
287 interrupt-controller;
288 #interrupt-cells = <3>;
290 emac_rgmii_pins: emac0 {
291 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
292 "PD5", "PD7", "PD8", "PD9", "PD10",
293 "PD12", "PD13", "PD15", "PD16", "PD17";
295 drive-strength = <40>;
299 pins = "PA11", "PA12";
304 pins = "PA18", "PA19";
309 pins = "PE12", "PE13";
314 pins = "PF0", "PF1", "PF2", "PF3",
317 drive-strength = <30>;
321 mmc0_cd_pin: mmc0_cd_pin {
323 function = "gpio_in";
328 pins = "PG0", "PG1", "PG2", "PG3",
331 drive-strength = <30>;
335 mmc2_8bit_pins: mmc2_8bit {
336 pins = "PC5", "PC6", "PC8",
337 "PC9", "PC10", "PC11",
338 "PC12", "PC13", "PC14",
341 drive-strength = <30>;
345 spdif_tx_pins_a: spdif {
351 pins = "PC0", "PC1", "PC2", "PC3";
356 pins = "PA15", "PA16", "PA14", "PA13";
360 uart0_pins_a: uart0 {
370 uart1_rts_cts_pins: uart1_rts_cts {
381 pins = "PA13", "PA14";
385 uart3_rts_cts_pins: uart3_rts_cts {
386 pins = "PA15", "PA16";
392 compatible = "allwinner,sun4i-a10-timer";
393 reg = <0x01c20c00 0xa0>;
394 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
399 emac: ethernet@1c30000 {
400 compatible = "allwinner,sun8i-h3-emac";
402 reg = <0x01c30000 0x10000>;
403 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-names = "macirq";
405 resets = <&ccu RST_BUS_EMAC>;
406 reset-names = "stmmaceth";
407 clocks = <&ccu CLK_BUS_EMAC>;
408 clock-names = "stmmaceth";
409 #address-cells = <1>;
414 #address-cells = <1>;
416 compatible = "snps,dwmac-mdio";
420 compatible = "allwinner,sun8i-h3-mdio-mux";
421 #address-cells = <1>;
424 mdio-parent-bus = <&mdio>;
425 /* Only one MDIO is usable at the time */
426 internal_mdio: mdio@1 {
427 compatible = "allwinner,sun8i-h3-mdio-internal";
429 #address-cells = <1>;
432 int_mii_phy: ethernet-phy@1 {
433 compatible = "ethernet-phy-ieee802.3-c22";
435 clocks = <&ccu CLK_BUS_EPHY>;
436 resets = <&ccu RST_BUS_EPHY>;
440 external_mdio: mdio@2 {
442 #address-cells = <1>;
449 compatible = "allwinner,sun8i-h3-spi";
450 reg = <0x01c68000 0x1000>;
451 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
453 clock-names = "ahb", "mod";
454 dmas = <&dma 23>, <&dma 23>;
455 dma-names = "rx", "tx";
456 pinctrl-names = "default";
457 pinctrl-0 = <&spi0_pins>;
458 resets = <&ccu RST_BUS_SPI0>;
460 #address-cells = <1>;
465 compatible = "allwinner,sun8i-h3-spi";
466 reg = <0x01c69000 0x1000>;
467 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
469 clock-names = "ahb", "mod";
470 dmas = <&dma 24>, <&dma 24>;
471 dma-names = "rx", "tx";
472 pinctrl-names = "default";
473 pinctrl-0 = <&spi1_pins>;
474 resets = <&ccu RST_BUS_SPI1>;
476 #address-cells = <1>;
480 wdt0: watchdog@1c20ca0 {
481 compatible = "allwinner,sun6i-a31-wdt";
482 reg = <0x01c20ca0 0x20>;
483 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
486 spdif: spdif@1c21000 {
487 #sound-dai-cells = <0>;
488 compatible = "allwinner,sun8i-h3-spdif";
489 reg = <0x01c21000 0x400>;
490 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
492 resets = <&ccu RST_BUS_SPDIF>;
493 clock-names = "apb", "spdif";
500 compatible = "allwinner,sun8i-h3-pwm";
501 reg = <0x01c21400 0x8>;
508 #sound-dai-cells = <0>;
509 compatible = "allwinner,sun8i-h3-i2s";
510 reg = <0x01c22000 0x400>;
511 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
513 clock-names = "apb", "mod";
514 dmas = <&dma 3>, <&dma 3>;
515 resets = <&ccu RST_BUS_I2S0>;
516 dma-names = "rx", "tx";
521 #sound-dai-cells = <0>;
522 compatible = "allwinner,sun8i-h3-i2s";
523 reg = <0x01c22400 0x400>;
524 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
526 clock-names = "apb", "mod";
527 dmas = <&dma 4>, <&dma 4>;
528 resets = <&ccu RST_BUS_I2S1>;
529 dma-names = "rx", "tx";
533 codec: codec@1c22c00 {
534 #sound-dai-cells = <0>;
535 compatible = "allwinner,sun8i-h3-codec";
536 reg = <0x01c22c00 0x400>;
537 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
539 clock-names = "apb", "codec";
540 resets = <&ccu RST_BUS_CODEC>;
541 dmas = <&dma 15>, <&dma 15>;
542 dma-names = "rx", "tx";
543 allwinner,codec-analog-controls = <&codec_analog>;
547 uart0: serial@1c28000 {
548 compatible = "snps,dw-apb-uart";
549 reg = <0x01c28000 0x400>;
550 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&ccu CLK_BUS_UART0>;
554 resets = <&ccu RST_BUS_UART0>;
555 dmas = <&dma 6>, <&dma 6>;
556 dma-names = "rx", "tx";
560 uart1: serial@1c28400 {
561 compatible = "snps,dw-apb-uart";
562 reg = <0x01c28400 0x400>;
563 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&ccu CLK_BUS_UART1>;
567 resets = <&ccu RST_BUS_UART1>;
568 dmas = <&dma 7>, <&dma 7>;
569 dma-names = "rx", "tx";
573 uart2: serial@1c28800 {
574 compatible = "snps,dw-apb-uart";
575 reg = <0x01c28800 0x400>;
576 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&ccu CLK_BUS_UART2>;
580 resets = <&ccu RST_BUS_UART2>;
581 dmas = <&dma 8>, <&dma 8>;
582 dma-names = "rx", "tx";
586 uart3: serial@1c28c00 {
587 compatible = "snps,dw-apb-uart";
588 reg = <0x01c28c00 0x400>;
589 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&ccu CLK_BUS_UART3>;
593 resets = <&ccu RST_BUS_UART3>;
594 dmas = <&dma 9>, <&dma 9>;
595 dma-names = "rx", "tx";
600 compatible = "allwinner,sun6i-a31-i2c";
601 reg = <0x01c2ac00 0x400>;
602 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&ccu CLK_BUS_I2C0>;
604 resets = <&ccu RST_BUS_I2C0>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&i2c0_pins>;
608 #address-cells = <1>;
613 compatible = "allwinner,sun6i-a31-i2c";
614 reg = <0x01c2b000 0x400>;
615 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&ccu CLK_BUS_I2C1>;
617 resets = <&ccu RST_BUS_I2C1>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2c1_pins>;
621 #address-cells = <1>;
626 compatible = "allwinner,sun6i-a31-i2c";
627 reg = <0x01c2b400 0x400>;
628 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&ccu CLK_BUS_I2C2>;
630 resets = <&ccu RST_BUS_I2C2>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&i2c2_pins>;
634 #address-cells = <1>;
638 gic: interrupt-controller@1c81000 {
639 compatible = "arm,gic-400";
640 reg = <0x01c81000 0x1000>,
644 interrupt-controller;
645 #interrupt-cells = <3>;
646 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
650 compatible = "allwinner,sun6i-a31-rtc";
651 reg = <0x01f00000 0x54>;
652 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
656 r_ccu: clock@1f01400 {
657 compatible = "allwinner,sun8i-h3-r-ccu";
658 reg = <0x01f01400 0x100>;
659 clocks = <&osc24M>, <&osc32k>, <&iosc>,
661 clock-names = "hosc", "losc", "iosc", "pll-periph";
666 codec_analog: codec-analog@1f015c0 {
667 compatible = "allwinner,sun8i-h3-codec-analog";
668 reg = <0x01f015c0 0x4>;
672 compatible = "allwinner,sun5i-a13-ir";
673 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
674 clock-names = "apb", "ir";
675 resets = <&r_ccu RST_APB0_IR>;
676 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
677 reg = <0x01f02000 0x40>;
681 r_pio: pinctrl@1f02c00 {
682 compatible = "allwinner,sun8i-h3-r-pinctrl";
683 reg = <0x01f02c00 0x400>;
684 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
686 clock-names = "apb", "hosc", "losc";
689 interrupt-controller;
690 #interrupt-cells = <3>;
694 function = "s_cir_rx";