2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
54 interrupt-parent = <&gic>;
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 clock-accuracy = <50000>;
66 clock-output-names = "osc24M";
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
73 clock-accuracy = <20000>;
74 clock-output-names = "ext-osc32k";
83 compatible = "arm,cortex-a7";
89 compatible = "arm,cortex-a7";
95 compatible = "arm,cortex-a7";
101 compatible = "arm,cortex-a7";
108 compatible = "allwinner,sun8i-r40-display-engine";
109 allwinner,pipelines = <&mixer0>, <&mixer1>;
114 compatible = "simple-bus";
115 #address-cells = <1>;
119 display_clocks: clock@1000000 {
120 compatible = "allwinner,sun8i-r40-de2-clk",
121 "allwinner,sun8i-h3-de2-clk";
122 reg = <0x01000000 0x100000>;
123 clocks = <&ccu CLK_BUS_DE>,
127 resets = <&ccu RST_BUS_DE>;
132 mixer0: mixer@1100000 {
133 compatible = "allwinner,sun8i-r40-de2-mixer-0";
134 reg = <0x01100000 0x100000>;
135 clocks = <&display_clocks CLK_BUS_MIXER0>,
136 <&display_clocks CLK_MIXER0>;
139 resets = <&display_clocks RST_MIXER0>;
142 #address-cells = <1>;
147 mixer0_out_tcon_top: endpoint {
148 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
154 mixer1: mixer@1200000 {
155 compatible = "allwinner,sun8i-r40-de2-mixer-1";
156 reg = <0x01200000 0x100000>;
157 clocks = <&display_clocks CLK_BUS_MIXER1>,
158 <&display_clocks CLK_MIXER1>;
161 resets = <&display_clocks RST_WB>;
164 #address-cells = <1>;
169 mixer1_out_tcon_top: endpoint {
170 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
176 nmi_intc: interrupt-controller@1c00030 {
177 compatible = "allwinner,sun7i-a20-sc-nmi";
178 interrupt-controller;
179 #interrupt-cells = <2>;
180 reg = <0x01c00030 0x0c>;
181 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
185 compatible = "allwinner,sun8i-r40-spi",
186 "allwinner,sun8i-h3-spi";
187 reg = <0x01c05000 0x1000>;
188 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
190 clock-names = "ahb", "mod";
191 resets = <&ccu RST_BUS_SPI0>;
193 #address-cells = <1>;
198 compatible = "allwinner,sun8i-r40-spi",
199 "allwinner,sun8i-h3-spi";
200 reg = <0x01c06000 0x1000>;
201 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
203 clock-names = "ahb", "mod";
204 resets = <&ccu RST_BUS_SPI1>;
206 #address-cells = <1>;
211 compatible = "allwinner,sun8i-r40-csi0",
212 "allwinner,sun7i-a20-csi0";
213 reg = <0x01c09000 0x1000>;
214 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
216 <&ccu CLK_DRAM_CSI0>;
217 clock-names = "bus", "isp", "ram";
218 resets = <&ccu RST_BUS_CSI0>;
219 interconnects = <&mbus 5>;
220 interconnect-names = "dma-mem";
225 compatible = "allwinner,sun8i-r40-mmc",
226 "allwinner,sun50i-a64-mmc";
227 reg = <0x01c0f000 0x1000>;
228 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
229 clock-names = "ahb", "mmc";
230 resets = <&ccu RST_BUS_MMC0>;
232 pinctrl-0 = <&mmc0_pins>;
233 pinctrl-names = "default";
234 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
236 #address-cells = <1>;
241 compatible = "allwinner,sun8i-r40-mmc",
242 "allwinner,sun50i-a64-mmc";
243 reg = <0x01c10000 0x1000>;
244 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
245 clock-names = "ahb", "mmc";
246 resets = <&ccu RST_BUS_MMC1>;
248 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
250 #address-cells = <1>;
255 compatible = "allwinner,sun8i-r40-emmc",
256 "allwinner,sun50i-a64-emmc";
257 reg = <0x01c11000 0x1000>;
258 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
259 clock-names = "ahb", "mmc";
260 resets = <&ccu RST_BUS_MMC2>;
262 pinctrl-0 = <&mmc2_pins>;
263 pinctrl-names = "default";
264 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
266 #address-cells = <1>;
271 compatible = "allwinner,sun8i-r40-mmc",
272 "allwinner,sun50i-a64-mmc";
273 reg = <0x01c12000 0x1000>;
274 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
275 clock-names = "ahb", "mmc";
276 resets = <&ccu RST_BUS_MMC3>;
278 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
280 #address-cells = <1>;
284 usbphy: phy@1c13400 {
285 compatible = "allwinner,sun8i-r40-usb-phy";
286 reg = <0x01c13400 0x14>,
290 reg-names = "phy_ctrl",
294 clocks = <&ccu CLK_USB_PHY0>,
297 clock-names = "usb0_phy",
300 resets = <&ccu RST_USB_PHY0>,
303 reset-names = "usb0_reset",
310 crypto: crypto@1c15000 {
311 compatible = "allwinner,sun8i-r40-crypto";
312 reg = <0x01c15000 0x1000>;
313 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
315 clock-names = "bus", "mod";
316 resets = <&ccu RST_BUS_CE>;
320 compatible = "allwinner,sun8i-r40-spi",
321 "allwinner,sun8i-h3-spi";
322 reg = <0x01c17000 0x1000>;
323 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
325 clock-names = "ahb", "mod";
326 resets = <&ccu RST_BUS_SPI2>;
328 #address-cells = <1>;
333 compatible = "allwinner,sun8i-r40-ahci";
334 reg = <0x01c18000 0x1000>;
335 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
337 resets = <&ccu RST_BUS_SATA>;
338 reset-names = "ahci";
343 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
344 reg = <0x01c19000 0x100>;
345 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&ccu CLK_BUS_EHCI1>;
347 resets = <&ccu RST_BUS_EHCI1>;
354 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
355 reg = <0x01c19400 0x100>;
356 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&ccu CLK_BUS_OHCI1>,
358 <&ccu CLK_USB_OHCI1>;
359 resets = <&ccu RST_BUS_OHCI1>;
366 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
367 reg = <0x01c1c000 0x100>;
368 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&ccu CLK_BUS_EHCI2>;
370 resets = <&ccu RST_BUS_EHCI2>;
377 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
378 reg = <0x01c1c400 0x100>;
379 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&ccu CLK_BUS_OHCI2>,
381 <&ccu CLK_USB_OHCI2>;
382 resets = <&ccu RST_BUS_OHCI2>;
389 compatible = "allwinner,sun8i-r40-spi",
390 "allwinner,sun8i-h3-spi";
391 reg = <0x01c1f000 0x1000>;
392 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
394 clock-names = "ahb", "mod";
395 resets = <&ccu RST_BUS_SPI3>;
397 #address-cells = <1>;
402 compatible = "allwinner,sun8i-r40-ccu";
403 reg = <0x01c20000 0x400>;
404 clocks = <&osc24M>, <&rtc 0>;
405 clock-names = "hosc", "losc";
411 compatible = "allwinner,sun8i-r40-rtc";
412 reg = <0x01c20400 0x400>;
413 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
414 clock-output-names = "osc32k", "osc32k-out";
419 pio: pinctrl@1c20800 {
420 compatible = "allwinner,sun8i-r40-pinctrl";
421 reg = <0x01c20800 0x400>;
422 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
424 clock-names = "apb", "hosc", "losc";
426 interrupt-controller;
427 #interrupt-cells = <3>;
430 clk_out_a_pin: clk-out-a-pin {
432 function = "clk_out_a";
436 csi0_8bits_pins: csi0-8bits-pins {
437 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
438 "PE6", "PE7", "PE8", "PE9", "PE10",
444 csi0_mclk_pin: csi0-mclk-pin {
449 gmac_rgmii_pins: gmac-rgmii-pins {
450 pins = "PA0", "PA1", "PA2", "PA3",
451 "PA4", "PA5", "PA6", "PA7",
452 "PA8", "PA10", "PA11", "PA12",
453 "PA13", "PA15", "PA16";
456 * data lines in RGMII mode use DDR mode
457 * and need a higher signal drive strength
459 drive-strength = <40>;
462 i2c0_pins: i2c0-pins {
467 i2c1_pins: i2c1-pins {
468 pins = "PB18", "PB19";
472 i2c2_pins: i2c2-pins {
473 pins = "PB20", "PB21";
477 i2c3_pins: i2c3-pins {
482 i2c4_pins: i2c4-pins {
487 mmc0_pins: mmc0-pins {
488 pins = "PF0", "PF1", "PF2",
491 drive-strength = <30>;
495 mmc1_pg_pins: mmc1-pg-pins {
496 pins = "PG0", "PG1", "PG2",
499 drive-strength = <30>;
503 mmc2_pins: mmc2-pins {
504 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
505 "PC10", "PC11", "PC12", "PC13", "PC14",
508 drive-strength = <30>;
513 spi0_pc_pins: spi0-pc-pins {
514 pins = "PC0", "PC1", "PC2";
519 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
525 spi1_pi_pins: spi1-pi-pins {
526 pins = "PI17", "PI18", "PI19";
531 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
537 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
542 uart0_pb_pins: uart0-pb-pins {
543 pins = "PB22", "PB23";
547 uart3_pg_pins: uart3-pg-pins {
552 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
558 wdt: watchdog@1c20c90 {
559 compatible = "allwinner,sun4i-a10-wdt";
560 reg = <0x01c20c90 0x10>;
561 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
565 uart0: serial@1c28000 {
566 compatible = "snps,dw-apb-uart";
567 reg = <0x01c28000 0x400>;
568 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&ccu CLK_BUS_UART0>;
572 resets = <&ccu RST_BUS_UART0>;
576 uart1: serial@1c28400 {
577 compatible = "snps,dw-apb-uart";
578 reg = <0x01c28400 0x400>;
579 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&ccu CLK_BUS_UART1>;
583 resets = <&ccu RST_BUS_UART1>;
587 uart2: serial@1c28800 {
588 compatible = "snps,dw-apb-uart";
589 reg = <0x01c28800 0x400>;
590 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&ccu CLK_BUS_UART2>;
594 resets = <&ccu RST_BUS_UART2>;
598 uart3: serial@1c28c00 {
599 compatible = "snps,dw-apb-uart";
600 reg = <0x01c28c00 0x400>;
601 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&ccu CLK_BUS_UART3>;
605 resets = <&ccu RST_BUS_UART3>;
609 uart4: serial@1c29000 {
610 compatible = "snps,dw-apb-uart";
611 reg = <0x01c29000 0x400>;
612 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&ccu CLK_BUS_UART4>;
616 resets = <&ccu RST_BUS_UART4>;
620 uart5: serial@1c29400 {
621 compatible = "snps,dw-apb-uart";
622 reg = <0x01c29400 0x400>;
623 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&ccu CLK_BUS_UART5>;
627 resets = <&ccu RST_BUS_UART5>;
631 uart6: serial@1c29800 {
632 compatible = "snps,dw-apb-uart";
633 reg = <0x01c29800 0x400>;
634 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&ccu CLK_BUS_UART6>;
638 resets = <&ccu RST_BUS_UART6>;
642 uart7: serial@1c29c00 {
643 compatible = "snps,dw-apb-uart";
644 reg = <0x01c29c00 0x400>;
645 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&ccu CLK_BUS_UART7>;
649 resets = <&ccu RST_BUS_UART7>;
654 compatible = "allwinner,sun6i-a31-i2c";
655 reg = <0x01c2ac00 0x400>;
656 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&ccu CLK_BUS_I2C0>;
658 resets = <&ccu RST_BUS_I2C0>;
659 pinctrl-0 = <&i2c0_pins>;
660 pinctrl-names = "default";
662 #address-cells = <1>;
667 compatible = "allwinner,sun6i-a31-i2c";
668 reg = <0x01c2b000 0x400>;
669 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&ccu CLK_BUS_I2C1>;
671 resets = <&ccu RST_BUS_I2C1>;
672 pinctrl-0 = <&i2c1_pins>;
673 pinctrl-names = "default";
675 #address-cells = <1>;
680 compatible = "allwinner,sun6i-a31-i2c";
681 reg = <0x01c2b400 0x400>;
682 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&ccu CLK_BUS_I2C2>;
684 resets = <&ccu RST_BUS_I2C2>;
685 pinctrl-0 = <&i2c2_pins>;
686 pinctrl-names = "default";
688 #address-cells = <1>;
693 compatible = "allwinner,sun6i-a31-i2c";
694 reg = <0x01c2b800 0x400>;
695 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&ccu CLK_BUS_I2C3>;
697 resets = <&ccu RST_BUS_I2C3>;
698 pinctrl-0 = <&i2c3_pins>;
699 pinctrl-names = "default";
701 #address-cells = <1>;
706 compatible = "allwinner,sun6i-a31-i2c";
707 reg = <0x01c2c000 0x400>;
708 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&ccu CLK_BUS_I2C4>;
710 resets = <&ccu RST_BUS_I2C4>;
711 pinctrl-0 = <&i2c4_pins>;
712 pinctrl-names = "default";
714 #address-cells = <1>;
718 gmac: ethernet@1c50000 {
719 compatible = "allwinner,sun8i-r40-gmac";
721 reg = <0x01c50000 0x10000>;
722 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "macirq";
724 resets = <&ccu RST_BUS_GMAC>;
725 reset-names = "stmmaceth";
726 clocks = <&ccu CLK_BUS_GMAC>;
727 clock-names = "stmmaceth";
731 compatible = "snps,dwmac-mdio";
732 #address-cells = <1>;
737 mbus: dram-controller@1c62000 {
738 compatible = "allwinner,sun8i-r40-mbus";
739 reg = <0x01c62000 0x1000>;
741 dma-ranges = <0x00000000 0x40000000 0x80000000>;
742 #interconnect-cells = <1>;
745 tcon_top: tcon-top@1c70000 {
746 compatible = "allwinner,sun8i-r40-tcon-top";
747 reg = <0x01c70000 0x1000>;
748 clocks = <&ccu CLK_BUS_TCON_TOP>,
760 clock-output-names = "tcon-top-tv0",
763 resets = <&ccu RST_BUS_TCON_TOP>;
767 #address-cells = <1>;
770 tcon_top_mixer0_in: port@0 {
773 tcon_top_mixer0_in_mixer0: endpoint {
774 remote-endpoint = <&mixer0_out_tcon_top>;
778 tcon_top_mixer0_out: port@1 {
779 #address-cells = <1>;
783 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
787 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
791 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
793 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
796 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
798 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
802 tcon_top_mixer1_in: port@2 {
803 #address-cells = <1>;
807 tcon_top_mixer1_in_mixer1: endpoint@1 {
809 remote-endpoint = <&mixer1_out_tcon_top>;
813 tcon_top_mixer1_out: port@3 {
814 #address-cells = <1>;
818 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
822 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
826 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
828 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
831 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
833 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
837 tcon_top_hdmi_in: port@4 {
838 #address-cells = <1>;
842 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
844 remote-endpoint = <&tcon_tv0_out_tcon_top>;
847 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
849 remote-endpoint = <&tcon_tv1_out_tcon_top>;
853 tcon_top_hdmi_out: port@5 {
856 tcon_top_hdmi_out_hdmi: endpoint {
857 remote-endpoint = <&hdmi_in_tcon_top>;
863 tcon_tv0: lcd-controller@1c73000 {
864 compatible = "allwinner,sun8i-r40-tcon-tv";
865 reg = <0x01c73000 0x1000>;
866 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
868 clock-names = "ahb", "tcon-ch1";
869 resets = <&ccu RST_BUS_TCON_TV0>;
874 #address-cells = <1>;
877 tcon_tv0_in: port@0 {
878 #address-cells = <1>;
882 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
884 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
887 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
889 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
893 tcon_tv0_out: port@1 {
894 #address-cells = <1>;
898 tcon_tv0_out_tcon_top: endpoint@1 {
900 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
906 tcon_tv1: lcd-controller@1c74000 {
907 compatible = "allwinner,sun8i-r40-tcon-tv";
908 reg = <0x01c74000 0x1000>;
909 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
911 clock-names = "ahb", "tcon-ch1";
912 resets = <&ccu RST_BUS_TCON_TV1>;
917 #address-cells = <1>;
920 tcon_tv1_in: port@0 {
921 #address-cells = <1>;
925 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
927 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
930 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
932 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
936 tcon_tv1_out: port@1 {
937 #address-cells = <1>;
941 tcon_tv1_out_tcon_top: endpoint@1 {
943 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
949 gic: interrupt-controller@1c81000 {
950 compatible = "arm,gic-400";
951 reg = <0x01c81000 0x1000>,
955 interrupt-controller;
956 #interrupt-cells = <3>;
957 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
961 compatible = "allwinner,sun8i-r40-dw-hdmi",
962 "allwinner,sun8i-a83t-dw-hdmi";
963 reg = <0x01ee0000 0x10000>;
965 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
968 clock-names = "iahb", "isfr", "tmds";
969 resets = <&ccu RST_BUS_HDMI1>;
970 reset-names = "ctrl";
976 #address-cells = <1>;
982 hdmi_in_tcon_top: endpoint {
983 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
993 hdmi_phy: hdmi-phy@1ef0000 {
994 compatible = "allwinner,sun8i-r40-hdmi-phy";
995 reg = <0x01ef0000 0x10000>;
996 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
997 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
998 clock-names = "bus", "mod", "pll-0", "pll-1";
999 resets = <&ccu RST_BUS_HDMI0>;
1000 reset-names = "phy";
1006 compatible = "arm,cortex-a7-pmu";
1007 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1010 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1011 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1015 compatible = "arm,armv7-timer";
1016 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1017 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1018 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1019 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;