2 * Copyright 2015 Vishnu Patekar
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 interrupt-parent = <&gic>;
65 compatible = "arm,cortex-a7";
71 compatible = "arm,cortex-a7";
77 compatible = "arm,cortex-a7";
83 compatible = "arm,cortex-a7";
89 compatible = "arm,cortex-a7";
95 compatible = "arm,cortex-a7";
101 compatible = "arm,cortex-a7";
107 compatible = "arm,cortex-a7";
114 compatible = "arm,armv7-timer";
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
122 #address-cells = <1>;
126 /* TODO: PRCM block has a mux for this. */
129 compatible = "fixed-clock";
130 clock-frequency = <24000000>;
131 clock-accuracy = <50000>;
132 clock-output-names = "osc24M";
136 * This is called "internal OSC" in some places.
137 * It is an internal RC-based oscillator.
138 * TODO: Its controls are in the PRCM block.
142 compatible = "fixed-clock";
143 clock-frequency = <16000000>;
144 clock-output-names = "osc16M";
147 osc16Md512: osc16Md512_clk {
149 compatible = "fixed-factor-clock";
153 clock-output-names = "osc16M-d512";
158 reg = <0x40000000 0x80000000>;
159 device_type = "memory";
163 compatible = "simple-bus";
164 #address-cells = <1>;
168 syscon: syscon@1c00000 {
169 compatible = "allwinner,sun8i-a83t-system-controller",
171 reg = <0x01c00000 0x1000>;
174 dma: dma-controller@1c02000 {
175 compatible = "allwinner,sun8i-a83t-dma";
176 reg = <0x01c02000 0x1000>;
177 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
184 compatible = "allwinner,sun8i-a83t-ccu";
185 reg = <0x01c20000 0x400>;
186 clocks = <&osc24M>, <&osc16Md512>;
187 clock-names = "hosc", "losc";
192 pio: pinctrl@1c20800 {
193 compatible = "allwinner,sun8i-a83t-pinctrl";
194 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
197 reg = <0x01c20800 0x400>;
198 clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
199 clock-names = "apb", "hosc", "losc";
201 interrupt-controller;
202 #interrupt-cells = <3>;
205 mmc0_pins: mmc0-pins {
206 pins = "PF0", "PF1", "PF2",
209 drive-strength = <30>;
213 spdif_tx_pin: spdif-tx-pin {
218 uart0_pb_pins: uart0-pb-pins {
219 pins = "PB9", "PB10";
223 uart0_pf_pins: uart0-pf-pins {
230 compatible = "allwinner,sun4i-a10-timer";
231 reg = <0x01c20c00 0xa0>;
232 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
238 compatible = "allwinner,sun6i-a31-wdt";
239 reg = <0x01c20ca0 0x20>;
240 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
244 spdif: spdif@1c21000 {
245 #sound-dai-cells = <0>;
246 compatible = "allwinner,sun8i-a83t-spdif",
247 "allwinner,sun8i-h3-spdif";
248 reg = <0x01c21000 0x400>;
249 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&ccu 44>, <&ccu 76>;
252 clock-names = "apb", "spdif";
255 pinctrl-names = "default";
256 pinctrl-0 = <&spdif_tx_pin>;
260 uart0: serial@01c28000 {
261 compatible = "snps,dw-apb-uart";
262 reg = <0x01c28000 0x400>;
263 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
271 gic: interrupt-controller@1c81000 {
272 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
273 reg = <0x01c81000 0x1000>,
277 interrupt-controller;
278 #interrupt-cells = <3>;
279 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
282 r_ccu: clock@1f01400 {
283 compatible = "allwinner,sun8i-a83t-r-ccu";
284 reg = <0x01f01400 0x400>;
285 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
287 clock-names = "hosc", "losc", "iosc", "pll-periph";
292 r_pio: pinctrl@1f02c00 {
293 compatible = "allwinner,sun8i-a83t-r-pinctrl";
294 reg = <0x01f02c00 0x400>;
295 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
298 clock-names = "apb", "hosc", "losc";
301 interrupt-controller;
302 #interrupt-cells = <3>;