2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
51 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
54 interrupt-parent = <&gic>;
61 simplefb_lcd: framebuffer@0 {
62 compatible = "allwinner,simple-framebuffer",
64 allwinner,pipeline = "de_be0-lcd0";
65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
73 compatible = "arm,armv7-timer";
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <24000000>;
79 arm,cpu-registers-not-fw-configured;
83 enable-method = "allwinner,sun8i-a23";
88 compatible = "arm,cortex-a7";
94 compatible = "arm,cortex-a7";
101 #address-cells = <1>;
107 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-output-names = "osc24M";
114 compatible = "fixed-clock";
115 clock-frequency = <32768>;
116 clock-output-names = "osc32k";
121 compatible = "simple-bus";
122 #address-cells = <1>;
126 dma: dma-controller@01c02000 {
127 compatible = "allwinner,sun8i-a23-dma";
128 reg = <0x01c02000 0x1000>;
129 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&ccu CLK_BUS_DMA>;
131 resets = <&ccu RST_BUS_DMA>;
136 compatible = "allwinner,sun7i-a20-mmc";
137 reg = <0x01c0f000 0x1000>;
138 clocks = <&ccu CLK_BUS_MMC0>,
140 <&ccu CLK_MMC0_OUTPUT>,
141 <&ccu CLK_MMC0_SAMPLE>;
146 resets = <&ccu RST_BUS_MMC0>;
148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
150 #address-cells = <1>;
155 compatible = "allwinner,sun7i-a20-mmc";
156 reg = <0x01c10000 0x1000>;
157 clocks = <&ccu CLK_BUS_MMC1>,
159 <&ccu CLK_MMC1_OUTPUT>,
160 <&ccu CLK_MMC1_SAMPLE>;
165 resets = <&ccu RST_BUS_MMC1>;
167 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
169 #address-cells = <1>;
174 compatible = "allwinner,sun7i-a20-mmc";
175 reg = <0x01c11000 0x1000>;
176 clocks = <&ccu CLK_BUS_MMC2>,
178 <&ccu CLK_MMC2_OUTPUT>,
179 <&ccu CLK_MMC2_SAMPLE>;
184 resets = <&ccu RST_BUS_MMC2>;
186 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
188 #address-cells = <1>;
193 compatible = "allwinner,sun4i-a10-nand";
194 reg = <0x01c03000 0x1000>;
195 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
197 clock-names = "ahb", "mod";
198 resets = <&ccu RST_BUS_NAND>;
201 #address-cells = <1>;
205 usb_otg: usb@01c19000 {
206 /* compatible gets set in SoC specific dtsi file */
207 reg = <0x01c19000 0x0400>;
208 clocks = <&ccu CLK_BUS_OTG>;
209 resets = <&ccu RST_BUS_OTG>;
210 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-names = "mc";
214 extcon = <&usbphy 0>;
218 usbphy: phy@01c19400 {
220 * compatible and address regions get set in
221 * SoC specific dtsi file
223 clocks = <&ccu CLK_USB_PHY0>,
225 clock-names = "usb0_phy",
227 resets = <&ccu RST_USB_PHY0>,
229 reset-names = "usb0_reset",
235 ehci0: usb@01c1a000 {
236 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
237 reg = <0x01c1a000 0x100>;
238 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&ccu CLK_BUS_EHCI>;
240 resets = <&ccu RST_BUS_EHCI>;
246 ohci0: usb@01c1a400 {
247 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
248 reg = <0x01c1a400 0x100>;
249 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
251 resets = <&ccu RST_BUS_OHCI>;
257 ccu: clock@01c20000 {
258 reg = <0x01c20000 0x400>;
259 clocks = <&osc24M>, <&osc32k>;
260 clock-names = "hosc", "losc";
265 pio: pinctrl@01c20800 {
266 /* compatible gets set in SoC specific dtsi file */
267 reg = <0x01c20800 0x400>;
268 /* interrupts get set in SoC specific dtsi file */
269 clocks = <&ccu CLK_BUS_PIO>;
271 interrupt-controller;
272 #interrupt-cells = <3>;
275 uart0_pins_a: uart0@0 {
276 allwinner,pins = "PF2", "PF4";
277 allwinner,function = "uart0";
278 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
279 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
282 uart1_pins_a: uart1@0 {
283 allwinner,pins = "PG6", "PG7";
284 allwinner,function = "uart1";
287 uart1_pins_cts_rts_a: uart1-cts-rts@0 {
288 allwinner,pins = "PG8", "PG9";
289 allwinner,function = "uart1";
292 mmc0_pins_a: mmc0@0 {
293 allwinner,pins = "PF0", "PF1", "PF2",
295 allwinner,function = "mmc0";
296 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
297 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
300 mmc1_pins_a: mmc1@0 {
301 allwinner,pins = "PG0", "PG1", "PG2",
303 allwinner,function = "mmc1";
304 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
305 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
308 mmc2_8bit_pins: mmc2_8bit {
309 allwinner,pins = "PC5", "PC6", "PC8",
310 "PC9", "PC10", "PC11",
311 "PC12", "PC13", "PC14",
313 allwinner,function = "mmc2";
314 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
315 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
319 allwinner,pins = "PH0";
320 allwinner,function = "pwm0";
321 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
322 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
325 i2c0_pins_a: i2c0@0 {
326 allwinner,pins = "PH2", "PH3";
327 allwinner,function = "i2c0";
328 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
329 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
332 i2c1_pins_a: i2c1@0 {
333 allwinner,pins = "PH4", "PH5";
334 allwinner,function = "i2c1";
335 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
336 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
339 i2c2_pins_a: i2c2@0 {
340 allwinner,pins = "PE12", "PE13";
341 allwinner,function = "i2c2";
342 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
343 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
346 lcd_rgb666_pins: lcd-rgb666@0 {
347 allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
348 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
349 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
350 "PD24", "PD25", "PD26", "PD27";
351 allwinner,function = "lcd0";
352 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
353 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
358 compatible = "allwinner,sun4i-a10-timer";
359 reg = <0x01c20c00 0xa0>;
360 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
365 wdt0: watchdog@01c20ca0 {
366 compatible = "allwinner,sun6i-a31-wdt";
367 reg = <0x01c20ca0 0x20>;
368 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
372 compatible = "allwinner,sun7i-a20-pwm";
373 reg = <0x01c21400 0xc>;
379 lradc: lradc@01c22800 {
380 compatible = "allwinner,sun4i-a10-lradc-keys";
381 reg = <0x01c22800 0x100>;
382 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
386 uart0: serial@01c28000 {
387 compatible = "snps,dw-apb-uart";
388 reg = <0x01c28000 0x400>;
389 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&ccu CLK_BUS_UART0>;
393 resets = <&ccu RST_BUS_UART0>;
394 dmas = <&dma 6>, <&dma 6>;
395 dma-names = "rx", "tx";
399 uart1: serial@01c28400 {
400 compatible = "snps,dw-apb-uart";
401 reg = <0x01c28400 0x400>;
402 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&ccu CLK_BUS_UART1>;
406 resets = <&ccu RST_BUS_UART1>;
407 dmas = <&dma 7>, <&dma 7>;
408 dma-names = "rx", "tx";
412 uart2: serial@01c28800 {
413 compatible = "snps,dw-apb-uart";
414 reg = <0x01c28800 0x400>;
415 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&ccu CLK_BUS_UART2>;
419 resets = <&ccu RST_BUS_UART2>;
420 dmas = <&dma 8>, <&dma 8>;
421 dma-names = "rx", "tx";
425 uart3: serial@01c28c00 {
426 compatible = "snps,dw-apb-uart";
427 reg = <0x01c28c00 0x400>;
428 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&ccu CLK_BUS_UART3>;
432 resets = <&ccu RST_BUS_UART3>;
433 dmas = <&dma 9>, <&dma 9>;
434 dma-names = "rx", "tx";
438 uart4: serial@01c29000 {
439 compatible = "snps,dw-apb-uart";
440 reg = <0x01c29000 0x400>;
441 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS_UART4>;
445 resets = <&ccu RST_BUS_UART4>;
446 dmas = <&dma 10>, <&dma 10>;
447 dma-names = "rx", "tx";
452 compatible = "allwinner,sun6i-a31-i2c";
453 reg = <0x01c2ac00 0x400>;
454 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&ccu CLK_BUS_I2C0>;
456 resets = <&ccu RST_BUS_I2C0>;
458 #address-cells = <1>;
463 compatible = "allwinner,sun6i-a31-i2c";
464 reg = <0x01c2b000 0x400>;
465 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&ccu CLK_BUS_I2C1>;
467 resets = <&ccu RST_BUS_I2C1>;
469 #address-cells = <1>;
474 compatible = "allwinner,sun6i-a31-i2c";
475 reg = <0x01c2b400 0x400>;
476 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&ccu CLK_BUS_I2C2>;
478 resets = <&ccu RST_BUS_I2C2>;
480 #address-cells = <1>;
484 gic: interrupt-controller@01c81000 {
485 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
486 reg = <0x01c81000 0x1000>,
490 interrupt-controller;
491 #interrupt-cells = <3>;
492 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
496 compatible = "allwinner,sun6i-a31-rtc";
497 reg = <0x01f00000 0x54>;
498 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
502 nmi_intc: interrupt-controller@01f00c0c {
503 compatible = "allwinner,sun6i-a31-sc-nmi";
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 reg = <0x01f00c0c 0x38>;
507 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
511 compatible = "allwinner,sun8i-a23-prcm";
512 reg = <0x01f01400 0x200>;
515 compatible = "fixed-factor-clock";
520 clock-output-names = "ar100";
524 compatible = "fixed-factor-clock";
529 clock-output-names = "ahb0";
533 compatible = "allwinner,sun8i-a23-apb0-clk";
536 clock-output-names = "apb0";
539 apb0_gates: apb0_gates_clk {
540 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
543 clock-output-names = "apb0_pio", "apb0_timer",
544 "apb0_rsb", "apb0_uart",
549 compatible = "allwinner,sun6i-a31-clock-reset";
555 compatible = "allwinner,sun8i-a23-cpuconfig";
556 reg = <0x01f01c00 0x300>;
559 r_uart: serial@01f02800 {
560 compatible = "snps,dw-apb-uart";
561 reg = <0x01f02800 0x400>;
562 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&apb0_gates 4>;
566 resets = <&apb0_rst 4>;
570 r_pio: pinctrl@01f02c00 {
571 compatible = "allwinner,sun8i-a23-r-pinctrl";
572 reg = <0x01f02c00 0x400>;
573 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&apb0_gates 0>;
575 resets = <&apb0_rst 0>;
577 interrupt-controller;
578 #interrupt-cells = <3>;
579 #address-cells = <1>;
584 allwinner,pins = "PL0", "PL1";
585 allwinner,function = "s_rsb";
586 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
587 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
590 r_uart_pins_a: r_uart@0 {
591 allwinner,pins = "PL2", "PL3";
592 allwinner,function = "s_uart";
593 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
594 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
598 r_rsb: rsb@01f03400 {
599 compatible = "allwinner,sun8i-a23-rsb";
600 reg = <0x01f03400 0x400>;
601 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&apb0_gates 3>;
603 clock-frequency = <3000000>;
604 resets = <&apb0_rst 3>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&r_rsb_pins>;
608 #address-cells = <1>;