2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 #include "skeleton.dtsi"
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 #include <dt-bindings/thermal/thermal.h>
55 #include <dt-bindings/dma/sun4i-a10.h>
56 #include <dt-bindings/pinctrl/sun4i-a10.h>
59 interrupt-parent = <&gic>;
71 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
72 allwinner,pipeline = "de_be0-lcd0-hdmi";
73 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
79 compatible = "allwinner,simple-framebuffer",
81 allwinner,pipeline = "de_be0-lcd0";
82 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
87 compatible = "allwinner,simple-framebuffer",
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
101 compatible = "arm,cortex-a7";
105 clock-latency = <244144>; /* 8 32k periods */
117 #cooling-cells = <2>;
118 cooling-min-level = <0>;
119 cooling-max-level = <7>;
123 compatible = "arm,cortex-a7";
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
144 cpu_alert0: cpu_alert0 {
146 temperature = <75000>;
153 temperature = <100000>;
162 reg = <0x40000000 0x80000000>;
166 compatible = "arm,armv7-timer";
167 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
170 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
174 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
175 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
180 #address-cells = <1>;
184 osc24M: clk@01c20050 {
186 compatible = "allwinner,sun4i-a10-osc-clk";
187 reg = <0x01c20050 0x4>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc24M";
194 compatible = "fixed-clock";
195 clock-frequency = <32768>;
196 clock-output-names = "osc32k";
201 compatible = "allwinner,sun4i-a10-pll1-clk";
202 reg = <0x01c20000 0x4>;
204 clock-output-names = "pll1";
209 compatible = "allwinner,sun7i-a20-pll4-clk";
210 reg = <0x01c20018 0x4>;
212 clock-output-names = "pll4";
217 compatible = "allwinner,sun4i-a10-pll5-clk";
218 reg = <0x01c20020 0x4>;
220 clock-output-names = "pll5_ddr", "pll5_other";
225 compatible = "allwinner,sun4i-a10-pll6-clk";
226 reg = <0x01c20028 0x4>;
228 clock-output-names = "pll6_sata", "pll6_other", "pll6";
233 compatible = "allwinner,sun7i-a20-pll4-clk";
234 reg = <0x01c20040 0x4>;
236 clock-output-names = "pll8";
241 compatible = "allwinner,sun4i-a10-cpu-clk";
242 reg = <0x01c20054 0x4>;
243 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
244 clock-output-names = "cpu";
249 compatible = "allwinner,sun4i-a10-axi-clk";
250 reg = <0x01c20054 0x4>;
252 clock-output-names = "axi";
257 compatible = "allwinner,sun4i-a10-ahb-clk";
258 reg = <0x01c20054 0x4>;
260 clock-output-names = "ahb";
263 ahb_gates: clk@01c20060 {
265 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
266 reg = <0x01c20060 0x8>;
268 clock-output-names = "ahb_usb0", "ahb_ehci0",
269 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
270 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
271 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
272 "ahb_nand", "ahb_sdram", "ahb_ace",
273 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
274 "ahb_spi2", "ahb_spi3", "ahb_sata",
275 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
276 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
277 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
278 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
279 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
283 apb0: apb0@01c20054 {
285 compatible = "allwinner,sun4i-a10-apb0-clk";
286 reg = <0x01c20054 0x4>;
288 clock-output-names = "apb0";
291 apb0_gates: clk@01c20068 {
293 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
294 reg = <0x01c20068 0x4>;
296 clock-output-names = "apb0_codec", "apb0_spdif",
297 "apb0_ac97", "apb0_iis0", "apb0_iis1",
298 "apb0_pio", "apb0_ir0", "apb0_ir1",
299 "apb0_iis2", "apb0_keypad";
304 compatible = "allwinner,sun4i-a10-apb1-clk";
305 reg = <0x01c20058 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
307 clock-output-names = "apb1";
310 apb1_gates: clk@01c2006c {
312 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
313 reg = <0x01c2006c 0x4>;
315 clock-output-names = "apb1_i2c0", "apb1_i2c1",
316 "apb1_i2c2", "apb1_i2c3", "apb1_can",
317 "apb1_scr", "apb1_ps20", "apb1_ps21",
318 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
319 "apb1_uart2", "apb1_uart3", "apb1_uart4",
320 "apb1_uart5", "apb1_uart6", "apb1_uart7";
323 nand_clk: clk@01c20080 {
325 compatible = "allwinner,sun4i-a10-mod0-clk";
326 reg = <0x01c20080 0x4>;
327 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
328 clock-output-names = "nand";
331 ms_clk: clk@01c20084 {
333 compatible = "allwinner,sun4i-a10-mod0-clk";
334 reg = <0x01c20084 0x4>;
335 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
336 clock-output-names = "ms";
339 mmc0_clk: clk@01c20088 {
341 compatible = "allwinner,sun4i-a10-mod0-clk";
342 reg = <0x01c20088 0x4>;
343 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
344 clock-output-names = "mmc0";
347 mmc1_clk: clk@01c2008c {
349 compatible = "allwinner,sun4i-a10-mod0-clk";
350 reg = <0x01c2008c 0x4>;
351 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
352 clock-output-names = "mmc1";
355 mmc2_clk: clk@01c20090 {
357 compatible = "allwinner,sun4i-a10-mod0-clk";
358 reg = <0x01c20090 0x4>;
359 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
360 clock-output-names = "mmc2";
363 mmc3_clk: clk@01c20094 {
365 compatible = "allwinner,sun4i-a10-mod0-clk";
366 reg = <0x01c20094 0x4>;
367 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
368 clock-output-names = "mmc3";
371 ts_clk: clk@01c20098 {
373 compatible = "allwinner,sun4i-a10-mod0-clk";
374 reg = <0x01c20098 0x4>;
375 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
376 clock-output-names = "ts";
379 ss_clk: clk@01c2009c {
381 compatible = "allwinner,sun4i-a10-mod0-clk";
382 reg = <0x01c2009c 0x4>;
383 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
384 clock-output-names = "ss";
387 spi0_clk: clk@01c200a0 {
389 compatible = "allwinner,sun4i-a10-mod0-clk";
390 reg = <0x01c200a0 0x4>;
391 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
392 clock-output-names = "spi0";
395 spi1_clk: clk@01c200a4 {
397 compatible = "allwinner,sun4i-a10-mod0-clk";
398 reg = <0x01c200a4 0x4>;
399 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
400 clock-output-names = "spi1";
403 spi2_clk: clk@01c200a8 {
405 compatible = "allwinner,sun4i-a10-mod0-clk";
406 reg = <0x01c200a8 0x4>;
407 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
408 clock-output-names = "spi2";
411 pata_clk: clk@01c200ac {
413 compatible = "allwinner,sun4i-a10-mod0-clk";
414 reg = <0x01c200ac 0x4>;
415 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
416 clock-output-names = "pata";
419 ir0_clk: clk@01c200b0 {
421 compatible = "allwinner,sun4i-a10-mod0-clk";
422 reg = <0x01c200b0 0x4>;
423 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
424 clock-output-names = "ir0";
427 ir1_clk: clk@01c200b4 {
429 compatible = "allwinner,sun4i-a10-mod0-clk";
430 reg = <0x01c200b4 0x4>;
431 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
432 clock-output-names = "ir1";
435 usb_clk: clk@01c200cc {
438 compatible = "allwinner,sun4i-a10-usb-clk";
439 reg = <0x01c200cc 0x4>;
441 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
444 spi3_clk: clk@01c200d4 {
446 compatible = "allwinner,sun4i-a10-mod0-clk";
447 reg = <0x01c200d4 0x4>;
448 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
449 clock-output-names = "spi3";
452 mbus_clk: clk@01c2015c {
454 compatible = "allwinner,sun5i-a13-mbus-clk";
455 reg = <0x01c2015c 0x4>;
456 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
457 clock-output-names = "mbus";
461 * The following two are dummy clocks, placeholders used in the gmac_tx
462 * clock. The gmac driver will choose one parent depending on the PHY
463 * interface mode, using clk_set_rate auto-reparenting.
464 * The actual TX clock rate is not controlled by the gmac_tx clock.
466 mii_phy_tx_clk: clk@2 {
468 compatible = "fixed-clock";
469 clock-frequency = <25000000>;
470 clock-output-names = "mii_phy_tx";
473 gmac_int_tx_clk: clk@3 {
475 compatible = "fixed-clock";
476 clock-frequency = <125000000>;
477 clock-output-names = "gmac_int_tx";
480 gmac_tx_clk: clk@01c20164 {
482 compatible = "allwinner,sun7i-a20-gmac-clk";
483 reg = <0x01c20164 0x4>;
484 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
485 clock-output-names = "gmac_tx";
489 * Dummy clock used by output clocks
493 compatible = "fixed-factor-clock";
497 clock-output-names = "osc24M_32k";
500 clk_out_a: clk@01c201f0 {
502 compatible = "allwinner,sun7i-a20-out-clk";
503 reg = <0x01c201f0 0x4>;
504 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
505 clock-output-names = "clk_out_a";
508 clk_out_b: clk@01c201f4 {
510 compatible = "allwinner,sun7i-a20-out-clk";
511 reg = <0x01c201f4 0x4>;
512 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
513 clock-output-names = "clk_out_b";
518 compatible = "simple-bus";
519 #address-cells = <1>;
523 nmi_intc: interrupt-controller@01c00030 {
524 compatible = "allwinner,sun7i-a20-sc-nmi";
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 reg = <0x01c00030 0x0c>;
528 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
531 dma: dma-controller@01c02000 {
532 compatible = "allwinner,sun4i-a10-dma";
533 reg = <0x01c02000 0x1000>;
534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&ahb_gates 6>;
540 compatible = "allwinner,sun4i-a10-spi";
541 reg = <0x01c05000 0x1000>;
542 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&ahb_gates 20>, <&spi0_clk>;
544 clock-names = "ahb", "mod";
545 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
546 <&dma SUN4I_DMA_DEDICATED 26>;
547 dma-names = "rx", "tx";
549 #address-cells = <1>;
554 compatible = "allwinner,sun4i-a10-spi";
555 reg = <0x01c06000 0x1000>;
556 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&ahb_gates 21>, <&spi1_clk>;
558 clock-names = "ahb", "mod";
559 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
560 <&dma SUN4I_DMA_DEDICATED 8>;
561 dma-names = "rx", "tx";
563 #address-cells = <1>;
567 emac: ethernet@01c0b000 {
568 compatible = "allwinner,sun4i-a10-emac";
569 reg = <0x01c0b000 0x1000>;
570 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&ahb_gates 17>;
575 mdio: mdio@01c0b080 {
576 compatible = "allwinner,sun4i-a10-mdio";
577 reg = <0x01c0b080 0x14>;
579 #address-cells = <1>;
584 compatible = "allwinner,sun5i-a13-mmc";
585 reg = <0x01c0f000 0x1000>;
586 clocks = <&ahb_gates 8>, <&mmc0_clk>;
587 clock-names = "ahb", "mmc";
588 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
593 compatible = "allwinner,sun5i-a13-mmc";
594 reg = <0x01c10000 0x1000>;
595 clocks = <&ahb_gates 9>, <&mmc1_clk>;
596 clock-names = "ahb", "mmc";
597 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
602 compatible = "allwinner,sun5i-a13-mmc";
603 reg = <0x01c11000 0x1000>;
604 clocks = <&ahb_gates 10>, <&mmc2_clk>;
605 clock-names = "ahb", "mmc";
606 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
611 compatible = "allwinner,sun5i-a13-mmc";
612 reg = <0x01c12000 0x1000>;
613 clocks = <&ahb_gates 11>, <&mmc3_clk>;
614 clock-names = "ahb", "mmc";
615 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
619 usbphy: phy@01c13400 {
621 compatible = "allwinner,sun7i-a20-usb-phy";
622 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
623 reg-names = "phy_ctrl", "pmu1", "pmu2";
624 clocks = <&usb_clk 8>;
625 clock-names = "usb_phy";
626 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
627 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
631 ehci0: usb@01c14000 {
632 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
633 reg = <0x01c14000 0x100>;
634 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&ahb_gates 1>;
641 ohci0: usb@01c14400 {
642 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
643 reg = <0x01c14400 0x100>;
644 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&usb_clk 6>, <&ahb_gates 2>;
652 compatible = "allwinner,sun4i-a10-spi";
653 reg = <0x01c17000 0x1000>;
654 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&ahb_gates 22>, <&spi2_clk>;
656 clock-names = "ahb", "mod";
657 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
658 <&dma SUN4I_DMA_DEDICATED 28>;
659 dma-names = "rx", "tx";
661 #address-cells = <1>;
665 ahci: sata@01c18000 {
666 compatible = "allwinner,sun4i-a10-ahci";
667 reg = <0x01c18000 0x1000>;
668 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&pll6 0>, <&ahb_gates 25>;
673 ehci1: usb@01c1c000 {
674 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
675 reg = <0x01c1c000 0x100>;
676 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&ahb_gates 3>;
683 ohci1: usb@01c1c400 {
684 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
685 reg = <0x01c1c400 0x100>;
686 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&usb_clk 7>, <&ahb_gates 4>;
694 compatible = "allwinner,sun4i-a10-spi";
695 reg = <0x01c1f000 0x1000>;
696 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&ahb_gates 23>, <&spi3_clk>;
698 clock-names = "ahb", "mod";
699 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
700 <&dma SUN4I_DMA_DEDICATED 30>;
701 dma-names = "rx", "tx";
703 #address-cells = <1>;
707 pio: pinctrl@01c20800 {
708 compatible = "allwinner,sun7i-a20-pinctrl";
709 reg = <0x01c20800 0x400>;
710 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&apb0_gates 5>;
713 interrupt-controller;
714 #interrupt-cells = <2>;
718 pwm0_pins_a: pwm0@0 {
719 allwinner,pins = "PB2";
720 allwinner,function = "pwm";
721 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
722 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
725 pwm1_pins_a: pwm1@0 {
726 allwinner,pins = "PI3";
727 allwinner,function = "pwm";
728 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
729 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
732 uart0_pins_a: uart0@0 {
733 allwinner,pins = "PB22", "PB23";
734 allwinner,function = "uart0";
735 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
736 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
739 uart2_pins_a: uart2@0 {
740 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
741 allwinner,function = "uart2";
742 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
743 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
746 uart3_pins_a: uart3@0 {
747 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
748 allwinner,function = "uart3";
749 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
750 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
753 uart3_pins_b: uart3@1 {
754 allwinner,pins = "PH0", "PH1";
755 allwinner,function = "uart3";
756 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
757 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
760 uart4_pins_a: uart4@0 {
761 allwinner,pins = "PG10", "PG11";
762 allwinner,function = "uart4";
763 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
764 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
767 uart5_pins_a: uart5@0 {
768 allwinner,pins = "PI10", "PI11";
769 allwinner,function = "uart5";
770 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
771 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
774 uart6_pins_a: uart6@0 {
775 allwinner,pins = "PI12", "PI13";
776 allwinner,function = "uart6";
777 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
778 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
781 uart7_pins_a: uart7@0 {
782 allwinner,pins = "PI20", "PI21";
783 allwinner,function = "uart7";
784 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
785 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
788 i2c0_pins_a: i2c0@0 {
789 allwinner,pins = "PB0", "PB1";
790 allwinner,function = "i2c0";
791 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
792 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
795 i2c1_pins_a: i2c1@0 {
796 allwinner,pins = "PB18", "PB19";
797 allwinner,function = "i2c1";
798 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
799 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
802 i2c2_pins_a: i2c2@0 {
803 allwinner,pins = "PB20", "PB21";
804 allwinner,function = "i2c2";
805 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
806 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
809 i2c3_pins_a: i2c3@0 {
810 allwinner,pins = "PI0", "PI1";
811 allwinner,function = "i2c3";
812 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
813 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
816 emac_pins_a: emac0@0 {
817 allwinner,pins = "PA0", "PA1", "PA2",
818 "PA3", "PA4", "PA5", "PA6",
819 "PA7", "PA8", "PA9", "PA10",
820 "PA11", "PA12", "PA13", "PA14",
822 allwinner,function = "emac";
823 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
824 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
827 clk_out_a_pins_a: clk_out_a@0 {
828 allwinner,pins = "PI12";
829 allwinner,function = "clk_out_a";
830 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
831 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
834 clk_out_b_pins_a: clk_out_b@0 {
835 allwinner,pins = "PI13";
836 allwinner,function = "clk_out_b";
837 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
838 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
841 gmac_pins_mii_a: gmac_mii@0 {
842 allwinner,pins = "PA0", "PA1", "PA2",
843 "PA3", "PA4", "PA5", "PA6",
844 "PA7", "PA8", "PA9", "PA10",
845 "PA11", "PA12", "PA13", "PA14",
847 allwinner,function = "gmac";
848 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
849 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
852 gmac_pins_rgmii_a: gmac_rgmii@0 {
853 allwinner,pins = "PA0", "PA1", "PA2",
854 "PA3", "PA4", "PA5", "PA6",
855 "PA7", "PA8", "PA10",
856 "PA11", "PA12", "PA13",
858 allwinner,function = "gmac";
860 * data lines in RGMII mode use DDR mode
861 * and need a higher signal drive strength
863 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
864 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
867 spi0_pins_a: spi0@0 {
868 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
869 allwinner,function = "spi0";
870 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
871 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
874 spi1_pins_a: spi1@0 {
875 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
876 allwinner,function = "spi1";
877 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
878 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
881 spi2_pins_a: spi2@0 {
882 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
883 allwinner,function = "spi2";
884 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
885 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
888 spi2_pins_b: spi2@1 {
889 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
890 allwinner,function = "spi2";
891 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
892 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
895 mmc0_pins_a: mmc0@0 {
896 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
897 allwinner,function = "mmc0";
898 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
899 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
902 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
903 allwinner,pins = "PH1";
904 allwinner,function = "gpio_in";
905 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
906 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
909 mmc2_pins_a: mmc2@0 {
910 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
911 allwinner,function = "mmc2";
912 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
913 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
916 mmc3_pins_a: mmc3@0 {
917 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
918 allwinner,function = "mmc3";
919 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
920 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
924 allwinner,pins = "PB3","PB4";
925 allwinner,function = "ir0";
926 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
927 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
931 allwinner,pins = "PB22","PB23";
932 allwinner,function = "ir1";
933 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
934 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
937 ps20_pins_a: ps20@0 {
938 allwinner,pins = "PI20", "PI21";
939 allwinner,function = "ps2";
940 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
941 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
944 ps21_pins_a: ps21@0 {
945 allwinner,pins = "PH12", "PH13";
946 allwinner,function = "ps2";
947 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
948 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
953 compatible = "allwinner,sun4i-a10-timer";
954 reg = <0x01c20c00 0x90>;
955 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
964 wdt: watchdog@01c20c90 {
965 compatible = "allwinner,sun4i-a10-wdt";
966 reg = <0x01c20c90 0x10>;
970 compatible = "allwinner,sun7i-a20-rtc";
971 reg = <0x01c20d00 0x20>;
972 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
976 compatible = "allwinner,sun7i-a20-pwm";
977 reg = <0x01c20e00 0xc>;
984 compatible = "allwinner,sun4i-a10-ir";
985 clocks = <&apb0_gates 6>, <&ir0_clk>;
986 clock-names = "apb", "ir";
987 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
988 reg = <0x01c21800 0x40>;
993 compatible = "allwinner,sun4i-a10-ir";
994 clocks = <&apb0_gates 7>, <&ir1_clk>;
995 clock-names = "apb", "ir";
996 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
997 reg = <0x01c21c00 0x40>;
1001 lradc: lradc@01c22800 {
1002 compatible = "allwinner,sun4i-a10-lradc-keys";
1003 reg = <0x01c22800 0x100>;
1004 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1005 status = "disabled";
1008 sid: eeprom@01c23800 {
1009 compatible = "allwinner,sun7i-a20-sid";
1010 reg = <0x01c23800 0x200>;
1014 compatible = "allwinner,sun4i-a10-ts";
1015 reg = <0x01c25000 0x100>;
1016 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1017 #thermal-sensor-cells = <0>;
1020 uart0: serial@01c28000 {
1021 compatible = "snps,dw-apb-uart";
1022 reg = <0x01c28000 0x400>;
1023 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&apb1_gates 16>;
1027 status = "disabled";
1030 uart1: serial@01c28400 {
1031 compatible = "snps,dw-apb-uart";
1032 reg = <0x01c28400 0x400>;
1033 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&apb1_gates 17>;
1037 status = "disabled";
1040 uart2: serial@01c28800 {
1041 compatible = "snps,dw-apb-uart";
1042 reg = <0x01c28800 0x400>;
1043 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&apb1_gates 18>;
1047 status = "disabled";
1050 uart3: serial@01c28c00 {
1051 compatible = "snps,dw-apb-uart";
1052 reg = <0x01c28c00 0x400>;
1053 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&apb1_gates 19>;
1057 status = "disabled";
1060 uart4: serial@01c29000 {
1061 compatible = "snps,dw-apb-uart";
1062 reg = <0x01c29000 0x400>;
1063 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&apb1_gates 20>;
1067 status = "disabled";
1070 uart5: serial@01c29400 {
1071 compatible = "snps,dw-apb-uart";
1072 reg = <0x01c29400 0x400>;
1073 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&apb1_gates 21>;
1077 status = "disabled";
1080 uart6: serial@01c29800 {
1081 compatible = "snps,dw-apb-uart";
1082 reg = <0x01c29800 0x400>;
1083 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&apb1_gates 22>;
1087 status = "disabled";
1090 uart7: serial@01c29c00 {
1091 compatible = "snps,dw-apb-uart";
1092 reg = <0x01c29c00 0x400>;
1093 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&apb1_gates 23>;
1097 status = "disabled";
1100 i2c0: i2c@01c2ac00 {
1101 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1102 reg = <0x01c2ac00 0x400>;
1103 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&apb1_gates 0>;
1105 status = "disabled";
1106 #address-cells = <1>;
1110 i2c1: i2c@01c2b000 {
1111 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1112 reg = <0x01c2b000 0x400>;
1113 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&apb1_gates 1>;
1115 status = "disabled";
1116 #address-cells = <1>;
1120 i2c2: i2c@01c2b400 {
1121 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1122 reg = <0x01c2b400 0x400>;
1123 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&apb1_gates 2>;
1125 status = "disabled";
1126 #address-cells = <1>;
1130 i2c3: i2c@01c2b800 {
1131 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1132 reg = <0x01c2b800 0x400>;
1133 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&apb1_gates 3>;
1135 status = "disabled";
1136 #address-cells = <1>;
1140 i2c4: i2c@01c2c000 {
1141 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1142 reg = <0x01c2c000 0x400>;
1143 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1144 clocks = <&apb1_gates 15>;
1145 status = "disabled";
1146 #address-cells = <1>;
1150 gmac: ethernet@01c50000 {
1151 compatible = "allwinner,sun7i-a20-gmac";
1152 reg = <0x01c50000 0x10000>;
1153 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1154 interrupt-names = "macirq";
1155 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1156 clock-names = "stmmaceth", "allwinner_gmac_tx";
1159 snps,force_sf_dma_mode;
1160 status = "disabled";
1161 #address-cells = <1>;
1166 compatible = "allwinner,sun7i-a20-hstimer";
1167 reg = <0x01c60000 0x1000>;
1168 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&ahb_gates 28>;
1175 gic: interrupt-controller@01c81000 {
1176 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1177 reg = <0x01c81000 0x1000>,
1178 <0x01c82000 0x1000>,
1179 <0x01c84000 0x2000>,
1180 <0x01c86000 0x2000>;
1181 interrupt-controller;
1182 #interrupt-cells = <3>;
1183 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1186 ps20: ps2@01c2a000 {
1187 compatible = "allwinner,sun4i-a10-ps2";
1188 reg = <0x01c2a000 0x400>;
1189 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1190 clocks = <&apb1_gates 6>;
1191 status = "disabled";
1194 ps21: ps2@01c2a400 {
1195 compatible = "allwinner,sun4i-a10-ps2";
1196 reg = <0x01c2a400 0x400>;
1197 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&apb1_gates 7>;
1199 status = "disabled";