arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/dma/sun4i-a10.h>
  48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
  49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 framebuffer-lcd0-hdmi {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  70                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  71                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
  72                                  <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 framebuffer-lcd0 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  81                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
  82                                  <&ccu CLK_DRAM_DE_BE0>;
  83                         status = "disabled";
  84                 };
  85
  86                 framebuffer-lcd0-tve0 {
  87                         compatible = "allwinner,simple-framebuffer",
  88                                      "simple-framebuffer";
  89                         allwinner,pipeline = "de_be0-lcd0-tve0";
  90                         clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
  91                                  <&ccu CLK_AHB_DE_BE0>,
  92                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
  93                                  <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
  94                         status = "disabled";
  95                 };
  96         };
  97
  98         cpus {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 960000  1400000
 111                                 912000  1400000
 112                                 864000  1300000
 113                                 720000  1200000
 114                                 528000  1100000
 115                                 312000  1000000
 116                                 144000  1000000
 117                                 >;
 118                         #cooling-cells = <2>;
 119                 };
 120
 121                 cpu1: cpu@1 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         reg = <1>;
 125                         clocks = <&ccu CLK_CPU>;
 126                         clock-latency = <244144>; /* 8 32k periods */
 127                         operating-points = <
 128                                 /* kHz    uV */
 129                                 960000  1400000
 130                                 912000  1400000
 131                                 864000  1300000
 132                                 720000  1200000
 133                                 528000  1100000
 134                                 312000  1000000
 135                                 144000  1000000
 136                                 >;
 137                         #cooling-cells = <2>;
 138                 };
 139         };
 140
 141         thermal-zones {
 142                 cpu_thermal {
 143                         /* milliseconds */
 144                         polling-delay-passive = <250>;
 145                         polling-delay = <1000>;
 146                         thermal-sensors = <&rtp>;
 147
 148                         cooling-maps {
 149                                 map0 {
 150                                         trip = <&cpu_alert0>;
 151                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 152                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 153                                 };
 154                         };
 155
 156                         trips {
 157                                 cpu_alert0: cpu_alert0 {
 158                                         /* milliCelsius */
 159                                         temperature = <75000>;
 160                                         hysteresis = <2000>;
 161                                         type = "passive";
 162                                 };
 163
 164                                 cpu_crit: cpu_crit {
 165                                         /* milliCelsius */
 166                                         temperature = <100000>;
 167                                         hysteresis = <2000>;
 168                                         type = "critical";
 169                                 };
 170                         };
 171                 };
 172         };
 173
 174         reserved-memory {
 175                 #address-cells = <1>;
 176                 #size-cells = <1>;
 177                 ranges;
 178
 179                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 180                 default-pool {
 181                         compatible = "shared-dma-pool";
 182                         size = <0x6000000>;
 183                         alloc-ranges = <0x4a000000 0x6000000>;
 184                         reusable;
 185                         linux,cma-default;
 186                 };
 187         };
 188
 189         timer {
 190                 compatible = "arm,armv7-timer";
 191                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 193                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 194                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 195         };
 196
 197         pmu {
 198                 compatible = "arm,cortex-a7-pmu";
 199                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 201         };
 202
 203         clocks {
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges;
 207
 208                 osc24M: clk-24M {
 209                         #clock-cells = <0>;
 210                         compatible = "fixed-clock";
 211                         clock-frequency = <24000000>;
 212                         clock-output-names = "osc24M";
 213                 };
 214
 215                 osc32k: clk-32k {
 216                         #clock-cells = <0>;
 217                         compatible = "fixed-clock";
 218                         clock-frequency = <32768>;
 219                         clock-output-names = "osc32k";
 220                 };
 221
 222                 /*
 223                  * The following two are dummy clocks, placeholders
 224                  * used in the gmac_tx clock. The gmac driver will
 225                  * choose one parent depending on the PHY interface
 226                  * mode, using clk_set_rate auto-reparenting.
 227                  *
 228                  * The actual TX clock rate is not controlled by the
 229                  * gmac_tx clock.
 230                  */
 231                 mii_phy_tx_clk: clk-mii-phy-tx {
 232                         #clock-cells = <0>;
 233                         compatible = "fixed-clock";
 234                         clock-frequency = <25000000>;
 235                         clock-output-names = "mii_phy_tx";
 236                 };
 237
 238                 gmac_int_tx_clk: clk-gmac-int-tx {
 239                         #clock-cells = <0>;
 240                         compatible = "fixed-clock";
 241                         clock-frequency = <125000000>;
 242                         clock-output-names = "gmac_int_tx";
 243                 };
 244
 245                 gmac_tx_clk: clk@1c20164 {
 246                         #clock-cells = <0>;
 247                         compatible = "allwinner,sun7i-a20-gmac-clk";
 248                         reg = <0x01c20164 0x4>;
 249                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 250                         clock-output-names = "gmac_tx";
 251                 };
 252         };
 253
 254
 255         de: display-engine {
 256                 compatible = "allwinner,sun7i-a20-display-engine";
 257                 allwinner,pipelines = <&fe0>, <&fe1>;
 258                 status = "disabled";
 259         };
 260
 261         soc {
 262                 compatible = "simple-bus";
 263                 #address-cells = <1>;
 264                 #size-cells = <1>;
 265                 ranges;
 266
 267                 system-control@1c00000 {
 268                         compatible = "allwinner,sun7i-a20-system-control",
 269                                      "allwinner,sun4i-a10-system-control";
 270                         reg = <0x01c00000 0x30>;
 271                         #address-cells = <1>;
 272                         #size-cells = <1>;
 273                         ranges;
 274
 275                         sram_a: sram@0 {
 276                                 compatible = "mmio-sram";
 277                                 reg = <0x00000000 0xc000>;
 278                                 #address-cells = <1>;
 279                                 #size-cells = <1>;
 280                                 ranges = <0 0x00000000 0xc000>;
 281
 282                                 emac_sram: sram-section@8000 {
 283                                         compatible = "allwinner,sun7i-a20-sram-a3-a4",
 284                                                      "allwinner,sun4i-a10-sram-a3-a4";
 285                                         reg = <0x8000 0x4000>;
 286                                         status = "disabled";
 287                                 };
 288                         };
 289
 290                         sram_d: sram@10000 {
 291                                 compatible = "mmio-sram";
 292                                 reg = <0x00010000 0x1000>;
 293                                 #address-cells = <1>;
 294                                 #size-cells = <1>;
 295                                 ranges = <0 0x00010000 0x1000>;
 296
 297                                 otg_sram: sram-section@0 {
 298                                         compatible = "allwinner,sun7i-a20-sram-d",
 299                                                      "allwinner,sun4i-a10-sram-d";
 300                                         reg = <0x0000 0x1000>;
 301                                         status = "disabled";
 302                                 };
 303                         };
 304
 305                         sram_c: sram@1d00000 {
 306                                 compatible = "mmio-sram";
 307                                 reg = <0x01d00000 0xd0000>;
 308                                 #address-cells = <1>;
 309                                 #size-cells = <1>;
 310                                 ranges = <0 0x01d00000 0xd0000>;
 311
 312                                 ve_sram: sram-section@0 {
 313                                         compatible = "allwinner,sun7i-a20-sram-c1",
 314                                                      "allwinner,sun4i-a10-sram-c1";
 315                                         reg = <0x000000 0x80000>;
 316                                 };
 317                         };
 318                 };
 319
 320                 nmi_intc: interrupt-controller@1c00030 {
 321                         compatible = "allwinner,sun7i-a20-sc-nmi";
 322                         interrupt-controller;
 323                         #interrupt-cells = <2>;
 324                         reg = <0x01c00030 0x0c>;
 325                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 326                 };
 327
 328                 dma: dma-controller@1c02000 {
 329                         compatible = "allwinner,sun4i-a10-dma";
 330                         reg = <0x01c02000 0x1000>;
 331                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&ccu CLK_AHB_DMA>;
 333                         #dma-cells = <2>;
 334                 };
 335
 336                 nfc: nand-controller@1c03000 {
 337                         compatible = "allwinner,sun4i-a10-nand";
 338                         reg = <0x01c03000 0x1000>;
 339                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 341                         clock-names = "ahb", "mod";
 342                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 343                         dma-names = "rxtx";
 344                         status = "disabled";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                 };
 348
 349                 spi0: spi@1c05000 {
 350                         compatible = "allwinner,sun4i-a10-spi";
 351                         reg = <0x01c05000 0x1000>;
 352                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 353                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 354                         clock-names = "ahb", "mod";
 355                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 356                                <&dma SUN4I_DMA_DEDICATED 26>;
 357                         dma-names = "rx", "tx";
 358                         status = "disabled";
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         num-cs = <4>;
 362                 };
 363
 364                 spi1: spi@1c06000 {
 365                         compatible = "allwinner,sun4i-a10-spi";
 366                         reg = <0x01c06000 0x1000>;
 367                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 369                         clock-names = "ahb", "mod";
 370                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 371                                <&dma SUN4I_DMA_DEDICATED 8>;
 372                         dma-names = "rx", "tx";
 373                         status = "disabled";
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         num-cs = <1>;
 377                 };
 378
 379                 csi0: csi@1c09000 {
 380                         compatible = "allwinner,sun7i-a20-csi0";
 381                         reg = <0x01c09000 0x1000>;
 382                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
 384                                  <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
 385                         clock-names = "bus", "mod", "isp", "ram";
 386                         resets = <&ccu RST_CSI0>;
 387                         status = "disabled";
 388                 };
 389
 390                 emac: ethernet@1c0b000 {
 391                         compatible = "allwinner,sun4i-a10-emac";
 392                         reg = <0x01c0b000 0x1000>;
 393                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&ccu CLK_AHB_EMAC>;
 395                         allwinner,sram = <&emac_sram 1>;
 396                         status = "disabled";
 397                 };
 398
 399                 mdio: mdio@1c0b080 {
 400                         compatible = "allwinner,sun4i-a10-mdio";
 401                         reg = <0x01c0b080 0x14>;
 402                         status = "disabled";
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                 };
 406
 407                 tcon0: lcd-controller@1c0c000 {
 408                         compatible = "allwinner,sun7i-a20-tcon";
 409                         reg = <0x01c0c000 0x1000>;
 410                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 411                         resets = <&ccu RST_TCON0>;
 412                         reset-names = "lcd";
 413                         clocks = <&ccu CLK_AHB_LCD0>,
 414                                  <&ccu CLK_TCON0_CH0>,
 415                                  <&ccu CLK_TCON0_CH1>;
 416                         clock-names = "ahb",
 417                                       "tcon-ch0",
 418                                       "tcon-ch1";
 419                         clock-output-names = "tcon0-pixel-clock";
 420                         #clock-cells = <0>;
 421                         dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 422
 423                         ports {
 424                                 #address-cells = <1>;
 425                                 #size-cells = <0>;
 426
 427                                 tcon0_in: port@0 {
 428                                         #address-cells = <1>;
 429                                         #size-cells = <0>;
 430                                         reg = <0>;
 431
 432                                         tcon0_in_be0: endpoint@0 {
 433                                                 reg = <0>;
 434                                                 remote-endpoint = <&be0_out_tcon0>;
 435                                         };
 436
 437                                         tcon0_in_be1: endpoint@1 {
 438                                                 reg = <1>;
 439                                                 remote-endpoint = <&be1_out_tcon0>;
 440                                         };
 441                                 };
 442
 443                                 tcon0_out: port@1 {
 444                                         #address-cells = <1>;
 445                                         #size-cells = <0>;
 446                                         reg = <1>;
 447
 448                                         tcon0_out_hdmi: endpoint@1 {
 449                                                 reg = <1>;
 450                                                 remote-endpoint = <&hdmi_in_tcon0>;
 451                                                 allwinner,tcon-channel = <1>;
 452                                         };
 453                                 };
 454                         };
 455                 };
 456
 457                 tcon1: lcd-controller@1c0d000 {
 458                         compatible = "allwinner,sun7i-a20-tcon";
 459                         reg = <0x01c0d000 0x1000>;
 460                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 461                         resets = <&ccu RST_TCON1>;
 462                         reset-names = "lcd";
 463                         clocks = <&ccu CLK_AHB_LCD1>,
 464                                  <&ccu CLK_TCON1_CH0>,
 465                                  <&ccu CLK_TCON1_CH1>;
 466                         clock-names = "ahb",
 467                                       "tcon-ch0",
 468                                       "tcon-ch1";
 469                         clock-output-names = "tcon1-pixel-clock";
 470                         #clock-cells = <0>;
 471                         dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 472
 473                         ports {
 474                                 #address-cells = <1>;
 475                                 #size-cells = <0>;
 476
 477                                 tcon1_in: port@0 {
 478                                         #address-cells = <1>;
 479                                         #size-cells = <0>;
 480                                         reg = <0>;
 481
 482                                         tcon1_in_be0: endpoint@0 {
 483                                                 reg = <0>;
 484                                                 remote-endpoint = <&be0_out_tcon1>;
 485                                         };
 486
 487                                         tcon1_in_be1: endpoint@1 {
 488                                                 reg = <1>;
 489                                                 remote-endpoint = <&be1_out_tcon1>;
 490                                         };
 491                                 };
 492
 493                                 tcon1_out: port@1 {
 494                                         #address-cells = <1>;
 495                                         #size-cells = <0>;
 496                                         reg = <1>;
 497
 498                                         tcon1_out_hdmi: endpoint@1 {
 499                                                 reg = <1>;
 500                                                 remote-endpoint = <&hdmi_in_tcon1>;
 501                                                 allwinner,tcon-channel = <1>;
 502                                         };
 503                                 };
 504                         };
 505                 };
 506
 507                 video-codec@1c0e000 {
 508                         compatible = "allwinner,sun7i-a20-video-engine";
 509                         reg = <0x01c0e000 0x1000>;
 510                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 511                                  <&ccu CLK_DRAM_VE>;
 512                         clock-names = "ahb", "mod", "ram";
 513                         resets = <&ccu RST_VE>;
 514                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 515                         allwinner,sram = <&ve_sram 1>;
 516                 };
 517
 518                 mmc0: mmc@1c0f000 {
 519                         compatible = "allwinner,sun7i-a20-mmc";
 520                         reg = <0x01c0f000 0x1000>;
 521                         clocks = <&ccu CLK_AHB_MMC0>,
 522                                  <&ccu CLK_MMC0>,
 523                                  <&ccu CLK_MMC0_OUTPUT>,
 524                                  <&ccu CLK_MMC0_SAMPLE>;
 525                         clock-names = "ahb",
 526                                       "mmc",
 527                                       "output",
 528                                       "sample";
 529                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 530                         pinctrl-names = "default";
 531                         pinctrl-0 = <&mmc0_pins>;
 532                         status = "disabled";
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                 };
 536
 537                 mmc1: mmc@1c10000 {
 538                         compatible = "allwinner,sun7i-a20-mmc";
 539                         reg = <0x01c10000 0x1000>;
 540                         clocks = <&ccu CLK_AHB_MMC1>,
 541                                  <&ccu CLK_MMC1>,
 542                                  <&ccu CLK_MMC1_OUTPUT>,
 543                                  <&ccu CLK_MMC1_SAMPLE>;
 544                         clock-names = "ahb",
 545                                       "mmc",
 546                                       "output",
 547                                       "sample";
 548                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 549                         status = "disabled";
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                 };
 553
 554                 mmc2: mmc@1c11000 {
 555                         compatible = "allwinner,sun7i-a20-mmc";
 556                         reg = <0x01c11000 0x1000>;
 557                         clocks = <&ccu CLK_AHB_MMC2>,
 558                                  <&ccu CLK_MMC2>,
 559                                  <&ccu CLK_MMC2_OUTPUT>,
 560                                  <&ccu CLK_MMC2_SAMPLE>;
 561                         clock-names = "ahb",
 562                                       "mmc",
 563                                       "output",
 564                                       "sample";
 565                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 566                         pinctrl-names = "default";
 567                         pinctrl-0 = <&mmc2_pins>;
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 mmc3: mmc@1c12000 {
 574                         compatible = "allwinner,sun7i-a20-mmc";
 575                         reg = <0x01c12000 0x1000>;
 576                         clocks = <&ccu CLK_AHB_MMC3>,
 577                                  <&ccu CLK_MMC3>,
 578                                  <&ccu CLK_MMC3_OUTPUT>,
 579                                  <&ccu CLK_MMC3_SAMPLE>;
 580                         clock-names = "ahb",
 581                                       "mmc",
 582                                       "output",
 583                                       "sample";
 584                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 585                         pinctrl-names = "default";
 586                         pinctrl-0 = <&mmc3_pins>;
 587                         status = "disabled";
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                 };
 591
 592                 usb_otg: usb@1c13000 {
 593                         compatible = "allwinner,sun4i-a10-musb";
 594                         reg = <0x01c13000 0x0400>;
 595                         clocks = <&ccu CLK_AHB_OTG>;
 596                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 597                         interrupt-names = "mc";
 598                         phys = <&usbphy 0>;
 599                         phy-names = "usb";
 600                         extcon = <&usbphy 0>;
 601                         allwinner,sram = <&otg_sram 1>;
 602                         dr_mode = "otg";
 603                         status = "disabled";
 604                 };
 605
 606                 usbphy: phy@1c13400 {
 607                         #phy-cells = <1>;
 608                         compatible = "allwinner,sun7i-a20-usb-phy";
 609                         reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
 610                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 611                         clocks = <&ccu CLK_USB_PHY>;
 612                         clock-names = "usb_phy";
 613                         resets = <&ccu RST_USB_PHY0>,
 614                                  <&ccu RST_USB_PHY1>,
 615                                  <&ccu RST_USB_PHY2>;
 616                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 617                         status = "disabled";
 618                 };
 619
 620                 ehci0: usb@1c14000 {
 621                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 622                         reg = <0x01c14000 0x100>;
 623                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 624                         clocks = <&ccu CLK_AHB_EHCI0>;
 625                         phys = <&usbphy 1>;
 626                         status = "disabled";
 627                 };
 628
 629                 ohci0: usb@1c14400 {
 630                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 631                         reg = <0x01c14400 0x100>;
 632                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 633                         clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 634                         phys = <&usbphy 1>;
 635                         status = "disabled";
 636                 };
 637
 638                 crypto: crypto-engine@1c15000 {
 639                         compatible = "allwinner,sun7i-a20-crypto",
 640                                      "allwinner,sun4i-a10-crypto";
 641                         reg = <0x01c15000 0x1000>;
 642                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 643                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 644                         clock-names = "ahb", "mod";
 645                 };
 646
 647                 hdmi: hdmi@1c16000 {
 648                         compatible = "allwinner,sun7i-a20-hdmi",
 649                                      "allwinner,sun5i-a10s-hdmi";
 650                         reg = <0x01c16000 0x1000>;
 651                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 652                         clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
 653                                  <&ccu CLK_PLL_VIDEO0_2X>,
 654                                  <&ccu CLK_PLL_VIDEO1_2X>;
 655                         clock-names = "ahb", "mod", "pll-0", "pll-1";
 656                         dmas = <&dma SUN4I_DMA_NORMAL 16>,
 657                                <&dma SUN4I_DMA_NORMAL 16>,
 658                                <&dma SUN4I_DMA_DEDICATED 24>;
 659                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 660                         status = "disabled";
 661
 662                         ports {
 663                                 #address-cells = <1>;
 664                                 #size-cells = <0>;
 665
 666                                 hdmi_in: port@0 {
 667                                         #address-cells = <1>;
 668                                         #size-cells = <0>;
 669                                         reg = <0>;
 670
 671                                         hdmi_in_tcon0: endpoint@0 {
 672                                                 reg = <0>;
 673                                                 remote-endpoint = <&tcon0_out_hdmi>;
 674                                         };
 675
 676                                         hdmi_in_tcon1: endpoint@1 {
 677                                                 reg = <1>;
 678                                                 remote-endpoint = <&tcon1_out_hdmi>;
 679                                         };
 680                                 };
 681
 682                                 hdmi_out: port@1 {
 683                                         reg = <1>;
 684                                 };
 685                         };
 686                 };
 687
 688                 spi2: spi@1c17000 {
 689                         compatible = "allwinner,sun4i-a10-spi";
 690                         reg = <0x01c17000 0x1000>;
 691                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 692                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 693                         clock-names = "ahb", "mod";
 694                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 695                                <&dma SUN4I_DMA_DEDICATED 28>;
 696                         dma-names = "rx", "tx";
 697                         status = "disabled";
 698                         #address-cells = <1>;
 699                         #size-cells = <0>;
 700                         num-cs = <1>;
 701                 };
 702
 703                 ahci: sata@1c18000 {
 704                         compatible = "allwinner,sun4i-a10-ahci";
 705                         reg = <0x01c18000 0x1000>;
 706                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 707                         clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
 708                         status = "disabled";
 709                 };
 710
 711                 ehci1: usb@1c1c000 {
 712                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 713                         reg = <0x01c1c000 0x100>;
 714                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 715                         clocks = <&ccu CLK_AHB_EHCI1>;
 716                         phys = <&usbphy 2>;
 717                         status = "disabled";
 718                 };
 719
 720                 ohci1: usb@1c1c400 {
 721                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 722                         reg = <0x01c1c400 0x100>;
 723                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 725                         phys = <&usbphy 2>;
 726                         status = "disabled";
 727                 };
 728
 729                 spi3: spi@1c1f000 {
 730                         compatible = "allwinner,sun4i-a10-spi";
 731                         reg = <0x01c1f000 0x1000>;
 732                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 733                         clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 734                         clock-names = "ahb", "mod";
 735                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 736                                <&dma SUN4I_DMA_DEDICATED 30>;
 737                         dma-names = "rx", "tx";
 738                         status = "disabled";
 739                         #address-cells = <1>;
 740                         #size-cells = <0>;
 741                         num-cs = <1>;
 742                 };
 743
 744                 ccu: clock@1c20000 {
 745                         compatible = "allwinner,sun7i-a20-ccu";
 746                         reg = <0x01c20000 0x400>;
 747                         clocks = <&osc24M>, <&osc32k>;
 748                         clock-names = "hosc", "losc";
 749                         #clock-cells = <1>;
 750                         #reset-cells = <1>;
 751                 };
 752
 753                 pio: pinctrl@1c20800 {
 754                         compatible = "allwinner,sun7i-a20-pinctrl";
 755                         reg = <0x01c20800 0x400>;
 756                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 757                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 758                         clock-names = "apb", "hosc", "losc";
 759                         gpio-controller;
 760                         interrupt-controller;
 761                         #interrupt-cells = <3>;
 762                         #gpio-cells = <3>;
 763
 764                         /omit-if-no-ref/
 765                         can_pa_pins: can-pa-pins {
 766                                 pins = "PA16", "PA17";
 767                                 function = "can";
 768                         };
 769
 770                         /omit-if-no-ref/
 771                         can_ph_pins: can-ph-pins {
 772                                 pins = "PH20", "PH21";
 773                                 function = "can";
 774                         };
 775
 776                         /omit-if-no-ref/
 777                         clk_out_a_pin: clk-out-a-pin {
 778                                 pins = "PI12";
 779                                 function = "clk_out_a";
 780                         };
 781
 782                         /omit-if-no-ref/
 783                         clk_out_b_pin: clk-out-b-pin {
 784                                 pins = "PI13";
 785                                 function = "clk_out_b";
 786                         };
 787
 788                         /omit-if-no-ref/
 789                         csi0_8bits_pins: csi-8bits-pins {
 790                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 791                                        "PE6", "PE7", "PE8", "PE9", "PE10",
 792                                        "PE11";
 793                                 function = "csi0";
 794                         };
 795
 796                         /omit-if-no-ref/
 797                         csi0_clk_pin: csi-clk-pin {
 798                                 pins = "PE1";
 799                                 function = "csi0";
 800                         };
 801
 802                         /omit-if-no-ref/
 803                         emac_pa_pins: emac-pa-pins {
 804                                 pins = "PA0", "PA1", "PA2",
 805                                        "PA3", "PA4", "PA5", "PA6",
 806                                        "PA7", "PA8", "PA9", "PA10",
 807                                        "PA11", "PA12", "PA13", "PA14",
 808                                        "PA15", "PA16";
 809                                 function = "emac";
 810                         };
 811
 812                         /omit-if-no-ref/
 813                         emac_ph_pins: emac-ph-pins {
 814                                 pins = "PH8", "PH9", "PH10", "PH11",
 815                                        "PH14", "PH15", "PH16", "PH17",
 816                                        "PH18", "PH19", "PH20", "PH21",
 817                                        "PH22", "PH23", "PH24", "PH25",
 818                                        "PH26";
 819                                 function = "emac";
 820                         };
 821
 822                         /omit-if-no-ref/
 823                         gmac_mii_pins: gmac-mii-pins {
 824                                 pins = "PA0", "PA1", "PA2",
 825                                        "PA3", "PA4", "PA5", "PA6",
 826                                        "PA7", "PA8", "PA9", "PA10",
 827                                        "PA11", "PA12", "PA13", "PA14",
 828                                        "PA15", "PA16";
 829                                 function = "gmac";
 830                         };
 831
 832                         /omit-if-no-ref/
 833                         gmac_rgmii_pins: gmac-rgmii-pins {
 834                                 pins = "PA0", "PA1", "PA2",
 835                                        "PA3", "PA4", "PA5", "PA6",
 836                                         "PA7", "PA8", "PA10",
 837                                        "PA11", "PA12", "PA13",
 838                                        "PA15", "PA16";
 839                                 function = "gmac";
 840                                 /*
 841                                  * data lines in RGMII mode use DDR mode
 842                                  * and need a higher signal drive strength
 843                                  */
 844                                 drive-strength = <40>;
 845                         };
 846
 847                         /omit-if-no-ref/
 848                         i2c0_pins: i2c0-pins {
 849                                 pins = "PB0", "PB1";
 850                                 function = "i2c0";
 851                         };
 852
 853                         /omit-if-no-ref/
 854                         i2c1_pins: i2c1-pins {
 855                                 pins = "PB18", "PB19";
 856                                 function = "i2c1";
 857                         };
 858
 859                         /omit-if-no-ref/
 860                         i2c2_pins: i2c2-pins {
 861                                 pins = "PB20", "PB21";
 862                                 function = "i2c2";
 863                         };
 864
 865                         /omit-if-no-ref/
 866                         i2c3_pins: i2c3-pins {
 867                                 pins = "PI0", "PI1";
 868                                 function = "i2c3";
 869                         };
 870
 871                         /omit-if-no-ref/
 872                         ir0_rx_pin: ir0-rx-pin {
 873                                 pins = "PB4";
 874                                 function = "ir0";
 875                         };
 876
 877                         /omit-if-no-ref/
 878                         ir0_tx_pin: ir0-tx-pin {
 879                                 pins = "PB3";
 880                                 function = "ir0";
 881                         };
 882
 883                         /omit-if-no-ref/
 884                         ir1_rx_pin: ir1-rx-pin {
 885                                 pins = "PB23";
 886                                 function = "ir1";
 887                         };
 888
 889                         /omit-if-no-ref/
 890                         ir1_tx_pin: ir1-tx-pin {
 891                                 pins = "PB22";
 892                                 function = "ir1";
 893                         };
 894
 895                         /omit-if-no-ref/
 896                         mmc0_pins: mmc0-pins {
 897                                 pins = "PF0", "PF1", "PF2",
 898                                        "PF3", "PF4", "PF5";
 899                                 function = "mmc0";
 900                                 drive-strength = <30>;
 901                                 bias-pull-up;
 902                         };
 903
 904                         /omit-if-no-ref/
 905                         mmc2_pins: mmc2-pins {
 906                                 pins = "PC6", "PC7", "PC8",
 907                                        "PC9", "PC10", "PC11";
 908                                 function = "mmc2";
 909                                 drive-strength = <30>;
 910                                 bias-pull-up;
 911                         };
 912
 913                         /omit-if-no-ref/
 914                         mmc3_pins: mmc3-pins {
 915                                 pins = "PI4", "PI5", "PI6",
 916                                        "PI7", "PI8", "PI9";
 917                                 function = "mmc3";
 918                                 drive-strength = <30>;
 919                                 bias-pull-up;
 920                         };
 921
 922                         /omit-if-no-ref/
 923                         ps2_0_pins: ps2-0-pins {
 924                                 pins = "PI20", "PI21";
 925                                 function = "ps2";
 926                         };
 927
 928                         /omit-if-no-ref/
 929                         ps2_1_ph_pins: ps2-1-ph-pins {
 930                                 pins = "PH12", "PH13";
 931                                 function = "ps2";
 932                         };
 933
 934                         /omit-if-no-ref/
 935                         pwm0_pin: pwm0-pin {
 936                                 pins = "PB2";
 937                                 function = "pwm";
 938                         };
 939
 940                         /omit-if-no-ref/
 941                         pwm1_pin: pwm1-pin {
 942                                 pins = "PI3";
 943                                 function = "pwm";
 944                         };
 945
 946                         /omit-if-no-ref/
 947                         spdif_tx_pin: spdif-tx-pin {
 948                                 pins = "PB13";
 949                                 function = "spdif";
 950                                 bias-pull-up;
 951                         };
 952
 953                         /omit-if-no-ref/
 954                         spi0_pi_pins: spi0-pi-pins {
 955                                 pins = "PI11", "PI12", "PI13";
 956                                 function = "spi0";
 957                         };
 958
 959                         /omit-if-no-ref/
 960                         spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 961                                 pins = "PI10";
 962                                 function = "spi0";
 963                         };
 964
 965                         /omit-if-no-ref/
 966                         spi0_cs1_pi_pin: spi0-cs1-pi-pin {
 967                                 pins = "PI14";
 968                                 function = "spi0";
 969                         };
 970
 971                         /omit-if-no-ref/
 972                         spi1_pi_pins: spi1-pi-pins {
 973                                 pins = "PI17", "PI18", "PI19";
 974                                 function = "spi1";
 975                         };
 976
 977                         /omit-if-no-ref/
 978                         spi1_cs0_pi_pin: spi1-cs0-pi-pin {
 979                                 pins = "PI16";
 980                                 function = "spi1";
 981                         };
 982
 983                         /omit-if-no-ref/
 984                         spi2_pb_pins: spi2-pb-pins {
 985                                 pins = "PB15", "PB16", "PB17";
 986                                 function = "spi2";
 987                         };
 988
 989                         /omit-if-no-ref/
 990                         spi2_cs0_pb_pin: spi2-cs0-pb-pin {
 991                                 pins = "PB14";
 992                                 function = "spi2";
 993                         };
 994
 995                         /omit-if-no-ref/
 996                         spi2_pc_pins: spi2-pc-pins {
 997                                 pins = "PC20", "PC21", "PC22";
 998                                 function = "spi2";
 999                         };
1000
1001                         /omit-if-no-ref/
1002                         spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1003                                 pins = "PC19";
1004                                 function = "spi2";
1005                         };
1006
1007                         /omit-if-no-ref/
1008                         uart0_pb_pins: uart0-pb-pins {
1009                                 pins = "PB22", "PB23";
1010                                 function = "uart0";
1011                         };
1012
1013                         /omit-if-no-ref/
1014                         uart0_pf_pins: uart0-pf-pins {
1015                                 pins = "PF2", "PF4";
1016                                 function = "uart0";
1017                         };
1018
1019                         /omit-if-no-ref/
1020                         uart1_pa_pins: uart1-pa-pins {
1021                                 pins = "PA10", "PA11";
1022                                 function = "uart1";
1023                         };
1024
1025                         /omit-if-no-ref/
1026                         uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1027                                 pins = "PA12", "PA13";
1028                                 function = "uart1";
1029                         };
1030
1031                         /omit-if-no-ref/
1032                         uart2_pa_pins: uart2-pa-pins {
1033                                 pins = "PA2", "PA3";
1034                                 function = "uart2";
1035                         };
1036
1037                         /omit-if-no-ref/
1038                         uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1039                                 pins = "PA0", "PA1";
1040                                 function = "uart2";
1041                         };
1042
1043                         /omit-if-no-ref/
1044                         uart2_pi_pins: uart2-pi-pins {
1045                                 pins = "PI18", "PI19";
1046                                 function = "uart2";
1047                         };
1048
1049                         /omit-if-no-ref/
1050                         uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1051                                 pins = "PI16", "PI17";
1052                                 function = "uart2";
1053                         };
1054
1055                         /omit-if-no-ref/
1056                         uart3_pg_pins: uart3-pg-pins {
1057                                 pins = "PG6", "PG7";
1058                                 function = "uart3";
1059                         };
1060
1061                         /omit-if-no-ref/
1062                         uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1063                                 pins = "PG8", "PG9";
1064                                 function = "uart3";
1065                         };
1066
1067                         /omit-if-no-ref/
1068                         uart3_ph_pins: uart3-ph-pins {
1069                                 pins = "PH0", "PH1";
1070                                 function = "uart3";
1071                         };
1072
1073                         /omit-if-no-ref/
1074                         uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1075                                 pins = "PH2", "PH3";
1076                                 function = "uart3";
1077                         };
1078
1079                         /omit-if-no-ref/
1080                         uart4_pg_pins: uart4-pg-pins {
1081                                 pins = "PG10", "PG11";
1082                                 function = "uart4";
1083                         };
1084
1085                         /omit-if-no-ref/
1086                         uart4_ph_pins: uart4-ph-pins {
1087                                 pins = "PH4", "PH5";
1088                                 function = "uart4";
1089                         };
1090
1091                         /omit-if-no-ref/
1092                         uart5_ph_pins: uart5-ph-pins {
1093                                 pins = "PH6", "PH7";
1094                                 function = "uart5";
1095                         };
1096
1097                         /omit-if-no-ref/
1098                         uart5_pi_pins: uart5-pi-pins {
1099                                 pins = "PI10", "PI11";
1100                                 function = "uart5";
1101                         };
1102
1103                         /omit-if-no-ref/
1104                         uart6_pa_pins: uart6-pa-pins {
1105                                 pins = "PA12", "PA13";
1106                                 function = "uart6";
1107                         };
1108
1109                         /omit-if-no-ref/
1110                         uart6_pi_pins: uart6-pi-pins {
1111                                 pins = "PI12", "PI13";
1112                                 function = "uart6";
1113                         };
1114
1115                         /omit-if-no-ref/
1116                         uart7_pa_pins: uart7-pa-pins {
1117                                 pins = "PA14", "PA15";
1118                                 function = "uart7";
1119                         };
1120
1121                         /omit-if-no-ref/
1122                         uart7_pi_pins: uart7-pi-pins {
1123                                 pins = "PI20", "PI21";
1124                                 function = "uart7";
1125                         };
1126                 };
1127
1128                 timer@1c20c00 {
1129                         compatible = "allwinner,sun4i-a10-timer";
1130                         reg = <0x01c20c00 0x90>;
1131                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1132                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1133                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1134                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1135                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1136                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1137                         clocks = <&osc24M>;
1138                 };
1139
1140                 wdt: watchdog@1c20c90 {
1141                         compatible = "allwinner,sun4i-a10-wdt";
1142                         reg = <0x01c20c90 0x10>;
1143                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1144                         clocks = <&osc24M>;
1145                 };
1146
1147                 rtc: rtc@1c20d00 {
1148                         compatible = "allwinner,sun7i-a20-rtc";
1149                         reg = <0x01c20d00 0x20>;
1150                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1151                 };
1152
1153                 pwm: pwm@1c20e00 {
1154                         compatible = "allwinner,sun7i-a20-pwm";
1155                         reg = <0x01c20e00 0xc>;
1156                         clocks = <&osc24M>;
1157                         #pwm-cells = <3>;
1158                         status = "disabled";
1159                 };
1160
1161                 spdif: spdif@1c21000 {
1162                         #sound-dai-cells = <0>;
1163                         compatible = "allwinner,sun4i-a10-spdif";
1164                         reg = <0x01c21000 0x400>;
1165                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1166                         clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1167                         clock-names = "apb", "spdif";
1168                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1169                                <&dma SUN4I_DMA_NORMAL 2>;
1170                         dma-names = "rx", "tx";
1171                         status = "disabled";
1172                 };
1173
1174                 ir0: ir@1c21800 {
1175                         compatible = "allwinner,sun4i-a10-ir";
1176                         clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1177                         clock-names = "apb", "ir";
1178                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1179                         reg = <0x01c21800 0x40>;
1180                         status = "disabled";
1181                 };
1182
1183                 ir1: ir@1c21c00 {
1184                         compatible = "allwinner,sun4i-a10-ir";
1185                         clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1186                         clock-names = "apb", "ir";
1187                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1188                         reg = <0x01c21c00 0x40>;
1189                         status = "disabled";
1190                 };
1191
1192                 i2s1: i2s@1c22000 {
1193                         #sound-dai-cells = <0>;
1194                         compatible = "allwinner,sun4i-a10-i2s";
1195                         reg = <0x01c22000 0x400>;
1196                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1197                         clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1198                         clock-names = "apb", "mod";
1199                         dmas = <&dma SUN4I_DMA_NORMAL 4>,
1200                                <&dma SUN4I_DMA_NORMAL 4>;
1201                         dma-names = "rx", "tx";
1202                         status = "disabled";
1203                 };
1204
1205                 i2s0: i2s@1c22400 {
1206                         #sound-dai-cells = <0>;
1207                         compatible = "allwinner,sun4i-a10-i2s";
1208                         reg = <0x01c22400 0x400>;
1209                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1210                         clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1211                         clock-names = "apb", "mod";
1212                         dmas = <&dma SUN4I_DMA_NORMAL 3>,
1213                                <&dma SUN4I_DMA_NORMAL 3>;
1214                         dma-names = "rx", "tx";
1215                         status = "disabled";
1216                 };
1217
1218                 lradc: lradc@1c22800 {
1219                         compatible = "allwinner,sun4i-a10-lradc-keys";
1220                         reg = <0x01c22800 0x100>;
1221                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1222                         status = "disabled";
1223                 };
1224
1225                 codec: codec@1c22c00 {
1226                         #sound-dai-cells = <0>;
1227                         compatible = "allwinner,sun7i-a20-codec";
1228                         reg = <0x01c22c00 0x40>;
1229                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1230                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1231                         clock-names = "apb", "codec";
1232                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1233                                <&dma SUN4I_DMA_NORMAL 19>;
1234                         dma-names = "rx", "tx";
1235                         status = "disabled";
1236                 };
1237
1238                 sid: eeprom@1c23800 {
1239                         compatible = "allwinner,sun7i-a20-sid";
1240                         reg = <0x01c23800 0x200>;
1241                 };
1242
1243                 i2s2: i2s@1c24400 {
1244                         #sound-dai-cells = <0>;
1245                         compatible = "allwinner,sun4i-a10-i2s";
1246                         reg = <0x01c24400 0x400>;
1247                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1248                         clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1249                         clock-names = "apb", "mod";
1250                         dmas = <&dma SUN4I_DMA_NORMAL 6>,
1251                                <&dma SUN4I_DMA_NORMAL 6>;
1252                         dma-names = "rx", "tx";
1253                         status = "disabled";
1254                 };
1255
1256                 rtp: rtp@1c25000 {
1257                         compatible = "allwinner,sun5i-a13-ts";
1258                         reg = <0x01c25000 0x100>;
1259                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1260                         #thermal-sensor-cells = <0>;
1261                 };
1262
1263                 uart0: serial@1c28000 {
1264                         compatible = "snps,dw-apb-uart";
1265                         reg = <0x01c28000 0x400>;
1266                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1267                         reg-shift = <2>;
1268                         reg-io-width = <4>;
1269                         clocks = <&ccu CLK_APB1_UART0>;
1270                         status = "disabled";
1271                 };
1272
1273                 uart1: serial@1c28400 {
1274                         compatible = "snps,dw-apb-uart";
1275                         reg = <0x01c28400 0x400>;
1276                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1277                         reg-shift = <2>;
1278                         reg-io-width = <4>;
1279                         clocks = <&ccu CLK_APB1_UART1>;
1280                         status = "disabled";
1281                 };
1282
1283                 uart2: serial@1c28800 {
1284                         compatible = "snps,dw-apb-uart";
1285                         reg = <0x01c28800 0x400>;
1286                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1287                         reg-shift = <2>;
1288                         reg-io-width = <4>;
1289                         clocks = <&ccu CLK_APB1_UART2>;
1290                         status = "disabled";
1291                 };
1292
1293                 uart3: serial@1c28c00 {
1294                         compatible = "snps,dw-apb-uart";
1295                         reg = <0x01c28c00 0x400>;
1296                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1297                         reg-shift = <2>;
1298                         reg-io-width = <4>;
1299                         clocks = <&ccu CLK_APB1_UART3>;
1300                         status = "disabled";
1301                 };
1302
1303                 uart4: serial@1c29000 {
1304                         compatible = "snps,dw-apb-uart";
1305                         reg = <0x01c29000 0x400>;
1306                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1307                         reg-shift = <2>;
1308                         reg-io-width = <4>;
1309                         clocks = <&ccu CLK_APB1_UART4>;
1310                         status = "disabled";
1311                 };
1312
1313                 uart5: serial@1c29400 {
1314                         compatible = "snps,dw-apb-uart";
1315                         reg = <0x01c29400 0x400>;
1316                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1317                         reg-shift = <2>;
1318                         reg-io-width = <4>;
1319                         clocks = <&ccu CLK_APB1_UART5>;
1320                         status = "disabled";
1321                 };
1322
1323                 uart6: serial@1c29800 {
1324                         compatible = "snps,dw-apb-uart";
1325                         reg = <0x01c29800 0x400>;
1326                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1327                         reg-shift = <2>;
1328                         reg-io-width = <4>;
1329                         clocks = <&ccu CLK_APB1_UART6>;
1330                         status = "disabled";
1331                 };
1332
1333                 uart7: serial@1c29c00 {
1334                         compatible = "snps,dw-apb-uart";
1335                         reg = <0x01c29c00 0x400>;
1336                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1337                         reg-shift = <2>;
1338                         reg-io-width = <4>;
1339                         clocks = <&ccu CLK_APB1_UART7>;
1340                         status = "disabled";
1341                 };
1342
1343                 ps20: ps2@1c2a000 {
1344                         compatible = "allwinner,sun4i-a10-ps2";
1345                         reg = <0x01c2a000 0x400>;
1346                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1347                         clocks = <&ccu CLK_APB1_PS20>;
1348                         status = "disabled";
1349                 };
1350
1351                 ps21: ps2@1c2a400 {
1352                         compatible = "allwinner,sun4i-a10-ps2";
1353                         reg = <0x01c2a400 0x400>;
1354                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1355                         clocks = <&ccu CLK_APB1_PS21>;
1356                         status = "disabled";
1357                 };
1358
1359                 i2c0: i2c@1c2ac00 {
1360                         compatible = "allwinner,sun7i-a20-i2c",
1361                                      "allwinner,sun4i-a10-i2c";
1362                         reg = <0x01c2ac00 0x400>;
1363                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1364                         clocks = <&ccu CLK_APB1_I2C0>;
1365                         pinctrl-names = "default";
1366                         pinctrl-0 = <&i2c0_pins>;
1367                         status = "disabled";
1368                         #address-cells = <1>;
1369                         #size-cells = <0>;
1370                 };
1371
1372                 i2c1: i2c@1c2b000 {
1373                         compatible = "allwinner,sun7i-a20-i2c",
1374                                      "allwinner,sun4i-a10-i2c";
1375                         reg = <0x01c2b000 0x400>;
1376                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1377                         clocks = <&ccu CLK_APB1_I2C1>;
1378                         pinctrl-names = "default";
1379                         pinctrl-0 = <&i2c1_pins>;
1380                         status = "disabled";
1381                         #address-cells = <1>;
1382                         #size-cells = <0>;
1383                 };
1384
1385                 i2c2: i2c@1c2b400 {
1386                         compatible = "allwinner,sun7i-a20-i2c",
1387                                      "allwinner,sun4i-a10-i2c";
1388                         reg = <0x01c2b400 0x400>;
1389                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1390                         clocks = <&ccu CLK_APB1_I2C2>;
1391                         pinctrl-names = "default";
1392                         pinctrl-0 = <&i2c2_pins>;
1393                         status = "disabled";
1394                         #address-cells = <1>;
1395                         #size-cells = <0>;
1396                 };
1397
1398                 i2c3: i2c@1c2b800 {
1399                         compatible = "allwinner,sun7i-a20-i2c",
1400                                      "allwinner,sun4i-a10-i2c";
1401                         reg = <0x01c2b800 0x400>;
1402                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1403                         clocks = <&ccu CLK_APB1_I2C3>;
1404                         pinctrl-names = "default";
1405                         pinctrl-0 = <&i2c3_pins>;
1406                         status = "disabled";
1407                         #address-cells = <1>;
1408                         #size-cells = <0>;
1409                 };
1410
1411                 can0: can@1c2bc00 {
1412                         compatible = "allwinner,sun7i-a20-can",
1413                                      "allwinner,sun4i-a10-can";
1414                         reg = <0x01c2bc00 0x400>;
1415                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1416                         clocks = <&ccu CLK_APB1_CAN>;
1417                         status = "disabled";
1418                 };
1419
1420                 i2c4: i2c@1c2c000 {
1421                         compatible = "allwinner,sun7i-a20-i2c",
1422                                      "allwinner,sun4i-a10-i2c";
1423                         reg = <0x01c2c000 0x400>;
1424                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1425                         clocks = <&ccu CLK_APB1_I2C4>;
1426                         status = "disabled";
1427                         #address-cells = <1>;
1428                         #size-cells = <0>;
1429                 };
1430
1431                 mali: gpu@1c40000 {
1432                         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1433                         reg = <0x01c40000 0x10000>;
1434                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1435                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1436                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1437                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1438                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1439                                      <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1440                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1441                         interrupt-names = "gp",
1442                                           "gpmmu",
1443                                           "pp0",
1444                                           "ppmmu0",
1445                                           "pp1",
1446                                           "ppmmu1",
1447                                           "pmu";
1448                         clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1449                         clock-names = "bus", "core";
1450                         resets = <&ccu RST_GPU>;
1451
1452                         assigned-clocks = <&ccu CLK_GPU>;
1453                         assigned-clock-rates = <384000000>;
1454                 };
1455
1456                 gmac: ethernet@1c50000 {
1457                         compatible = "allwinner,sun7i-a20-gmac";
1458                         reg = <0x01c50000 0x10000>;
1459                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1460                         interrupt-names = "macirq";
1461                         clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1462                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1463                         snps,pbl = <2>;
1464                         snps,fixed-burst;
1465                         snps,force_sf_dma_mode;
1466                         status = "disabled";
1467
1468                         gmac_mdio: mdio {
1469                                 compatible = "snps,dwmac-mdio";
1470                                 #address-cells = <1>;
1471                                 #size-cells = <0>;
1472                         };
1473                 };
1474
1475                 hstimer@1c60000 {
1476                         compatible = "allwinner,sun7i-a20-hstimer";
1477                         reg = <0x01c60000 0x1000>;
1478                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1479                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1480                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1481                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1482                         clocks = <&ccu CLK_AHB_HSTIMER>;
1483                 };
1484
1485                 gic: interrupt-controller@1c81000 {
1486                         compatible = "arm,gic-400";
1487                         reg = <0x01c81000 0x1000>,
1488                               <0x01c82000 0x2000>,
1489                               <0x01c84000 0x2000>,
1490                               <0x01c86000 0x2000>;
1491                         interrupt-controller;
1492                         #interrupt-cells = <3>;
1493                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1494                 };
1495
1496                 fe0: display-frontend@1e00000 {
1497                         compatible = "allwinner,sun7i-a20-display-frontend";
1498                         reg = <0x01e00000 0x20000>;
1499                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1500                         clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1501                                  <&ccu CLK_DRAM_DE_FE0>;
1502                         clock-names = "ahb", "mod",
1503                                       "ram";
1504                         resets = <&ccu RST_DE_FE0>;
1505
1506                         ports {
1507                                 #address-cells = <1>;
1508                                 #size-cells = <0>;
1509
1510                                 fe0_out: port@1 {
1511                                         #address-cells = <1>;
1512                                         #size-cells = <0>;
1513                                         reg = <1>;
1514
1515                                         fe0_out_be0: endpoint@0 {
1516                                                 reg = <0>;
1517                                                 remote-endpoint = <&be0_in_fe0>;
1518                                         };
1519
1520                                         fe0_out_be1: endpoint@1 {
1521                                                 reg = <1>;
1522                                                 remote-endpoint = <&be1_in_fe0>;
1523                                         };
1524                                 };
1525                         };
1526                 };
1527
1528                 fe1: display-frontend@1e20000 {
1529                         compatible = "allwinner,sun7i-a20-display-frontend";
1530                         reg = <0x01e20000 0x20000>;
1531                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1532                         clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1533                                  <&ccu CLK_DRAM_DE_FE1>;
1534                         clock-names = "ahb", "mod",
1535                                       "ram";
1536                         resets = <&ccu RST_DE_FE1>;
1537
1538                         ports {
1539                                 #address-cells = <1>;
1540                                 #size-cells = <0>;
1541
1542                                 fe1_out: port@1 {
1543                                         #address-cells = <1>;
1544                                         #size-cells = <0>;
1545                                         reg = <1>;
1546
1547                                         fe1_out_be0: endpoint@0 {
1548                                                 reg = <0>;
1549                                                 remote-endpoint = <&be0_in_fe1>;
1550                                         };
1551
1552                                         fe1_out_be1: endpoint@1 {
1553                                                 reg = <1>;
1554                                                 remote-endpoint = <&be1_in_fe1>;
1555                                         };
1556                                 };
1557                         };
1558                 };
1559
1560                 be1: display-backend@1e40000 {
1561                         compatible = "allwinner,sun7i-a20-display-backend";
1562                         reg = <0x01e40000 0x10000>;
1563                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1564                         clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1565                                  <&ccu CLK_DRAM_DE_BE1>;
1566                         clock-names = "ahb", "mod",
1567                                       "ram";
1568                         resets = <&ccu RST_DE_BE1>;
1569
1570                         ports {
1571                                 #address-cells = <1>;
1572                                 #size-cells = <0>;
1573
1574                                 be1_in: port@0 {
1575                                         #address-cells = <1>;
1576                                         #size-cells = <0>;
1577                                         reg = <0>;
1578
1579                                         be1_in_fe0: endpoint@0 {
1580                                                 reg = <0>;
1581                                                 remote-endpoint = <&fe0_out_be1>;
1582                                         };
1583
1584                                         be1_in_fe1: endpoint@1 {
1585                                                 reg = <1>;
1586                                                 remote-endpoint = <&fe1_out_be1>;
1587                                         };
1588                                 };
1589
1590                                 be1_out: port@1 {
1591                                         #address-cells = <1>;
1592                                         #size-cells = <0>;
1593                                         reg = <1>;
1594
1595                                         be1_out_tcon0: endpoint@0 {
1596                                                 reg = <0>;
1597                                                 remote-endpoint = <&tcon0_in_be1>;
1598                                         };
1599
1600                                         be1_out_tcon1: endpoint@1 {
1601                                                 reg = <1>;
1602                                                 remote-endpoint = <&tcon1_in_be1>;
1603                                         };
1604                                 };
1605                         };
1606                 };
1607
1608                 be0: display-backend@1e60000 {
1609                         compatible = "allwinner,sun7i-a20-display-backend";
1610                         reg = <0x01e60000 0x10000>;
1611                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1612                         clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1613                                  <&ccu CLK_DRAM_DE_BE0>;
1614                         clock-names = "ahb", "mod",
1615                                       "ram";
1616                         resets = <&ccu RST_DE_BE0>;
1617
1618                         ports {
1619                                 #address-cells = <1>;
1620                                 #size-cells = <0>;
1621
1622                                 be0_in: port@0 {
1623                                         #address-cells = <1>;
1624                                         #size-cells = <0>;
1625                                         reg = <0>;
1626
1627                                         be0_in_fe0: endpoint@0 {
1628                                                 reg = <0>;
1629                                                 remote-endpoint = <&fe0_out_be0>;
1630                                         };
1631
1632                                         be0_in_fe1: endpoint@1 {
1633                                                 reg = <1>;
1634                                                 remote-endpoint = <&fe1_out_be0>;
1635                                         };
1636                                 };
1637
1638                                 be0_out: port@1 {
1639                                         #address-cells = <1>;
1640                                         #size-cells = <0>;
1641                                         reg = <1>;
1642
1643                                         be0_out_tcon0: endpoint@0 {
1644                                                 reg = <0>;
1645                                                 remote-endpoint = <&tcon0_in_be0>;
1646                                         };
1647
1648                                         be0_out_tcon1: endpoint@1 {
1649                                                 reg = <1>;
1650                                                 remote-endpoint = <&tcon1_in_be0>;
1651                                         };
1652                                 };
1653                         };
1654                 };
1655         };
1656 };