2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 #include "skeleton.dtsi"
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 #include <dt-bindings/thermal/thermal.h>
55 #include <dt-bindings/dma/sun4i-a10.h>
56 #include <dt-bindings/pinctrl/sun4i-a10.h>
59 interrupt-parent = <&gic>;
71 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
72 allwinner,pipeline = "de_be0-lcd0-hdmi";
73 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
79 compatible = "allwinner,simple-framebuffer",
81 allwinner,pipeline = "de_be0-lcd0";
82 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
87 compatible = "allwinner,simple-framebuffer",
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
101 compatible = "arm,cortex-a7";
105 clock-latency = <244144>; /* 8 32k periods */
117 #cooling-cells = <2>;
118 cooling-min-level = <0>;
119 cooling-max-level = <7>;
123 compatible = "arm,cortex-a7";
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
144 cpu_alert0: cpu_alert0 {
146 temperature = <75000>;
153 temperature = <100000>;
162 reg = <0x40000000 0x80000000>;
166 compatible = "arm,armv7-timer";
167 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
170 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
174 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
175 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
180 #address-cells = <1>;
184 osc24M: clk@01c20050 {
186 compatible = "allwinner,sun4i-a10-osc-clk";
187 reg = <0x01c20050 0x4>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc24M";
194 compatible = "fixed-clock";
195 clock-frequency = <32768>;
196 clock-output-names = "osc32k";
201 compatible = "allwinner,sun4i-a10-pll1-clk";
202 reg = <0x01c20000 0x4>;
204 clock-output-names = "pll1";
209 compatible = "allwinner,sun7i-a20-pll4-clk";
210 reg = <0x01c20018 0x4>;
212 clock-output-names = "pll4";
217 compatible = "allwinner,sun4i-a10-pll5-clk";
218 reg = <0x01c20020 0x4>;
220 clock-output-names = "pll5_ddr", "pll5_other";
225 compatible = "allwinner,sun4i-a10-pll6-clk";
226 reg = <0x01c20028 0x4>;
228 clock-output-names = "pll6_sata", "pll6_other", "pll6";
233 compatible = "allwinner,sun7i-a20-pll4-clk";
234 reg = <0x01c20040 0x4>;
236 clock-output-names = "pll8";
241 compatible = "allwinner,sun4i-a10-cpu-clk";
242 reg = <0x01c20054 0x4>;
243 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
244 clock-output-names = "cpu";
249 compatible = "allwinner,sun4i-a10-axi-clk";
250 reg = <0x01c20054 0x4>;
252 clock-output-names = "axi";
257 compatible = "allwinner,sun4i-a10-ahb-clk";
258 reg = <0x01c20054 0x4>;
260 clock-output-names = "ahb";
263 ahb_gates: clk@01c20060 {
265 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
266 reg = <0x01c20060 0x8>;
268 clock-output-names = "ahb_usb0", "ahb_ehci0",
269 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
270 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
271 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
272 "ahb_nand", "ahb_sdram", "ahb_ace",
273 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
274 "ahb_spi2", "ahb_spi3", "ahb_sata",
275 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
276 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
277 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
278 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
279 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
283 apb0: apb0@01c20054 {
285 compatible = "allwinner,sun4i-a10-apb0-clk";
286 reg = <0x01c20054 0x4>;
288 clock-output-names = "apb0";
291 apb0_gates: clk@01c20068 {
293 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
294 reg = <0x01c20068 0x4>;
296 clock-output-names = "apb0_codec", "apb0_spdif",
297 "apb0_ac97", "apb0_iis0", "apb0_iis1",
298 "apb0_pio", "apb0_ir0", "apb0_ir1",
299 "apb0_iis2", "apb0_keypad";
304 compatible = "allwinner,sun4i-a10-apb1-clk";
305 reg = <0x01c20058 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
307 clock-output-names = "apb1";
310 apb1_gates: clk@01c2006c {
312 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
313 reg = <0x01c2006c 0x4>;
315 clock-output-names = "apb1_i2c0", "apb1_i2c1",
316 "apb1_i2c2", "apb1_i2c3", "apb1_can",
317 "apb1_scr", "apb1_ps20", "apb1_ps21",
318 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
319 "apb1_uart2", "apb1_uart3", "apb1_uart4",
320 "apb1_uart5", "apb1_uart6", "apb1_uart7";
323 nand_clk: clk@01c20080 {
325 compatible = "allwinner,sun4i-a10-mod0-clk";
326 reg = <0x01c20080 0x4>;
327 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
328 clock-output-names = "nand";
331 ms_clk: clk@01c20084 {
333 compatible = "allwinner,sun4i-a10-mod0-clk";
334 reg = <0x01c20084 0x4>;
335 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
336 clock-output-names = "ms";
339 mmc0_clk: clk@01c20088 {
341 compatible = "allwinner,sun4i-a10-mmc-clk";
342 reg = <0x01c20088 0x4>;
343 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
344 clock-output-names = "mmc0",
349 mmc1_clk: clk@01c2008c {
351 compatible = "allwinner,sun4i-a10-mmc-clk";
352 reg = <0x01c2008c 0x4>;
353 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
354 clock-output-names = "mmc1",
359 mmc2_clk: clk@01c20090 {
361 compatible = "allwinner,sun4i-a10-mmc-clk";
362 reg = <0x01c20090 0x4>;
363 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
364 clock-output-names = "mmc2",
369 mmc3_clk: clk@01c20094 {
371 compatible = "allwinner,sun4i-a10-mmc-clk";
372 reg = <0x01c20094 0x4>;
373 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
374 clock-output-names = "mmc3",
379 ts_clk: clk@01c20098 {
381 compatible = "allwinner,sun4i-a10-mod0-clk";
382 reg = <0x01c20098 0x4>;
383 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
384 clock-output-names = "ts";
387 ss_clk: clk@01c2009c {
389 compatible = "allwinner,sun4i-a10-mod0-clk";
390 reg = <0x01c2009c 0x4>;
391 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
392 clock-output-names = "ss";
395 spi0_clk: clk@01c200a0 {
397 compatible = "allwinner,sun4i-a10-mod0-clk";
398 reg = <0x01c200a0 0x4>;
399 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
400 clock-output-names = "spi0";
403 spi1_clk: clk@01c200a4 {
405 compatible = "allwinner,sun4i-a10-mod0-clk";
406 reg = <0x01c200a4 0x4>;
407 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
408 clock-output-names = "spi1";
411 spi2_clk: clk@01c200a8 {
413 compatible = "allwinner,sun4i-a10-mod0-clk";
414 reg = <0x01c200a8 0x4>;
415 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
416 clock-output-names = "spi2";
419 pata_clk: clk@01c200ac {
421 compatible = "allwinner,sun4i-a10-mod0-clk";
422 reg = <0x01c200ac 0x4>;
423 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
424 clock-output-names = "pata";
427 ir0_clk: clk@01c200b0 {
429 compatible = "allwinner,sun4i-a10-mod0-clk";
430 reg = <0x01c200b0 0x4>;
431 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
432 clock-output-names = "ir0";
435 ir1_clk: clk@01c200b4 {
437 compatible = "allwinner,sun4i-a10-mod0-clk";
438 reg = <0x01c200b4 0x4>;
439 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
440 clock-output-names = "ir1";
443 usb_clk: clk@01c200cc {
446 compatible = "allwinner,sun4i-a10-usb-clk";
447 reg = <0x01c200cc 0x4>;
449 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
452 spi3_clk: clk@01c200d4 {
454 compatible = "allwinner,sun4i-a10-mod0-clk";
455 reg = <0x01c200d4 0x4>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clock-output-names = "spi3";
460 mbus_clk: clk@01c2015c {
462 compatible = "allwinner,sun5i-a13-mbus-clk";
463 reg = <0x01c2015c 0x4>;
464 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
465 clock-output-names = "mbus";
469 * The following two are dummy clocks, placeholders used in the gmac_tx
470 * clock. The gmac driver will choose one parent depending on the PHY
471 * interface mode, using clk_set_rate auto-reparenting.
472 * The actual TX clock rate is not controlled by the gmac_tx clock.
474 mii_phy_tx_clk: clk@2 {
476 compatible = "fixed-clock";
477 clock-frequency = <25000000>;
478 clock-output-names = "mii_phy_tx";
481 gmac_int_tx_clk: clk@3 {
483 compatible = "fixed-clock";
484 clock-frequency = <125000000>;
485 clock-output-names = "gmac_int_tx";
488 gmac_tx_clk: clk@01c20164 {
490 compatible = "allwinner,sun7i-a20-gmac-clk";
491 reg = <0x01c20164 0x4>;
492 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
493 clock-output-names = "gmac_tx";
497 * Dummy clock used by output clocks
501 compatible = "fixed-factor-clock";
505 clock-output-names = "osc24M_32k";
508 clk_out_a: clk@01c201f0 {
510 compatible = "allwinner,sun7i-a20-out-clk";
511 reg = <0x01c201f0 0x4>;
512 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
513 clock-output-names = "clk_out_a";
516 clk_out_b: clk@01c201f4 {
518 compatible = "allwinner,sun7i-a20-out-clk";
519 reg = <0x01c201f4 0x4>;
520 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
521 clock-output-names = "clk_out_b";
526 compatible = "simple-bus";
527 #address-cells = <1>;
531 nmi_intc: interrupt-controller@01c00030 {
532 compatible = "allwinner,sun7i-a20-sc-nmi";
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 reg = <0x01c00030 0x0c>;
536 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
539 dma: dma-controller@01c02000 {
540 compatible = "allwinner,sun4i-a10-dma";
541 reg = <0x01c02000 0x1000>;
542 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&ahb_gates 6>;
548 compatible = "allwinner,sun4i-a10-spi";
549 reg = <0x01c05000 0x1000>;
550 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&ahb_gates 20>, <&spi0_clk>;
552 clock-names = "ahb", "mod";
553 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
554 <&dma SUN4I_DMA_DEDICATED 26>;
555 dma-names = "rx", "tx";
557 #address-cells = <1>;
562 compatible = "allwinner,sun4i-a10-spi";
563 reg = <0x01c06000 0x1000>;
564 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&ahb_gates 21>, <&spi1_clk>;
566 clock-names = "ahb", "mod";
567 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
568 <&dma SUN4I_DMA_DEDICATED 8>;
569 dma-names = "rx", "tx";
571 #address-cells = <1>;
575 emac: ethernet@01c0b000 {
576 compatible = "allwinner,sun4i-a10-emac";
577 reg = <0x01c0b000 0x1000>;
578 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&ahb_gates 17>;
583 mdio: mdio@01c0b080 {
584 compatible = "allwinner,sun4i-a10-mdio";
585 reg = <0x01c0b080 0x14>;
587 #address-cells = <1>;
592 compatible = "allwinner,sun5i-a13-mmc";
593 reg = <0x01c0f000 0x1000>;
594 clocks = <&ahb_gates 8>,
602 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
607 compatible = "allwinner,sun5i-a13-mmc";
608 reg = <0x01c10000 0x1000>;
609 clocks = <&ahb_gates 9>,
617 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
622 compatible = "allwinner,sun5i-a13-mmc";
623 reg = <0x01c11000 0x1000>;
624 clocks = <&ahb_gates 10>,
632 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
637 compatible = "allwinner,sun5i-a13-mmc";
638 reg = <0x01c12000 0x1000>;
639 clocks = <&ahb_gates 11>,
647 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
651 usbphy: phy@01c13400 {
653 compatible = "allwinner,sun7i-a20-usb-phy";
654 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
655 reg-names = "phy_ctrl", "pmu1", "pmu2";
656 clocks = <&usb_clk 8>;
657 clock-names = "usb_phy";
658 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
659 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
663 ehci0: usb@01c14000 {
664 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
665 reg = <0x01c14000 0x100>;
666 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&ahb_gates 1>;
673 ohci0: usb@01c14400 {
674 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
675 reg = <0x01c14400 0x100>;
676 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&usb_clk 6>, <&ahb_gates 2>;
684 compatible = "allwinner,sun4i-a10-spi";
685 reg = <0x01c17000 0x1000>;
686 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&ahb_gates 22>, <&spi2_clk>;
688 clock-names = "ahb", "mod";
689 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
690 <&dma SUN4I_DMA_DEDICATED 28>;
691 dma-names = "rx", "tx";
693 #address-cells = <1>;
697 ahci: sata@01c18000 {
698 compatible = "allwinner,sun4i-a10-ahci";
699 reg = <0x01c18000 0x1000>;
700 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&pll6 0>, <&ahb_gates 25>;
705 ehci1: usb@01c1c000 {
706 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
707 reg = <0x01c1c000 0x100>;
708 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&ahb_gates 3>;
715 ohci1: usb@01c1c400 {
716 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
717 reg = <0x01c1c400 0x100>;
718 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&usb_clk 7>, <&ahb_gates 4>;
726 compatible = "allwinner,sun4i-a10-spi";
727 reg = <0x01c1f000 0x1000>;
728 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&ahb_gates 23>, <&spi3_clk>;
730 clock-names = "ahb", "mod";
731 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
732 <&dma SUN4I_DMA_DEDICATED 30>;
733 dma-names = "rx", "tx";
735 #address-cells = <1>;
739 pio: pinctrl@01c20800 {
740 compatible = "allwinner,sun7i-a20-pinctrl";
741 reg = <0x01c20800 0x400>;
742 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&apb0_gates 5>;
745 interrupt-controller;
746 #interrupt-cells = <2>;
750 pwm0_pins_a: pwm0@0 {
751 allwinner,pins = "PB2";
752 allwinner,function = "pwm";
753 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
754 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
757 pwm1_pins_a: pwm1@0 {
758 allwinner,pins = "PI3";
759 allwinner,function = "pwm";
760 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
761 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
764 uart0_pins_a: uart0@0 {
765 allwinner,pins = "PB22", "PB23";
766 allwinner,function = "uart0";
767 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
768 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
771 uart2_pins_a: uart2@0 {
772 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
773 allwinner,function = "uart2";
774 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
775 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
778 uart3_pins_a: uart3@0 {
779 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
780 allwinner,function = "uart3";
781 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
782 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
785 uart3_pins_b: uart3@1 {
786 allwinner,pins = "PH0", "PH1";
787 allwinner,function = "uart3";
788 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
789 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
792 uart4_pins_a: uart4@0 {
793 allwinner,pins = "PG10", "PG11";
794 allwinner,function = "uart4";
795 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
796 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
799 uart5_pins_a: uart5@0 {
800 allwinner,pins = "PI10", "PI11";
801 allwinner,function = "uart5";
802 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
803 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
806 uart6_pins_a: uart6@0 {
807 allwinner,pins = "PI12", "PI13";
808 allwinner,function = "uart6";
809 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
810 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
813 uart7_pins_a: uart7@0 {
814 allwinner,pins = "PI20", "PI21";
815 allwinner,function = "uart7";
816 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
817 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
820 i2c0_pins_a: i2c0@0 {
821 allwinner,pins = "PB0", "PB1";
822 allwinner,function = "i2c0";
823 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
824 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
827 i2c1_pins_a: i2c1@0 {
828 allwinner,pins = "PB18", "PB19";
829 allwinner,function = "i2c1";
830 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
831 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
834 i2c2_pins_a: i2c2@0 {
835 allwinner,pins = "PB20", "PB21";
836 allwinner,function = "i2c2";
837 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
838 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
841 i2c3_pins_a: i2c3@0 {
842 allwinner,pins = "PI0", "PI1";
843 allwinner,function = "i2c3";
844 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
845 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
848 emac_pins_a: emac0@0 {
849 allwinner,pins = "PA0", "PA1", "PA2",
850 "PA3", "PA4", "PA5", "PA6",
851 "PA7", "PA8", "PA9", "PA10",
852 "PA11", "PA12", "PA13", "PA14",
854 allwinner,function = "emac";
855 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
856 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
859 clk_out_a_pins_a: clk_out_a@0 {
860 allwinner,pins = "PI12";
861 allwinner,function = "clk_out_a";
862 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
863 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
866 clk_out_b_pins_a: clk_out_b@0 {
867 allwinner,pins = "PI13";
868 allwinner,function = "clk_out_b";
869 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
870 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
873 gmac_pins_mii_a: gmac_mii@0 {
874 allwinner,pins = "PA0", "PA1", "PA2",
875 "PA3", "PA4", "PA5", "PA6",
876 "PA7", "PA8", "PA9", "PA10",
877 "PA11", "PA12", "PA13", "PA14",
879 allwinner,function = "gmac";
880 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
881 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
884 gmac_pins_rgmii_a: gmac_rgmii@0 {
885 allwinner,pins = "PA0", "PA1", "PA2",
886 "PA3", "PA4", "PA5", "PA6",
887 "PA7", "PA8", "PA10",
888 "PA11", "PA12", "PA13",
890 allwinner,function = "gmac";
892 * data lines in RGMII mode use DDR mode
893 * and need a higher signal drive strength
895 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
896 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
899 spi0_pins_a: spi0@0 {
900 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
901 allwinner,function = "spi0";
902 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
903 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
906 spi1_pins_a: spi1@0 {
907 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
908 allwinner,function = "spi1";
909 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
910 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
913 spi2_pins_a: spi2@0 {
914 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
915 allwinner,function = "spi2";
916 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
917 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
920 spi2_pins_b: spi2@1 {
921 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
922 allwinner,function = "spi2";
923 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
924 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
927 mmc0_pins_a: mmc0@0 {
928 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
929 allwinner,function = "mmc0";
930 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
931 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
934 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
935 allwinner,pins = "PH1";
936 allwinner,function = "gpio_in";
937 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
938 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
941 mmc2_pins_a: mmc2@0 {
942 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
943 allwinner,function = "mmc2";
944 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
945 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
948 mmc3_pins_a: mmc3@0 {
949 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
950 allwinner,function = "mmc3";
951 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
952 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
956 allwinner,pins = "PB3","PB4";
957 allwinner,function = "ir0";
958 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
959 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
963 allwinner,pins = "PB22","PB23";
964 allwinner,function = "ir1";
965 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
966 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
969 ps20_pins_a: ps20@0 {
970 allwinner,pins = "PI20", "PI21";
971 allwinner,function = "ps2";
972 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
973 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
976 ps21_pins_a: ps21@0 {
977 allwinner,pins = "PH12", "PH13";
978 allwinner,function = "ps2";
979 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
980 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
985 compatible = "allwinner,sun4i-a10-timer";
986 reg = <0x01c20c00 0x90>;
987 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
996 wdt: watchdog@01c20c90 {
997 compatible = "allwinner,sun4i-a10-wdt";
998 reg = <0x01c20c90 0x10>;
1002 compatible = "allwinner,sun7i-a20-rtc";
1003 reg = <0x01c20d00 0x20>;
1004 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1008 compatible = "allwinner,sun7i-a20-pwm";
1009 reg = <0x01c20e00 0xc>;
1012 status = "disabled";
1016 compatible = "allwinner,sun4i-a10-ir";
1017 clocks = <&apb0_gates 6>, <&ir0_clk>;
1018 clock-names = "apb", "ir";
1019 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1020 reg = <0x01c21800 0x40>;
1021 status = "disabled";
1025 compatible = "allwinner,sun4i-a10-ir";
1026 clocks = <&apb0_gates 7>, <&ir1_clk>;
1027 clock-names = "apb", "ir";
1028 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1029 reg = <0x01c21c00 0x40>;
1030 status = "disabled";
1033 lradc: lradc@01c22800 {
1034 compatible = "allwinner,sun4i-a10-lradc-keys";
1035 reg = <0x01c22800 0x100>;
1036 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1037 status = "disabled";
1040 sid: eeprom@01c23800 {
1041 compatible = "allwinner,sun7i-a20-sid";
1042 reg = <0x01c23800 0x200>;
1046 compatible = "allwinner,sun4i-a10-ts";
1047 reg = <0x01c25000 0x100>;
1048 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1049 #thermal-sensor-cells = <0>;
1052 uart0: serial@01c28000 {
1053 compatible = "snps,dw-apb-uart";
1054 reg = <0x01c28000 0x400>;
1055 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1058 clocks = <&apb1_gates 16>;
1059 status = "disabled";
1062 uart1: serial@01c28400 {
1063 compatible = "snps,dw-apb-uart";
1064 reg = <0x01c28400 0x400>;
1065 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&apb1_gates 17>;
1069 status = "disabled";
1072 uart2: serial@01c28800 {
1073 compatible = "snps,dw-apb-uart";
1074 reg = <0x01c28800 0x400>;
1075 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&apb1_gates 18>;
1079 status = "disabled";
1082 uart3: serial@01c28c00 {
1083 compatible = "snps,dw-apb-uart";
1084 reg = <0x01c28c00 0x400>;
1085 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&apb1_gates 19>;
1089 status = "disabled";
1092 uart4: serial@01c29000 {
1093 compatible = "snps,dw-apb-uart";
1094 reg = <0x01c29000 0x400>;
1095 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&apb1_gates 20>;
1099 status = "disabled";
1102 uart5: serial@01c29400 {
1103 compatible = "snps,dw-apb-uart";
1104 reg = <0x01c29400 0x400>;
1105 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&apb1_gates 21>;
1109 status = "disabled";
1112 uart6: serial@01c29800 {
1113 compatible = "snps,dw-apb-uart";
1114 reg = <0x01c29800 0x400>;
1115 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&apb1_gates 22>;
1119 status = "disabled";
1122 uart7: serial@01c29c00 {
1123 compatible = "snps,dw-apb-uart";
1124 reg = <0x01c29c00 0x400>;
1125 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&apb1_gates 23>;
1129 status = "disabled";
1132 i2c0: i2c@01c2ac00 {
1133 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1134 reg = <0x01c2ac00 0x400>;
1135 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&apb1_gates 0>;
1137 status = "disabled";
1138 #address-cells = <1>;
1142 i2c1: i2c@01c2b000 {
1143 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1144 reg = <0x01c2b000 0x400>;
1145 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&apb1_gates 1>;
1147 status = "disabled";
1148 #address-cells = <1>;
1152 i2c2: i2c@01c2b400 {
1153 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1154 reg = <0x01c2b400 0x400>;
1155 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&apb1_gates 2>;
1157 status = "disabled";
1158 #address-cells = <1>;
1162 i2c3: i2c@01c2b800 {
1163 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1164 reg = <0x01c2b800 0x400>;
1165 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&apb1_gates 3>;
1167 status = "disabled";
1168 #address-cells = <1>;
1172 i2c4: i2c@01c2c000 {
1173 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1174 reg = <0x01c2c000 0x400>;
1175 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1176 clocks = <&apb1_gates 15>;
1177 status = "disabled";
1178 #address-cells = <1>;
1182 gmac: ethernet@01c50000 {
1183 compatible = "allwinner,sun7i-a20-gmac";
1184 reg = <0x01c50000 0x10000>;
1185 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1186 interrupt-names = "macirq";
1187 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1188 clock-names = "stmmaceth", "allwinner_gmac_tx";
1191 snps,force_sf_dma_mode;
1192 status = "disabled";
1193 #address-cells = <1>;
1198 compatible = "allwinner,sun7i-a20-hstimer";
1199 reg = <0x01c60000 0x1000>;
1200 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1204 clocks = <&ahb_gates 28>;
1207 gic: interrupt-controller@01c81000 {
1208 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1209 reg = <0x01c81000 0x1000>,
1210 <0x01c82000 0x1000>,
1211 <0x01c84000 0x2000>,
1212 <0x01c86000 0x2000>;
1213 interrupt-controller;
1214 #interrupt-cells = <3>;
1215 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1218 ps20: ps2@01c2a000 {
1219 compatible = "allwinner,sun4i-a10-ps2";
1220 reg = <0x01c2a000 0x400>;
1221 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1222 clocks = <&apb1_gates 6>;
1223 status = "disabled";
1226 ps21: ps2@01c2a400 {
1227 compatible = "allwinner,sun4i-a10-ps2";
1228 reg = <0x01c2a400 0x400>;
1229 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&apb1_gates 7>;
1231 status = "disabled";