2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
54 interrupt-parent = <&gic>;
65 simplefb_hdmi: framebuffer@0 {
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
76 simplefb_lcd: framebuffer@1 {
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 clock-frequency = <24000000>;
94 arm,cpu-registers-not-fw-configured;
98 enable-method = "allwinner,sun6i-a31";
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
115 #cooling-cells = <2>;
116 cooling-min-level = <0>;
117 cooling-max-level = <3>;
121 compatible = "arm,cortex-a7";
127 compatible = "arm,cortex-a7";
133 compatible = "arm,cortex-a7";
142 polling-delay-passive = <250>;
143 polling-delay = <1000>;
144 thermal-sensors = <&rtp>;
148 trip = <&cpu_alert0>;
149 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
154 cpu_alert0: cpu_alert0 {
156 temperature = <70000>;
163 temperature = <100000>;
172 reg = <0x40000000 0x80000000>;
176 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
177 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
184 #address-cells = <1>;
190 compatible = "fixed-clock";
191 clock-frequency = <24000000>;
196 compatible = "fixed-clock";
197 clock-frequency = <32768>;
198 clock-output-names = "osc32k";
202 * The following two are dummy clocks, placeholders
203 * used in the gmac_tx clock. The gmac driver will
204 * choose one parent depending on the PHY interface
205 * mode, using clk_set_rate auto-reparenting.
207 * The actual TX clock rate is not controlled by the
210 mii_phy_tx_clk: clk@1 {
212 compatible = "fixed-clock";
213 clock-frequency = <25000000>;
214 clock-output-names = "mii_phy_tx";
217 gmac_int_tx_clk: clk@2 {
219 compatible = "fixed-clock";
220 clock-frequency = <125000000>;
221 clock-output-names = "gmac_int_tx";
224 gmac_tx_clk: clk@01c200d0 {
226 compatible = "allwinner,sun7i-a20-gmac-clk";
227 reg = <0x01c200d0 0x4>;
228 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
229 clock-output-names = "gmac_tx";
234 compatible = "allwinner,sun6i-a31-display-engine";
235 allwinner,pipelines = <&fe0>;
240 compatible = "simple-bus";
241 #address-cells = <1>;
245 dma: dma-controller@01c02000 {
246 compatible = "allwinner,sun6i-a31-dma";
247 reg = <0x01c02000 0x1000>;
248 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&ccu CLK_AHB1_DMA>;
250 resets = <&ccu RST_AHB1_DMA>;
254 tcon0: lcd-controller@01c0c000 {
255 compatible = "allwinner,sun6i-a31-tcon";
256 reg = <0x01c0c000 0x1000>;
257 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
258 resets = <&ccu RST_AHB1_LCD0>;
260 clocks = <&ccu CLK_AHB1_LCD0>,
266 clock-output-names = "tcon0-pixel-clock";
270 #address-cells = <1>;
274 #address-cells = <1>;
278 tcon0_in_drc0: endpoint@0 {
280 remote-endpoint = <&drc0_out_tcon0>;
285 #address-cells = <1>;
293 compatible = "allwinner,sun7i-a20-mmc";
294 reg = <0x01c0f000 0x1000>;
295 clocks = <&ccu CLK_AHB1_MMC0>,
297 <&ccu CLK_MMC0_OUTPUT>,
298 <&ccu CLK_MMC0_SAMPLE>;
303 resets = <&ccu RST_AHB1_MMC0>;
305 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
307 #address-cells = <1>;
312 compatible = "allwinner,sun7i-a20-mmc";
313 reg = <0x01c10000 0x1000>;
314 clocks = <&ccu CLK_AHB1_MMC1>,
316 <&ccu CLK_MMC1_OUTPUT>,
317 <&ccu CLK_MMC1_SAMPLE>;
322 resets = <&ccu RST_AHB1_MMC1>;
324 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
331 compatible = "allwinner,sun7i-a20-mmc";
332 reg = <0x01c11000 0x1000>;
333 clocks = <&ccu CLK_AHB1_MMC2>,
335 <&ccu CLK_MMC2_OUTPUT>,
336 <&ccu CLK_MMC2_SAMPLE>;
341 resets = <&ccu RST_AHB1_MMC2>;
343 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
345 #address-cells = <1>;
350 compatible = "allwinner,sun7i-a20-mmc";
351 reg = <0x01c12000 0x1000>;
352 clocks = <&ccu CLK_AHB1_MMC3>,
354 <&ccu CLK_MMC3_OUTPUT>,
355 <&ccu CLK_MMC3_SAMPLE>;
360 resets = <&ccu RST_AHB1_MMC3>;
362 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
368 usb_otg: usb@01c19000 {
369 compatible = "allwinner,sun6i-a31-musb";
370 reg = <0x01c19000 0x0400>;
371 clocks = <&ccu CLK_AHB1_OTG>;
372 resets = <&ccu RST_AHB1_OTG>;
373 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
374 interrupt-names = "mc";
377 extcon = <&usbphy 0>;
381 usbphy: phy@01c19400 {
382 compatible = "allwinner,sun6i-a31-usb-phy";
383 reg = <0x01c19400 0x10>,
386 reg-names = "phy_ctrl",
389 clocks = <&ccu CLK_USB_PHY0>,
392 clock-names = "usb0_phy",
395 resets = <&ccu RST_USB_PHY0>,
398 reset-names = "usb0_reset",
405 ehci0: usb@01c1a000 {
406 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
407 reg = <0x01c1a000 0x100>;
408 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&ccu CLK_AHB1_EHCI0>;
410 resets = <&ccu RST_AHB1_EHCI0>;
416 ohci0: usb@01c1a400 {
417 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
418 reg = <0x01c1a400 0x100>;
419 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
421 resets = <&ccu RST_AHB1_OHCI0>;
427 ehci1: usb@01c1b000 {
428 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
429 reg = <0x01c1b000 0x100>;
430 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&ccu CLK_AHB1_EHCI1>;
432 resets = <&ccu RST_AHB1_EHCI1>;
438 ohci1: usb@01c1b400 {
439 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
440 reg = <0x01c1b400 0x100>;
441 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
443 resets = <&ccu RST_AHB1_OHCI1>;
449 ohci2: usb@01c1c400 {
450 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
451 reg = <0x01c1c400 0x100>;
452 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
454 resets = <&ccu RST_AHB1_OHCI2>;
458 ccu: clock@01c20000 {
459 compatible = "allwinner,sun6i-a31-ccu";
460 reg = <0x01c20000 0x400>;
461 clocks = <&osc24M>, <&osc32k>;
462 clock-names = "hosc", "losc";
467 pio: pinctrl@01c20800 {
468 compatible = "allwinner,sun6i-a31-pinctrl";
469 reg = <0x01c20800 0x400>;
470 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
475 clock-names = "apb", "hosc", "losc";
477 interrupt-controller;
478 #interrupt-cells = <3>;
481 gmac_pins_gmii_a: gmac_gmii@0 {
482 pins = "PA0", "PA1", "PA2", "PA3",
483 "PA4", "PA5", "PA6", "PA7",
484 "PA8", "PA9", "PA10", "PA11",
485 "PA12", "PA13", "PA14", "PA15",
486 "PA16", "PA17", "PA18", "PA19",
487 "PA20", "PA21", "PA22", "PA23",
488 "PA24", "PA25", "PA26", "PA27";
491 * data lines in GMII mode run at 125MHz and
492 * might need a higher signal drive strength
494 drive-strength = <30>;
497 gmac_pins_mii_a: gmac_mii@0 {
498 pins = "PA0", "PA1", "PA2", "PA3",
499 "PA8", "PA9", "PA11",
500 "PA12", "PA13", "PA14", "PA19",
501 "PA20", "PA21", "PA22", "PA23",
502 "PA24", "PA26", "PA27";
506 gmac_pins_rgmii_a: gmac_rgmii@0 {
507 pins = "PA0", "PA1", "PA2", "PA3",
508 "PA9", "PA10", "PA11",
509 "PA12", "PA13", "PA14", "PA19",
510 "PA20", "PA25", "PA26", "PA27";
513 * data lines in RGMII mode use DDR mode
514 * and need a higher signal drive strength
516 drive-strength = <40>;
519 i2c0_pins_a: i2c0@0 {
520 pins = "PH14", "PH15";
524 i2c1_pins_a: i2c1@0 {
525 pins = "PH16", "PH17";
529 i2c2_pins_a: i2c2@0 {
530 pins = "PH18", "PH19";
534 lcd0_rgb888_pins: lcd0_rgb888 {
535 pins = "PD0", "PD1", "PD2", "PD3",
536 "PD4", "PD5", "PD6", "PD7",
537 "PD8", "PD9", "PD10", "PD11",
538 "PD12", "PD13", "PD14", "PD15",
539 "PD16", "PD17", "PD18", "PD19",
540 "PD20", "PD21", "PD22", "PD23",
541 "PD24", "PD25", "PD26", "PD27";
545 mmc0_pins_a: mmc0@0 {
546 pins = "PF0", "PF1", "PF2",
549 drive-strength = <30>;
553 mmc1_pins_a: mmc1@0 {
554 pins = "PG0", "PG1", "PG2", "PG3",
557 drive-strength = <30>;
561 mmc2_pins_a: mmc2@0 {
562 pins = "PC6", "PC7", "PC8", "PC9",
565 drive-strength = <30>;
569 mmc2_8bit_emmc_pins: mmc2@1 {
570 pins = "PC6", "PC7", "PC8", "PC9",
571 "PC10", "PC11", "PC12",
572 "PC13", "PC14", "PC15",
575 drive-strength = <30>;
579 mmc3_8bit_emmc_pins: mmc3@1 {
580 pins = "PC6", "PC7", "PC8", "PC9",
581 "PC10", "PC11", "PC12",
582 "PC13", "PC14", "PC15",
585 drive-strength = <40>;
589 spdif_pins_a: spdif@0 {
594 uart0_pins_a: uart0@0 {
595 pins = "PH20", "PH21";
601 compatible = "allwinner,sun4i-a10-timer";
602 reg = <0x01c20c00 0xa0>;
603 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
611 wdt1: watchdog@01c20ca0 {
612 compatible = "allwinner,sun6i-a31-wdt";
613 reg = <0x01c20ca0 0x20>;
616 spdif: spdif@01c21000 {
617 #sound-dai-cells = <0>;
618 compatible = "allwinner,sun6i-a31-spdif";
619 reg = <0x01c21000 0x400>;
620 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
622 resets = <&ccu RST_APB1_SPDIF>;
623 clock-names = "apb", "spdif";
624 dmas = <&dma 2>, <&dma 2>;
625 dma-names = "rx", "tx";
629 lradc: lradc@01c22800 {
630 compatible = "allwinner,sun4i-a10-lradc-keys";
631 reg = <0x01c22800 0x100>;
632 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
637 compatible = "allwinner,sun6i-a31-ts";
638 reg = <0x01c25000 0x100>;
639 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
640 #thermal-sensor-cells = <0>;
643 uart0: serial@01c28000 {
644 compatible = "snps,dw-apb-uart";
645 reg = <0x01c28000 0x400>;
646 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_APB2_UART0>;
650 resets = <&ccu RST_APB2_UART0>;
651 dmas = <&dma 6>, <&dma 6>;
652 dma-names = "rx", "tx";
656 uart1: serial@01c28400 {
657 compatible = "snps,dw-apb-uart";
658 reg = <0x01c28400 0x400>;
659 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&ccu CLK_APB2_UART1>;
663 resets = <&ccu RST_APB2_UART1>;
664 dmas = <&dma 7>, <&dma 7>;
665 dma-names = "rx", "tx";
669 uart2: serial@01c28800 {
670 compatible = "snps,dw-apb-uart";
671 reg = <0x01c28800 0x400>;
672 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_APB2_UART2>;
676 resets = <&ccu RST_APB2_UART2>;
677 dmas = <&dma 8>, <&dma 8>;
678 dma-names = "rx", "tx";
682 uart3: serial@01c28c00 {
683 compatible = "snps,dw-apb-uart";
684 reg = <0x01c28c00 0x400>;
685 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&ccu CLK_APB2_UART3>;
689 resets = <&ccu RST_APB2_UART3>;
690 dmas = <&dma 9>, <&dma 9>;
691 dma-names = "rx", "tx";
695 uart4: serial@01c29000 {
696 compatible = "snps,dw-apb-uart";
697 reg = <0x01c29000 0x400>;
698 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&ccu CLK_APB2_UART4>;
702 resets = <&ccu RST_APB2_UART4>;
703 dmas = <&dma 10>, <&dma 10>;
704 dma-names = "rx", "tx";
708 uart5: serial@01c29400 {
709 compatible = "snps,dw-apb-uart";
710 reg = <0x01c29400 0x400>;
711 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&ccu CLK_APB2_UART5>;
715 resets = <&ccu RST_APB2_UART5>;
716 dmas = <&dma 22>, <&dma 22>;
717 dma-names = "rx", "tx";
722 compatible = "allwinner,sun6i-a31-i2c";
723 reg = <0x01c2ac00 0x400>;
724 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&ccu CLK_APB2_I2C0>;
726 resets = <&ccu RST_APB2_I2C0>;
728 #address-cells = <1>;
733 compatible = "allwinner,sun6i-a31-i2c";
734 reg = <0x01c2b000 0x400>;
735 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&ccu CLK_APB2_I2C1>;
737 resets = <&ccu RST_APB2_I2C1>;
739 #address-cells = <1>;
744 compatible = "allwinner,sun6i-a31-i2c";
745 reg = <0x01c2b400 0x400>;
746 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&ccu CLK_APB2_I2C2>;
748 resets = <&ccu RST_APB2_I2C2>;
750 #address-cells = <1>;
755 compatible = "allwinner,sun6i-a31-i2c";
756 reg = <0x01c2b800 0x400>;
757 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&ccu CLK_APB2_I2C3>;
759 resets = <&ccu RST_APB2_I2C3>;
761 #address-cells = <1>;
765 gmac: ethernet@01c30000 {
766 compatible = "allwinner,sun7i-a20-gmac";
767 reg = <0x01c30000 0x1054>;
768 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
769 interrupt-names = "macirq";
770 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
771 clock-names = "stmmaceth", "allwinner_gmac_tx";
772 resets = <&ccu RST_AHB1_EMAC>;
773 reset-names = "stmmaceth";
776 snps,force_sf_dma_mode;
778 #address-cells = <1>;
782 crypto: crypto-engine@01c15000 {
783 compatible = "allwinner,sun4i-a10-crypto";
784 reg = <0x01c15000 0x1000>;
785 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
787 clock-names = "ahb", "mod";
788 resets = <&ccu RST_AHB1_SS>;
792 codec: codec@01c22c00 {
793 #sound-dai-cells = <0>;
794 compatible = "allwinner,sun6i-a31-codec";
795 reg = <0x01c22c00 0x400>;
796 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
798 clock-names = "apb", "codec";
799 resets = <&ccu RST_APB1_CODEC>;
800 dmas = <&dma 15>, <&dma 15>;
801 dma-names = "rx", "tx";
806 compatible = "allwinner,sun6i-a31-hstimer",
807 "allwinner,sun7i-a20-hstimer";
808 reg = <0x01c60000 0x1000>;
809 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&ccu CLK_AHB1_HSTIMER>;
814 resets = <&ccu RST_AHB1_HSTIMER>;
818 compatible = "allwinner,sun6i-a31-spi";
819 reg = <0x01c68000 0x1000>;
820 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
822 clock-names = "ahb", "mod";
823 dmas = <&dma 23>, <&dma 23>;
824 dma-names = "rx", "tx";
825 resets = <&ccu RST_AHB1_SPI0>;
830 compatible = "allwinner,sun6i-a31-spi";
831 reg = <0x01c69000 0x1000>;
832 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
834 clock-names = "ahb", "mod";
835 dmas = <&dma 24>, <&dma 24>;
836 dma-names = "rx", "tx";
837 resets = <&ccu RST_AHB1_SPI1>;
842 compatible = "allwinner,sun6i-a31-spi";
843 reg = <0x01c6a000 0x1000>;
844 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
846 clock-names = "ahb", "mod";
847 dmas = <&dma 25>, <&dma 25>;
848 dma-names = "rx", "tx";
849 resets = <&ccu RST_AHB1_SPI2>;
854 compatible = "allwinner,sun6i-a31-spi";
855 reg = <0x01c6b000 0x1000>;
856 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
858 clock-names = "ahb", "mod";
859 dmas = <&dma 26>, <&dma 26>;
860 dma-names = "rx", "tx";
861 resets = <&ccu RST_AHB1_SPI3>;
865 gic: interrupt-controller@01c81000 {
866 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
867 reg = <0x01c81000 0x1000>,
871 interrupt-controller;
872 #interrupt-cells = <3>;
873 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
876 fe0: display-frontend@01e00000 {
877 compatible = "allwinner,sun6i-a31-display-frontend";
878 reg = <0x01e00000 0x20000>;
879 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
882 clock-names = "ahb", "mod",
884 resets = <&ccu RST_AHB1_FE0>;
887 #address-cells = <1>;
891 #address-cells = <1>;
895 fe0_out_be0: endpoint@0 {
897 remote-endpoint = <&be0_in_fe0>;
903 be0: display-backend@01e60000 {
904 compatible = "allwinner,sun6i-a31-display-backend";
905 reg = <0x01e60000 0x10000>;
906 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
909 clock-names = "ahb", "mod",
911 resets = <&ccu RST_AHB1_BE0>;
913 assigned-clocks = <&ccu CLK_BE0>;
914 assigned-clock-rates = <300000000>;
917 #address-cells = <1>;
921 #address-cells = <1>;
925 be0_in_fe0: endpoint@0 {
927 remote-endpoint = <&fe0_out_be0>;
932 #address-cells = <1>;
936 be0_out_drc0: endpoint@0 {
938 remote-endpoint = <&drc0_in_be0>;
945 compatible = "allwinner,sun6i-a31-drc";
946 reg = <0x01e70000 0x10000>;
947 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
949 <&ccu CLK_DRAM_DRC0>;
950 clock-names = "ahb", "mod",
952 resets = <&ccu RST_AHB1_DRC0>;
954 assigned-clocks = <&ccu CLK_IEP_DRC0>;
955 assigned-clock-rates = <300000000>;
958 #address-cells = <1>;
962 #address-cells = <1>;
966 drc0_in_be0: endpoint@0 {
968 remote-endpoint = <&be0_out_drc0>;
973 #address-cells = <1>;
977 drc0_out_tcon0: endpoint@0 {
979 remote-endpoint = <&tcon0_in_drc0>;
986 compatible = "allwinner,sun6i-a31-rtc";
987 reg = <0x01f00000 0x54>;
988 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
992 nmi_intc: interrupt-controller@01f00c0c {
993 compatible = "allwinner,sun6i-a31-sc-nmi";
994 interrupt-controller;
995 #interrupt-cells = <2>;
996 reg = <0x01f00c0c 0x38>;
997 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1001 compatible = "allwinner,sun6i-a31-prcm";
1002 reg = <0x01f01400 0x200>;
1005 compatible = "allwinner,sun6i-a31-ar100-clk";
1007 clocks = <&osc32k>, <&osc24M>,
1008 <&ccu CLK_PLL_PERIPH>,
1009 <&ccu CLK_PLL_PERIPH>;
1010 clock-output-names = "ar100";
1014 compatible = "fixed-factor-clock";
1019 clock-output-names = "ahb0";
1023 compatible = "allwinner,sun6i-a31-apb0-clk";
1026 clock-output-names = "apb0";
1029 apb0_gates: apb0_gates_clk {
1030 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1033 clock-output-names = "apb0_pio", "apb0_ir",
1034 "apb0_timer", "apb0_p2wi",
1035 "apb0_uart", "apb0_1wire",
1041 compatible = "allwinner,sun4i-a10-mod0-clk";
1042 clocks = <&osc32k>, <&osc24M>;
1043 clock-output-names = "ir";
1046 apb0_rst: apb0_rst {
1047 compatible = "allwinner,sun6i-a31-clock-reset";
1053 compatible = "allwinner,sun6i-a31-cpuconfig";
1054 reg = <0x01f01c00 0x300>;
1058 compatible = "allwinner,sun5i-a13-ir";
1059 clocks = <&apb0_gates 1>, <&ir_clk>;
1060 clock-names = "apb", "ir";
1061 resets = <&apb0_rst 1>;
1062 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1063 reg = <0x01f02000 0x40>;
1064 status = "disabled";
1067 r_pio: pinctrl@01f02c00 {
1068 compatible = "allwinner,sun6i-a31-r-pinctrl";
1069 reg = <0x01f02c00 0x400>;
1070 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1071 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1073 clock-names = "apb", "hosc", "losc";
1074 resets = <&apb0_rst 0>;
1076 interrupt-controller;
1077 #interrupt-cells = <3>;
1087 pins = "PL0", "PL1";
1088 function = "s_p2wi";
1092 p2wi: i2c@01f03400 {
1093 compatible = "allwinner,sun6i-a31-p2wi";
1094 reg = <0x01f03400 0x400>;
1095 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&apb0_gates 3>;
1097 clock-frequency = <100000>;
1098 resets = <&apb0_rst 3>;
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&p2wi_pins>;
1101 status = "disabled";
1102 #address-cells = <1>;